JPS6410644A - Manufacture of semiconductor device - Google Patents
Manufacture of semiconductor deviceInfo
- Publication number
- JPS6410644A JPS6410644A JP62167182A JP16718287A JPS6410644A JP S6410644 A JPS6410644 A JP S6410644A JP 62167182 A JP62167182 A JP 62167182A JP 16718287 A JP16718287 A JP 16718287A JP S6410644 A JPS6410644 A JP S6410644A
- Authority
- JP
- Japan
- Prior art keywords
- region
- buried layer
- type buried
- type
- layer
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/76—Making of isolation regions between components
- H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
- H01L21/76202—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using a local oxidation of silicon, e.g. LOCOS, SWAMI, SILO
- H01L21/76205—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using a local oxidation of silicon, e.g. LOCOS, SWAMI, SILO in a region being recessed from the surface, e.g. in a recess, groove, tub or trench region
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/027—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34
- H01L21/033—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising inorganic layers
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/74—Making of localized buried regions, e.g. buried collector layers, internal connections substrate contacts
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/76—Making of isolation regions between components
- H01L21/761—PN junctions
-
- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
- Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y10S148/00—Metal treatment
- Y10S148/117—Oxidation, selective
-
- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
- Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y10S148/00—Metal treatment
- Y10S148/151—Simultaneous diffusion
-
- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
- Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y10S148/00—Metal treatment
- Y10S148/163—Thick-thin oxides
Landscapes
- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Chemical & Material Sciences (AREA)
- Inorganic Chemistry (AREA)
- Element Separation (AREA)
Priority Applications (4)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP62167182A JPS6410644A (en) | 1987-07-02 | 1987-07-02 | Manufacture of semiconductor device |
US07/100,947 US4840920A (en) | 1987-07-02 | 1987-09-25 | Method of isolating a semiconductor device using local oxidation |
GB8722998A GB2206446B (en) | 1987-07-02 | 1987-09-30 | Method of manufacturing semiconductor device |
US07/342,086 US4897363A (en) | 1987-07-02 | 1989-04-24 | Method of manufacturing semiconductor device isolation |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP62167182A JPS6410644A (en) | 1987-07-02 | 1987-07-02 | Manufacture of semiconductor device |
Publications (1)
Publication Number | Publication Date |
---|---|
JPS6410644A true JPS6410644A (en) | 1989-01-13 |
Family
ID=15844946
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP62167182A Pending JPS6410644A (en) | 1987-07-02 | 1987-07-02 | Manufacture of semiconductor device |
Country Status (3)
Country | Link |
---|---|
US (2) | US4840920A (ja) |
JP (1) | JPS6410644A (ja) |
GB (1) | GB2206446B (ja) |
Cited By (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5365104A (en) * | 1993-03-25 | 1994-11-15 | Paradigm Technology, Inc. | Oxynitride fuse protective/passivation film for integrated circuit having resistors |
KR100777847B1 (ko) * | 2001-04-10 | 2007-11-21 | 에스. 오. 이. 떼끄 씰리꽁 오 냉쉴라또흐 떼끄놀로지 | 기판-층 절단 장치 및 이것에 관한 방법 |
Families Citing this family (16)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5310690A (en) * | 1988-10-31 | 1994-05-10 | Texas Instruments Incorporated | Method for forming integrated circuits having buried doped regions |
JP2504567B2 (ja) * | 1989-06-14 | 1996-06-05 | 株式会社東芝 | 半導体装置の製造方法 |
US5218224A (en) * | 1989-06-14 | 1993-06-08 | Kabushiki Kaisha Toshiba | Semiconductor device including inversion preventing layers having a plurality of impurity concentration peaks in direction of depth |
US5132765A (en) * | 1989-09-11 | 1992-07-21 | Blouse Jeffrey L | Narrow base transistor and method of fabricating same |
US5008207A (en) * | 1989-09-11 | 1991-04-16 | International Business Machines Corporation | Method of fabricating a narrow base transistor |
EP0434182B1 (en) * | 1989-12-22 | 2002-04-03 | Samsung Semiconductor, Inc. | Fabrication of buried layers in integrated circuits |
JPH0770629B2 (ja) * | 1990-03-20 | 1995-07-31 | 株式会社東芝 | 不揮発性半導体記憶装置の製造方法 |
US5451530A (en) * | 1990-12-21 | 1995-09-19 | Texas Instruments Incorporated | Method for forming integrated circuits having buried doped regions |
JP2748988B2 (ja) * | 1991-03-13 | 1998-05-13 | 三菱電機株式会社 | 半導体装置とその製造方法 |
US5135884A (en) * | 1991-03-28 | 1992-08-04 | Sgs-Thomson Microelectronics, Inc. | Method of producing isoplanar isolated active regions |
US5225377A (en) * | 1991-05-03 | 1993-07-06 | Honeywell Inc. | Method for micromachining semiconductor material |
JP2679683B2 (ja) * | 1995-04-28 | 1997-11-19 | 日本電気株式会社 | 半導体装置の製造方法 |
US5861339A (en) * | 1995-10-27 | 1999-01-19 | Integrated Device Technology, Inc. | Recessed isolation with double oxidation |
US5872392A (en) * | 1996-04-30 | 1999-02-16 | Nippon Steel Corporation | Semiconductor device and a method of fabricating the same |
AT2173U1 (de) * | 1997-06-19 | 1998-05-25 | Austria Mikrosysteme Int | Verfahren zur herstellung von begrenzten, dotierten teilgebieten in einem substratmaterial aus monokristallinem silizium |
US20040053439A1 (en) * | 2002-09-17 | 2004-03-18 | Infineon Technologies North America Corp. | Method for producing low-resistance ohmic contacts between substrates and wells in CMOS integrated circuits |
Citations (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS58111344A (ja) * | 1981-12-25 | 1983-07-02 | Hitachi Ltd | 半導体装置及びその製造方法 |
JPS6058637A (ja) * | 1983-09-12 | 1985-04-04 | Nec Corp | 半導体装置の製造方法 |
JPS62112340A (ja) * | 1985-11-11 | 1987-05-23 | Sony Corp | 半導体装置の製造方法 |
Family Cites Families (13)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
NL7204741A (ja) * | 1972-04-08 | 1973-10-10 | ||
US4168997A (en) * | 1978-10-10 | 1979-09-25 | National Semiconductor Corporation | Method for making integrated circuit transistors with isolation and substrate connected collectors utilizing simultaneous outdiffusion to convert an epitaxial layer |
US4168999A (en) * | 1978-12-26 | 1979-09-25 | Fairchild Camera And Instrument Corporation | Method for forming oxide isolated integrated injection logic semiconductor structures having minimal encroachment utilizing special masking techniques |
US4251300A (en) * | 1979-05-14 | 1981-02-17 | Fairchild Camera And Instrument Corporation | Method for forming shaped buried layers in semiconductor devices utilizing etching, epitaxial deposition and oxide formation |
US4373252A (en) * | 1981-02-17 | 1983-02-15 | Fairchild Camera & Instrument | Method for manufacturing a semiconductor structure having reduced lateral spacing between buried regions |
JPS57139965A (en) * | 1981-02-24 | 1982-08-30 | Toshiba Corp | Manufacture of semiconductor device |
US4381956A (en) * | 1981-04-06 | 1983-05-03 | Motorola, Inc. | Self-aligned buried channel fabrication process |
US4563227A (en) * | 1981-12-08 | 1986-01-07 | Matsushita Electric Industrial Co., Ltd. | Method for manufacturing a semiconductor device |
DE3149185A1 (de) * | 1981-12-11 | 1983-06-23 | Siemens AG, 1000 Berlin und 8000 München | Verfahren zur herstellung benachbarter mit dotierstoffionen implantierter wannen bei der herstellung von hochintegrierten komplementaeren mos-feldeffekttransistorschaltungen |
US4569698A (en) * | 1982-02-25 | 1986-02-11 | Raytheon Company | Method of forming isolated device regions by selective successive etching of composite masking layers and semiconductor material prior to ion implantation |
JPS5955052A (ja) * | 1982-09-24 | 1984-03-29 | Hitachi Ltd | 半導体集積回路装置の製造方法 |
US4637125A (en) * | 1983-09-22 | 1987-01-20 | Kabushiki Kaisha Toshiba | Method for making a semiconductor integrated device including bipolar transistor and CMOS transistor |
US4561172A (en) * | 1984-06-15 | 1985-12-31 | Texas Instruments Incorporated | Integrated circuit fabrication method utilizing selective etching and oxidation to form isolation regions |
-
1987
- 1987-07-02 JP JP62167182A patent/JPS6410644A/ja active Pending
- 1987-09-25 US US07/100,947 patent/US4840920A/en not_active Expired - Lifetime
- 1987-09-30 GB GB8722998A patent/GB2206446B/en not_active Expired - Lifetime
-
1989
- 1989-04-24 US US07/342,086 patent/US4897363A/en not_active Expired - Lifetime
Patent Citations (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS58111344A (ja) * | 1981-12-25 | 1983-07-02 | Hitachi Ltd | 半導体装置及びその製造方法 |
JPS6058637A (ja) * | 1983-09-12 | 1985-04-04 | Nec Corp | 半導体装置の製造方法 |
JPS62112340A (ja) * | 1985-11-11 | 1987-05-23 | Sony Corp | 半導体装置の製造方法 |
Cited By (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5365104A (en) * | 1993-03-25 | 1994-11-15 | Paradigm Technology, Inc. | Oxynitride fuse protective/passivation film for integrated circuit having resistors |
KR100777847B1 (ko) * | 2001-04-10 | 2007-11-21 | 에스. 오. 이. 떼끄 씰리꽁 오 냉쉴라또흐 떼끄놀로지 | 기판-층 절단 장치 및 이것에 관한 방법 |
Also Published As
Publication number | Publication date |
---|---|
US4897363A (en) | 1990-01-30 |
GB2206446A (en) | 1989-01-05 |
US4840920A (en) | 1989-06-20 |
GB2206446B (en) | 1991-04-24 |
GB8722998D0 (en) | 1987-11-04 |
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