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JPS5578568A - Manufacture of semiconductor device - Google Patents

Manufacture of semiconductor device

Info

Publication number
JPS5578568A
JPS5578568A JP15225878A JP15225878A JPS5578568A JP S5578568 A JPS5578568 A JP S5578568A JP 15225878 A JP15225878 A JP 15225878A JP 15225878 A JP15225878 A JP 15225878A JP S5578568 A JPS5578568 A JP S5578568A
Authority
JP
Japan
Prior art keywords
impurity
region
layer
film
yielded
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP15225878A
Other languages
Japanese (ja)
Inventor
Minoru Kawakami
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Mitsubishi Electric Corp
Original Assignee
Mitsubishi Electric Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Mitsubishi Electric Corp filed Critical Mitsubishi Electric Corp
Priority to JP15225878A priority Critical patent/JPS5578568A/en
Publication of JPS5578568A publication Critical patent/JPS5578568A/en
Pending legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/08Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
    • H01L29/083Anode or cathode regions of thyristors or gated bipolar-mode devices
    • H01L29/0839Cathode regions of thyristors

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Ceramic Engineering (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Bipolar Transistors (AREA)
  • Thyristors (AREA)
  • Electrodes Of Semiconductors (AREA)

Abstract

PURPOSE:To obtain electrodes having excellent ohmic contact by selectively forming the second impurity-diffused layer after the first impurity diffused layer has been formed on a semiconductor substrate, then, removing the first impurity-diffused layer, and forming metal electrodes on the exposed surfaces. CONSTITUTION:At the stage an n-type emitter layer 5 is formed on the surface of a p-type base layer 4, an impurity-density reduced region 6 is yielded on the surface of the layer 4, and an SiO2 film 7 is formed on the region 6. An impurity- density reduced region 8 is also yielded on the surface of a p-type emitter layer 2, and an SiO2 film 9 is formed on the region 8. Then, after the layers 5 and 4, the film 7 on the region 6, and the film 9 have been removed, the regions 6 and 8 are removed by lapping, etching, and the like; and the surfaces of the layers 4 and 2, which have a high impurity density, are exposed. Thereafter, metal electrodes are formed on both the exposed surfaces.
JP15225878A 1978-12-08 1978-12-08 Manufacture of semiconductor device Pending JPS5578568A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP15225878A JPS5578568A (en) 1978-12-08 1978-12-08 Manufacture of semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP15225878A JPS5578568A (en) 1978-12-08 1978-12-08 Manufacture of semiconductor device

Publications (1)

Publication Number Publication Date
JPS5578568A true JPS5578568A (en) 1980-06-13

Family

ID=15536541

Family Applications (1)

Application Number Title Priority Date Filing Date
JP15225878A Pending JPS5578568A (en) 1978-12-08 1978-12-08 Manufacture of semiconductor device

Country Status (1)

Country Link
JP (1) JPS5578568A (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS60182774A (en) * 1984-02-29 1985-09-18 Matsushita Electronics Corp Manufacture of fet
JP2004103763A (en) * 2002-09-09 2004-04-02 Fuji Electric Device Technology Co Ltd Method for manufacturing semiconductor device

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS60182774A (en) * 1984-02-29 1985-09-18 Matsushita Electronics Corp Manufacture of fet
JPH0654811B2 (en) * 1984-02-29 1994-07-20 松下電子工業株式会社 Method for manufacturing field effect transistor
JP2004103763A (en) * 2002-09-09 2004-04-02 Fuji Electric Device Technology Co Ltd Method for manufacturing semiconductor device

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