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JPS58197873A - Manufacture of semiconductor device - Google Patents

Manufacture of semiconductor device

Info

Publication number
JPS58197873A
JPS58197873A JP57079970A JP7997082A JPS58197873A JP S58197873 A JPS58197873 A JP S58197873A JP 57079970 A JP57079970 A JP 57079970A JP 7997082 A JP7997082 A JP 7997082A JP S58197873 A JPS58197873 A JP S58197873A
Authority
JP
Japan
Prior art keywords
region
poly
layer
oxidation
conductor
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP57079970A
Other languages
Japanese (ja)
Other versions
JPH0462179B2 (en
Inventor
Akihisa Uchida
明久 内田
Toshihiko Takakura
俊彦 高倉
Takashi Ishikawa
孝 石川
Nobuhiko Ono
大野 信彦
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Hitachi Ltd
Original Assignee
Hitachi Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hitachi Ltd filed Critical Hitachi Ltd
Priority to JP57079970A priority Critical patent/JPS58197873A/en
Publication of JPS58197873A publication Critical patent/JPS58197873A/en
Publication of JPH0462179B2 publication Critical patent/JPH0462179B2/ja
Granted legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10BELECTRONIC MEMORY DEVICES
    • H10B20/00Read-only memory [ROM] devices
    • H10B20/10ROM devices comprising bipolar components
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10BELECTRONIC MEMORY DEVICES
    • H10B20/00Read-only memory [ROM] devices
    • H10B20/20Programmable ROM [PROM] devices comprising field-effect components

Landscapes

  • Element Separation (AREA)
  • Bipolar Integrated Circuits (AREA)
  • Semiconductor Memories (AREA)
  • Electrodes Of Semiconductors (AREA)
  • Local Oxidation Of Silicon (AREA)

Abstract

PURPOSE:To prevent defects in laminated layers yielded in a poly Si oxidation process and to improve reliability of a semiconductor device, by exposing Si only in a region (walled emitter region) where poly Si is made to remain in the future before poly Si is deposited, and forming an oxide film on the other Si surface. CONSTITUTION:An N type epitaxial layer 3 is grown through an N<+> type embedded layer 2 on a P type Si substrate 1. An isolation oxide film 4 is formed down to the depth reaching the N<+> embedded layer 2. Photoetching is performed on the surface of a region I of the epitaxial layer surrounded by the oxide film layer 4. An N<+> diffused layer 5 is formed so as to reach the embedded layer 2. The poly Si film on the region I , wherein an Si3N4 film mask is not formed, is oxidized, and a poly Si oxide film 9 is formed. The side of the region I is covered by a mask. A P-base layer 10 is formed in the epitaxial layer in a region II through the poly Si film by boron ion implantation. Impurities for a Schottky barrier diode are introduced in the side of a surrounding region. Ion implantation is performed for forming an N<+> emitter 11 on the surface of the base layer in the region II. Hot etching is performed on the side of the region I .

Description

【発明の詳細な説明】 本発#4蝶、ポリ&i(多結晶シリコンノを使…するプ
ロセスkMする牛停体装置の製造法においてポリ81酸
化工梅での積層欠陥の発生音防止−rる蚊術に関するも
のでるる。
Detailed Description of the Invention This invention #4 Butterfly, Poly & I (polycrystalline silicone process) In the manufacturing method of the cow stopper device, the noise prevention of stacking faults in poly 81 oxidation process -r There is something about mosquito techniques.

半導体メモリ制電、−Jえばl 6 K P ROM 
(Pr −Ogramable Read 0nly 
Memory ) %の’El遺11Cνいて、ポリS
L’(使ってウォールドエミッタ偽造r形成している。
Semiconductor memory antistatic, -J 6K P ROM
(Pr-Ogramable Read ONLY
Memory) %'El remains 11Cν, polyS
L' (using walled emitter forgery r).

このウォールドエミッタ形成プロセスではメモリセルの
みにポリ5iifiし、+)a(M1辺s)OホlJ 
S i ktltl化り、テエツfングする工41il
kili2MJしている。周辺部のボIJ B 12歌
化しエツチングした部分の下地生部体表面には積層欠陥
か%生ずることか判明している。〜にこの周辺部i11
を域Vc次圓層【利用するショットキバリアダイオード
を形成する礪曾、b4IwI久陥のた欠陥(−メモリ装
置全体の歩w9の低下tひき起している。
In this walled emitter formation process, poly 5iifi is applied only to the memory cell, +) a (M1 side s) O hole J
41il
I'm doing kili2MJ. It has been found that stacking faults occur on the surface of the base material in the peripheral areas where the IJB 12 pattern has been formed and etched. 〜Niko peripheral area i11
In the area Vc, the second round layer [Using the Schottky barrier diode formation, b4IwI has a defect (--causing a decrease in the step W9 of the entire memory device).

この歩貿りはボIJ B 1−犀と酸化時1I111ν
C依仔し、酸化時1’lJ’lk増すはど積層欠陥の成
長か助長されることか実験でaMされた。
This trade is 1I111ν when oxidized with BoIJ B 1-Rhinoceros
Experiments have shown that increasing 1'lJ'lk during oxidation promotes the growth of stacking faults.

この発明の目的Fi、ポリS1ウオールドエミツタプロ
セスにおいて、ポリ81酸化工輸で発生する積層欠陥の
防止とそれによる生部体装置の18籾度向上にある。
The purpose of this invention is to prevent stacking faults that occur in the poly 81 oxidation process in the Fi, poly S1 wall emitter process, and thereby improve the graininess of the raw material.

この発明の一つのmましい形態t’;cmに赴べるフ゛
0セス16KFROM(ポリS1ウオールドエミツタプ
ロセス)に示すように積層欠陥を防止する目的でポリS
1デボ罰にポリB 1 t−将米慢丁−pjI城(ウォ
ールドエミッタ鎖酸)v)み81忙篇出し、その他t)
sirkJに酸化膜を形成しておき、ポリ81を欧化す
る工程で予め欧化1..t、J310 *かボIJ 8
1酸化時のポリ81から5IItlへのストレスt−h
aするバッファとして役立たせ積層欠陥か発生しないよ
うKする奄のである。
As shown in a 16KFROM (poly S1 wall emitter process) which can be applied to t';cm in one preferred embodiment of the present invention, polyS
Poly B 1 T-Shomai Arrogance-PJI Castle (Walled Emitter Chain Acid) v) Mi 81 busy edition, other T)
An oxide film is formed on sirkJ, and in the process of Europeanizing poly 81, Europeanization 1. .. t, J310 * Kabo IJ 8
Stress t-h from poly 81 to 5IItl during 1 oxidation
It serves as a buffer to prevent stacking defects from occurring.

以下実施ガにそって本発明を詳述する。The present invention will be described in detail below along with examples of implementation.

謳1図−) 〜(f)は本発明に16KFROMブo*
スに通用した場會の工相図を示す。同図Vこおいて、I
は崗辺領域(又はコレクタ)、Hはメモリ十ル@雛とな
るべき領域を示す。
Figure 1-) ~ (f) is a 16KFROM bus o* in the present invention.
This figure shows a construction phase diagram of a field that is commonly used in this field. In the same figure V, I
indicates the area (or collector), and H indicates the area that should become the memory space.

(uJp型81基&(8UB)l上にM”*埋込1曽2
に介してN番エピタキシャル鳩3虻成長さぜ、St<的
表th+酸化によってアイソレーション融化@(810
,)4t−M+埋埋込2に逼する深さまで形成する。こ
の酸化1$4でhまれ次エピタキシャル層のIIM I
 &血の酸化談rホトエッチしてリン轡のドナ不純物に
遇択循散することによりM 拡数層(ON)5’!に一
糠込層2に遍するように形成する。
(uJp type 81 units & (8UB) M”*embedded 1 so 2 on l
Growth of N epitaxial pigeon 3 through St < th + isolation melting by oxidation @ (810
, ) 4t-M+ form to a depth that fits the embedment 2. This oxidation is applied to the next epitaxial layer IIM I
& Blood oxidation story R photo-etched and selectively circulated into the donor impurity of the ring M Expansion layer (ON) 5'! It is formed so as to cover the entire nukakomi layer 2.

(b)  領*を責m<mい(:vooム)酸化−(s
to、)6y形成し、他方The1表面はエピタキシャ
ル層31m1出し几状聰で領域1.1lfillIVC
ポリ81%71デポジットする。
(b) Responsible for territory *m<m (:voom) oxidation -(s
to, )6y is formed, and on the other hand, on the surface of The1, an epitaxial layer 31m1 is exposed and a region 1.1lfillIVC is formed.
Poly 81% 71 Deposit.

(C)  ’WIIRif 衣圓VC−酊* 化マスク
トシテ81sNa Ill! br影形成る。
(C) 'WIIRif Kinen VC-drunk* kamasuktoshite81sNa Ill! brShadow formation.

〒 (d)  上記811焉編マスクの形成されない領域1
上のポリ81gkllk化してポリS1緻イと編9とす
る。
(d) Area 1 where the above 811 end mask is not formed
The above poly 81gkllk is made into poly S1 detailed and edition 9.

(8)  81sNalllk熱りン−等のエッチ液で
除去し友後、ボvs1tst化St−フッ識糸エッチ霞
で除去する。なお前記除化楓6及びボIJ8L@7はこ
のとき除去されない。
(8) After removing with an etchant such as 81sNalllk hot phosphorus, remove with a etchant such as 81sNalllk heat phosphorus, etc. Note that the above-mentioned removed Kaede 6 and Bo IJ8L@7 are not removed at this time.

(0この後、領域l關tマスクで稽い、領域」のエピタ
キシャル層にポリst−に通してボロンイオン打込みに
よるtペース層10に形成、父、図示されないか周辺領
域1IllKシヨツトキバリアダイオードのための必1
’:&不純1!FIm−専入、懺植■のベースMI表+
kuc)i+工にツタ11杉成のためのイオン打込みt
行ない、領域l−の酸化験6tホトエッチする。最後に
配酬工相に人9.111j11!ll1lのON層5に
1*ムl蒸看によるコレクタ電極を形成し、又領域11
1iにはポリ81層を弁してムl蒸mによるエミッタ電
極を形成スることになる。上記実J11tHのプロセス
仕様により実験した軸来、all−中)K示す1柳で領
域I−のst基*(エピタキシャル層)次面に0°N拡
e軒了後麺化議6忙エッチ除去して11C直接にボIJ
 81 kデボし、これ虻は化し友場合に基4ij衆面
に !!!! 表1に示すような積層欠陥か発生することか判明し友。
(After this, the epitaxial layer in the region 1 is removed using a mask, and a t-space layer 10 is formed by implanting boron ions through the epitaxial layer in the region 10, and the peripheral region 1IllK shot barrier diode (not shown) is formed by implanting boron ions. Must-have for
': & Impurity 1! FIm-Specialized, Printed Base MI Table+
kuc) Ion implantation for i+ construction for ivy 11 cedar formation
Then, the area l- is photoetched using an oxidation process of 6t. Finally, there is a person 9.111j11 for the remuneration minister! A collector electrode is formed on the ON layer 5 of ll1l by 1*mul vaporization, and the region 11 is
In step 1i, an emitter electrode is formed using a polyethylene 81 layer and vaporized. The experiment was carried out according to the process specifications of the actual J11tH above. Then 11C directly Bo IJ
81 K debo, this is a fly turned into a friend, and the base 4ij people face! ! ! ! It has been determined that stacking faults as shown in Table 1 occur.

この実験プロセス仕様では、0M拡散終了後、酸化−6
にエツチングし、基板5に直壷ポリ817rデボする。
In this experimental process specification, after the completion of 0M diffusion, oxidation-6
Then, a polygon 817r is directly deposited on the substrate 5.

この伏線で、ボ1J817敵化7ると、ポリ81デポ礁
厚2QOnIn、fi化時t&170分(100L)℃
、weto、)以下では積層欠陥は見られず、ポリ81
デボ−廖25t)nm、@化時間110分、及びポリ8
1デボa11廖350nsn、 H化時1&1240分
については、それぞれ半均2,5μm。
With this foreshadowing, when Bo 1J817 becomes enemy 7, poly 81 deposit reef thickness 2QOnIn, when fi becomes t & 170 minutes (100L) ℃
, weto, ) and below, no stacking faults were observed, and poly81
Debo-Liao 25t) nm, conversion time 110 minutes, and poly 8
1 debo a 11 liao 350 nsn, half average 2.5 μm for 1 & 1240 min during hydrogenation.

3.5μm9寸床の積層欠陥カム豪察され友。第2凶(
IL)(切<Q)に、その積増久wktボす。積層欠陥
の発住瓢因及びプロセス矯汗との関係kill討するた
めに、結晶基板にポ1J81[11デボし友ウェハ及び
基板81とポリ81との間にg□nmの#11/躾虻形
成したウェハを用いて、積層欠陥のポリ81−犀#鈑仕
時間・鹸化方法依存性を調べた。その横肘iI!I来を
纂3図に示す。横軸に、ボ17 S Lか酸化された後
の81基板の酸化−岸倉、縦軸VC1横層欠陥の寸法を
示す。ポ1J8L[ai基板に直接デボした場合には、
ポリ日1鱗厚・酸化方法にかかわらず、81基板の酸化
S*か増すにしたかつて積層欠陥か成長していくことか
わかる。また、81基板か約35nmlil化されると
欠陥か発生しはじめることか推定される。−万、ポリ8
1j直播81基仮にデポした場合に、81基板か110
0n噛化されると、1.6μmから2.1pmの欠陥か
発生するのに対して、すQnmの酸化a【は場んだ魯げ
には、81基板kloOnm絵化しても積層欠陥か発生
しないことかわかった。taxpaomの本仕様では、
ポリ81デボ績犀は200±2QnmポリB1象化(2
)時間[70分(tooo℃、 wsttOn  )で
める。本仕様において試作したロッ)1からロット8に
おいては積層久w!Iは1察されなかりた。しかし、ポ
リ81のデボII厚のばらつきr:211mすると、ポ
リ81デポ論厚は180mmから220mmまで変動し
、これにともなって、s1基板の酸化埃厚は22nmか
ら66nmのばらつき1生じるととになる。この範曲で
は、欠陥の発生する割合か高^。そこで、ON拡敏饋、
ホトレジエ4!!を追加して、(PSMホト)、ポリB
1酸化(?)時の積層欠陥の発生V防止するプロセス仕
様に褒貴し友。絽番図(IL)及び[有])に、それぞ
れ積層欠陥の蒙−j−及び酸化−rはさんだ場合の皺絢
釣針示す。
3.5 μm 9 inch floor stacking defect cam was discovered by a friend. Second evil (
IL) (Kiri<Q), its product increase Hisashi wkt voice. In order to eliminate the cause of stacking faults and their relationship with process sweating, a #11 debossing layer of g□nm was applied to the crystal substrate between the wafer and the substrate 81 and the poly 81. Using the formed wafers, the dependence of stacking faults on poly81-Rhin # plating time and saponification method was investigated. That side elbow II! The process is shown in Figure 3. The horizontal axis shows the oxidation-Kishikura of the 81 substrate after oxidation of Bo17SL, and the vertical axis shows the size of the VC1 horizontal layer defect. Po1J8L [If you debo directly onto the AI board,
Regardless of the polyscale thickness or oxidation method, it can be seen that the oxidation S* of the 81 substrate increases, indicating that stacking faults will continue to grow. Furthermore, it is estimated that defects will begin to occur when the 81 substrate is reduced to about 35 nm. - million, poly8
If 81 1j direct seeding units were deposited, 81 substrates or 110
When 0n is oxidized, defects of 1.6 μm to 2.1 pm occur, whereas stacking defects do not occur even when 81 substrates are made of kloOn. I understand that. In this specification of taxpaom,
Poly81 debossed rhinoceros is 200±2Qnm polyB1 (2
) time [70 minutes (tooo°C, wsttOn). In Lots 1 to 8, which were prototyped according to this specification, the lamination was long! I was not detected at all. However, if the variation r in the poly 81 deposit II thickness is 211 m, the poly 81 deposit theoretical thickness will vary from 180 mm to 220 mm, and along with this, the oxidized dust thickness of the s1 substrate will vary from 22 nm to 66 nm. Become. In this genre, the rate of defects occurring is high. Therefore, ON amplification,
Photoregie 4! ! Add (PSM photo), polyB
Congratulations on the process specification that prevents the occurrence of stacking faults during mono-oxidation (?). Figures (IL) and [Y]) show wrinkled fish hooks with stacking faults of oxide-j and oxidation-r, respectively.

以上夾JII−で述べた不発明によればボIJ B i
 i酸化するプロセスにおいて81基板表面に発生する
槓層久[−低賦し、待に問題となっているショットキバ
リアダイオード臀性不艮VCよる歩wり低下r防止」・
−歩留v化か期待する・         1本妬#4
はポリst2基板上に形成する牛導体装置の製造プロセ
スの丁べてkこ応用でさる。
According to the non-invention mentioned above in 夾JII-, BoIJB i
81 In the process of oxidation, the layer thickness generated on the surface of the 81 substrate is reduced, and the long-awaited problem of Schottky barrier diode failure due to VC is prevented.
-Expecting that the yield will change to v/1 jealousy #4
This is a comprehensive application of the manufacturing process for a conductor device formed on a poly ST2 substrate.

【図面の簡単な説明】[Brief explanation of drawings]

第11N(IL)〜(0は本発明によるメモリセル・プ
ロセスの工程lyT向図、lKZ図−)〜(0)は積場
欠陥発生状況を示す拡大平面図、第3図は積層欠陥の8
1基板頗化喚厚依存性菅示す曲縁図、謝4図−)(麹は
積層欠陥の形態を示す拡大平面図でるる。 1−Pa1!81J%板、2−N m埋込層、3・・・
Nmエピタキシャル層、4・・・アイソレーション酸化
−15・・・ON拡散層、6・・・鍮化娯、7・・・ボ
IJ 81験。 訃・・81.N4候、9・・・ポリB1酸化編、10・
・・Pベース、11・・・N 工(ツタ。 代1人 弁理士 薄 1)利 辛−1 第  1  図 1         1 第  2  図 (b) 第  3  図 、sl、a  の1mイclWl  (xm’)14図
No. 11N (IL) to (0 is a process lyT view of the memory cell process according to the present invention, lKZ diagram -) to (0) are enlarged plan views showing the stacking fault occurrence situation, and Fig. 3 is an enlarged plan view of the stacking fault 8.
1 Curved edge diagram showing the thickness dependence of the substrate, Figure 4-) (Koji is an enlarged plan view showing the morphology of stacking faults. 1-Pa1!81J% plate, 2-Nm buried layer, 3...
Nm epitaxial layer, 4... Isolation oxidation-15... ON diffusion layer, 6... Brass treatment, 7... Bo IJ 81 experiment. Death...81. N4 condition, 9... Poly B1 oxidation edition, 10.
...P base, 11...N Tsuta. 1 patent attorney Susuki 1) Ri Shin-1 1st Figure 1 1 Figure 2 (b) Figure 3, 1 m clWl of sl, a (xm ') Figure 14

Claims (1)

【特許請求の範囲】 !、#−俤体基体表面で多結晶午導体躾を款(Eする工
@At有するMP導体装置の製造法において、午導体!
!面に第1の酸化−を介して多鮎晶生部体−を形成し、
この多結晶手停体iisrm化して第2の酸化−とし、
この第2の酸化imrエッチ除去し、その後縞1の鹸化
i[t−エッチ除去することt〜値とする苧専体装置の
製造法。 2、牛導体基体表面で半辱体[il[[接に金緬電憔を
設ける第1の領域と生部体面に多結晶牛昏体映を介して
金属電極を設ける篤2の領域を形成するにめたって、第
1の領域の生部体懺歯に飢lの歇化編を形成した状緒で
絡1(Z)領域と繕2の領域上に多結晶牛専体膜【形成
し、絽lの輩域上の憂鮎^牛導体線を泗択的に酸化して
纂2の酸化機とし、この第2の版化11にエッチ除去し
、第2の領域の生部体内に多結晶牛導体績を通して不純
wJt停人し7を後、絽1の像域上の第112)瞭化暎
tエツ噴去し、第1のi!l廠とA2の一域上νC電惨
のためし)金属を形成するこ′と1特偵とTる生部捧装
ば区)製造法。
[Claims]! , #- In the manufacturing method of an MP conductor device having a polycrystalline conductor on the surface of the base body (E), the meridian conductor!
! forming polyacrylic crystalline parts on the surface through the first oxidation;
This polycrystalline IISRM is formed into a second oxidation,
This second oxidation imr etch is removed, and then the saponification of the stripe 1 is removed by the t~ value. 2. On the surface of the cow conductor substrate, form a first region where a metal electrode is provided in contact with the half body [il [[] and a second region where a metal electrode is provided on the live body surface through a polycrystalline body surface. In order to do this, a polycrystalline cow-specific film [formed] is formed on the tangle 1 (Z) region and the grooming 2 region in the state where a starvation patch has been formed on the dentition of the living part of the first region. , selectively oxidize the conductor wire on the area of the wire to form the second oxidizer, etch it away on this second plate 11, and inject it into the living body of the second area. Through the polycrystalline conductor record, the impurity wJt stops and after 7, the 112th) clear image on the image area of 紽1 is ejected, and the first i! In the area of 1 factory and A2, the νC electric disaster was carried out) to form metal and 1 special agent and T were dedicated to the production method.
JP57079970A 1982-05-14 1982-05-14 Manufacture of semiconductor device Granted JPS58197873A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP57079970A JPS58197873A (en) 1982-05-14 1982-05-14 Manufacture of semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP57079970A JPS58197873A (en) 1982-05-14 1982-05-14 Manufacture of semiconductor device

Publications (2)

Publication Number Publication Date
JPS58197873A true JPS58197873A (en) 1983-11-17
JPH0462179B2 JPH0462179B2 (en) 1992-10-05

Family

ID=13705171

Family Applications (1)

Application Number Title Priority Date Filing Date
JP57079970A Granted JPS58197873A (en) 1982-05-14 1982-05-14 Manufacture of semiconductor device

Country Status (1)

Country Link
JP (1) JPS58197873A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH07214008A (en) * 1993-10-12 1995-08-15 Elpatronic Ag Method and device for removing and separating bottle returned and recovered from circulating stream

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS55128861A (en) * 1979-03-28 1980-10-06 Hitachi Ltd Semiconductor integrated circuit device and method of fabricating the same
JPS5642367A (en) * 1979-09-14 1981-04-20 Toshiba Corp Manufacture of bipolar integrated circuit

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS55128861A (en) * 1979-03-28 1980-10-06 Hitachi Ltd Semiconductor integrated circuit device and method of fabricating the same
JPS5642367A (en) * 1979-09-14 1981-04-20 Toshiba Corp Manufacture of bipolar integrated circuit

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH07214008A (en) * 1993-10-12 1995-08-15 Elpatronic Ag Method and device for removing and separating bottle returned and recovered from circulating stream

Also Published As

Publication number Publication date
JPH0462179B2 (en) 1992-10-05

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