JPS5840852A - Complementary metal oxide semiconductor device and its manufacture - Google Patents

Abstract

PURPOSE:To prevent latch-up, and to fine the device by positioning an insulating layer at one side of an adjacent p layer or n layer isolated by the insulating layer and one part or all of the interface of a substrate while forming a p<+> layer under an isolation layer. CONSTITUTION:A resist mask 103 is shaped, the p<+> layers 104 are formed through ion implantation, Al 105 is stacked, and the isolation layers 106 are shaped through etching of SiO2 102 by masks 1052. The surface of the substrate is coated selectively with SiO2 108, poly Si 109 is stacked, the p layer 110 is molded by diffusion from the substrate through the irradiation of laser beams, and Si3N4 111 is deposited. The p layer 110 is etched through reactive ion etching while using Si3N4 111' remaining in a concave section as a mask, and the n layer 113 is shaped through the selective implantation of ions. When the CMOS device is manufactured according to a predetermined method, the complementary transistor is insulated by the films 106, a parasitic transistor is not formed, the device is not latched up, the surface of the element is flat, the degree of integration can be increased, and characteristics are also excellent.

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to an improvement in a complementary MO8 semiconductor device and a method for manufacturing the same.

As is well known, a complementary MO8 semiconductor device (hereinafter abbreviated as CMO8) has a p-channel Tr and an n-channel Tr formed on the same substrate. In particular, with the recent trend toward higher density and higher integration of OMO8, there is a demand for the establishment of miniaturization technology.

By the way, conventional OMO8 is manufactured by the method shown below.

First, a thermal oxide film 2 is grown on a silicon substrate 1 of, for example, an n-type (100) plane, and a resist pattern 3 is formed by photolithography from which a planned well area is removed.This is then used as a mask. For example, 100 keV, )
'-, the substrate It/Cd after ion implantation under the conditions of e amount 8.5X1012crIL-2? A ion-implanted layer 4 is formed (as shown in FIG. 1 (-)). Subsequently, the resist pattern 3 is removed, and the ion implantation layer 4 is heated at 1200° C., for example.
After thermally diffusing for 30 hours to form a p-well region 5 and removing the thermal oxide film 2 by etching, a thermal oxide film 6 and a silicon nitride film 7 are again formed in sequence (as shown in FIG. 1(b)).
Subsequently, the field portion of the silicon nitride film is selectively etched using photoetching technology to form silicon nitride film patterns 77h to 7e'5- (as shown in Figure 1 (0)).
.

Next, a resist mother turn 8 covering areas other than the p-well region 5 is formed by photolithography, and the resist J? For example, an apron is accelerated at a voltage of 40 keV and a dose of 8x using the matrix 78 and the silicon nitride film pattern 7b as a mask.
After ion implantation under the condition of lOan, thermal diffusion is performed to form a p+ layer 9 for preventing field reversal (first
Figure (d) (illustrated).

Subsequently, the resist pattern 8 is removed, and a renost pattern 10 covering the p-fer region 5 is again used by the photographic axis side method.
For example, +1 is formed using the resist arm main 10 and the silicon nitride [1) terres 77t and 7c as a mask.
．． 'Accelerate phosphorus at voltage 1OO)caV + dose 5×
After ion implantation under the conditions of 10-, thermal diffusion is performed to form an n+ layer 11 for preventing field reversal (as shown in FIG. 1(a)).

Subsequently, the resist layer 1o was removed, and selective oxidation was performed in a high-temperature Couette atmosphere using the silicon nitride film patterns 7a to 7c as oxidation-resistant masks to form a field oxide film 12 (as shown in FIG. 5-1(f)). ).

Next, a thermal oxide film is grown on the island-shaped n-type silicon substrate 1 region and the p-well region 5 separated by the field oxide film 12, a polycrystalline silicon film is further deposited, and phosphorus is diffused into this polycrystalline silicon layer. ◎Next, the polycrystalline silicon layer is patterned to form dirt electrodes '31+132, and using this as a mask, the thermal oxide film is etched to f-) Oxide film 141714. After forming ?, on the island-shaped substrate I region? Arsenic is added to the island-shaped p-well region 5,
P+ type source and drain regions 15 are formed by ion implantation, respectively.
1*161, n+ type source and drain regions 15. ．．
1B (as shown in FIG. 1(g)). After that, a CV'o-5to□ film 17 is deposited on the entire surface according to a conventional method, and contact holes 1111 to 184 are opened therein.
A/AI wiring 19-2 by film deposition and turning
2 to produce 0MO8 (as shown in FIG. 1(h))
.

However, the conventional method described above has the following drawbacks. That is, first, a parasitic pnp transnoster formed by the p+ type solo region Z51 (or drain region 161), the n type substrate 1, and the p− well region 5, and the parasitic pnp transistor formed by the p+ type source region Z51 (or drain region 161) and the p - Parasitic npn due to the well region 5 and the n-type substrate I) The latch-up phenomenon occurs due to the occurrence of a run star. The zero latch-up phenomenon is determined by the resistance of the substrate I and the shell region 5 and the arrival probability of minority carriers. Since the probability of arrival is determined by the distance between the n-channel and p-channel device regions, miniaturization makes it easier for latch-up to occur, leading to deterioration in device characteristics. Further, as shown in FIG. 1(b), the p-well region 5 extends not only in the depth direction of the substrate I but also in the lateral direction (for example, if it extends 10 μm in the direction of the substrate, it also extends 7 to 8 ILm in the lateral direction). , resulting in an obstacle to miniaturization and a decrease in the degree of integration. Furthermore, as shown in FIGS. 1(a) and 1(e), since ion implantation is performed to prevent field reversal of the n-channel and p-channel, the number of photo-etching steps, etc. increases, which becomes an obstacle to improving productivity.

The present invention has been made in order to eliminate the above-mentioned drawbacks, and includes: (1) a high-performance, highly integrated complementary MO8 semiconductor device that prevents the chirp phenomenon and miniaturizes the elements; Hereinafter, CMO8 of the present invention will be explained along with the manufacturing method shown in FIGS. 2(a) to (j).

[1] First, a p-type silicon substrate 101 with a surface index (100) was subjected to thermal oxidation treatment in a wet oxygen atmosphere at 1000° C. to grow a thermal oxide film (insulating film) 102 with a thickness of 1 μm.0Continued, A 7 Otresost film was applied to the entire surface, and resist patterns (mask materials) z03a and zO3b were formed by photolithography to cover the intended device area. Subsequently, the resist pattern 103a.

Using 103b as a mask, pyrone, which is an impurity for preventing inversion, is double charged at an acceleration voltage of 210 keV,
Ions are selectively implanted into the substrate 101 through the thermal oxide film 102 at a dose of 1 x 10 cm, and then heat treated to form a p
A + type inversion prevention layer 104 was formed (as shown in FIG. 2 (-)).
.

[11] Then, for example, coat A with a thickness of 2001 on the entire surface.
1 coating was vacuum deposited. At this time, as shown in FIG. 2(b), the resist patterns 1031L, 103b and the thermal oxide film 1
The Al film 1051 on the same patterns 103a and '103b and the Al film 1052 on the thermal oxide film 102 are discontinuous and separated due to the step difference from the resist pattern 103&, 103b. A above
l coating 1057. was lifted off to leave the AA film 10IH on the upper part of the thermal oxide film 102 in the intended element isolation region (as shown in FIG. 2(C)).
052 as a mask, the thermal oxide film 102 was selectively etched, for example by reactive ion etching, to form the element isolation region 106. Thereafter, the remaining A/coating 052 on the element isolation region 106 was removed (as shown in FIG. 2(d)).

At this time, two adjacent island-shaped substrate regions 107 . , 1072 were formed.

CIll) Next, the exposed substrate region 1071 is subjected to thermal oxidation treatment. 107. For example, after growing an oxide layer with a thickness of 100 OX, and removing the turtle layer on one substrate region 1071, a thin oxide layer Iθ8 was left in the free substrate region 1072. Next, an element isolation region 1 is formed on the entire surface.
A non-monocrystalline silicon layer, for example a polycrystalline silicon layer 109, having the same thickness as 06 was deposited. Subsequently, the entire surface of the polycrystalline silicon lii 7 o 9 was irradiated with an energy beam, such as a laser beam. At this time, as shown in FIG. 2(f), the polycrystalline silicon in direct contact with the p-type silicon substrate 1θ is single-crystalized using the substrate 101 as a crystal nucleus, and the entire layer becomes a p-type nested crystalline silicon layer 110. Ta.

[iv] Next, a plasma nitride film 111 was deposited on the entire surface of the single crystal silicon layer 110 (as shown in FIG. 20).
0Continuing, the glazma gold film 111 was treated by reactive ion etching. At this time, as shown in Figure 2 (h),
The etching rate of the plasma nitride film portion deposited in the recessed portion of the single crystal silicon layer 10-layer 110 is slower than that of the plasma nitride film portion deposited on the other flat silicon layer 110. A plasma nitride film 111' remained.

Subsequently, the single crystal silicon layer is selectively etched using the remaining plasma nitride film zzf as a mask to form element isolation region 1.
06, island-shaped substrate regions 101K, 107.
After leaving the p-type silicon layer only on the top, an oxide layer 1 is placed on the bottom.
For example, phosphorus is ion-implanted into the p-type single-crystal silicon layer where 08 does not exist, using the resist (not shown) turn as a mask, at an acceleration voltage of 200 k@V and a dose of 5 cm, and then heat-treated at, for example, 1100°C. An oxide layer 108 exists at the interface between a p-type element region 112 made of a p-type single crystal silicon layer and the substrate 101, and an n-type element region (n-well region) made of a single crystal silicon region converted to an n-type. 113 (as shown in FIG. 2 (1)).

[v] Next, p-type and n-type element regions IZ2゜11
3 is thermally oxidized to grow an oxide film with a thickness of 400×, a phosphorus-doped polycrystalline silicon film is further deposited on the entire surface, and this is patterned to selectively form dirt electrodes 1141 and 1142 on each element region 112 and 113. After forming these dirt electrodes 1141 and 1142 as a mask, the oxide film was etched to form r-to oxide films 1151+1152. Subsequently, arsenic and melon ions are implanted into the p-type element region 112 and the n-type element region 113, respectively, and heat-treated.
Type source and drain regions 1161+1171 yp+
Type source and drain regions 116. ．． 117° was formed. After that, after depositing CvD-8lO□ film 11B on the entire surface and opening contact holes 1191 to 1194,
AJ wiring 120 to 12 by vapor deposition and patterning of i film
3 was formed to produce 0MO8 (as shown in Figure 2 (J)).
0 As shown in FIG. 2(j), the 0MO8 of the present invention has an element isolation region 106 provided on a p-type silicon substrate 101, and an island-shaped substrate region 1071.101 separated by this element isolation region 106. p-type element region (n-channel Tr region) Iz2+n each consisting of a single crystal silicon layer
It has a structure in which a type element region (p-channel T, region) 113 is provided and a thin oxide layer 108 is interposed over the entire interface between the substrate 101 and the n-type element region 113. Therefore, since the n-channel Tr and the p-channel T are insulated by the thin oxide layer 108, no parasitic transistor is formed, and it is possible to obtain an 0MO8 having good device characteristics without the latch-up phenomenon caused by this. Further, the surfaces of the element isolation region 106 and the p-type and n-type element regions 112 and 113 are at the same level, and can be flattened.

Further, the n-type element region 113, which becomes a well region, is determined by the width between the element isolation regions 106, and lateral diffusion is prevented. Therefore, by preventing the latch-up phenomenon, flattening the device region, and preventing lateral diffusion in the well region, it is possible to obtain a high-density, high-integration 0MO8.

13- Also, a p+ type inversion prevention layer 104 is provided under the element isolation region 10B.
By providing this, it is possible to prevent malfunctions due to electrical leakage between the substrate 101 and the n-channel transistor formed in the p-type element isolation region 112 made of p-type nested crystalline silicon.

On the other hand, according to the method of the present invention, as shown in FIG. 2(1), the island-shaped substrate region separated by the element isolation region 10B has a p-type layer at approximately the same level as the surface of the element isolation region.

Element region 112° 113 made of n-type single crystal silicon
can be formed. Therefore, in the step [v], after the oxide film growth, the deposition of the phosphorous doped polycrystalline silicon film, the resist film coating, and the photolithography, it is possible to avoid the formation of resist residue at the end of the element isolation region 106. This makes it possible to form a resist pattern with good dimensional accuracy, which in turn makes it possible to form highly accurate dart electrodes 1141rZ142. Moreover, in the same [V] process, AA? When forming the wiring, each A wiring 1 is formed at the end of the element isolation region 106.
20 to 123 can be prevented from being cut off.

14- Also, the element region 112 of the n-channel Tr and the substrate 101
By forming the oxide layer 108 at the interface of
MO8 can be produced.

Furthermore, in the process of forming the element isolation region 106, bird's beaks do not occur as in the selective oxidation method, so that the element isolation region 106 can be miniaturized and the element regions 112, 113 can be made smaller.
It is possible to suppress the size reduction of , and to manufacture a highly integrated 0MO8. Moreover, since it is possible to prevent white ribbons from being generated in the element regions 112 and 113, the
MO8 can be obtained.

In addition, as in the above embodiment, a resist pattern 103* is formed on the thermal oxide film 102 in the intended element area.

Form 103b and use this as a mask? After forming the p+ type anti-inversion layer 104 by performing ion implantation of ions,
AI film deposition, resist pattern Iθ3*, 103b
AJ coating lift-off due to removal of AA' coating, residual AA' coating 1
By forming the element isolation region 106 by etching the thermal oxide film 102 using 052 as a mask, the element isolation region 106 and the anti-inversion layer 104 can be made into a self-line, and the element isolation region 106 can be formed from the anti-inversion layer 104 into the element region. Ions can be prevented from leaking into the source and drain regions.

In the above embodiment, a thermal oxide film was used as the insulating film, but the invention is not limited to this.
, 81, N4 film, AA'205 film, etc. may be used.

Also, amorphous silicon may be used instead of polycrystalline silicon as the non-monocrystalline silicon layer. In the above embodiment, a Radhe beam was used as the energy beam, but an electron beam, ion beam, etc. may also be used. In the above embodiment, ion implantation was used as a means to change the p-type single crystal silicon layer to n-type, but the method is not limited to this.
A method using an O film, A, or 5GPA as a diffusion source, a phosphorus diffusion method, or the like may be adopted.

In the above embodiment, an element isolation region is provided on a p-type substrate, a non-single-crystal silicon layer is coated, a p-type single-crystal silicon layer is formed by irradiation with an energy beam, and a p-type single-crystal silicon layer is formed between the element isolation regions by selective etching. Although the p-type single-crystal silicon layer in which the oxide layer exists was converted into an n-type (n-well region), the present invention is not limited thereto. For example, a p-type single crystal silicon layer without an oxide layer may be changed to an n-type layer.

Alternatively, one n-type single crystal silicon layer may be converted to a p-type (p-well region) using an n-type semiconductor substrate, contrary to the above.

In the above embodiment, an oxide layer was interposed on the entire interface between at least one of the element regions formed in two adjacent regions and the substrate, but a thin insulating layer such as an oxide layer was provided on a part of the interface. It is also possible to intervene. When partially interposed in this way, a high-performance, highly integrated 17-complementary MO8 semiconductor device in which elements are absolutely miniaturized at the interface near the other adjacent element region side, and such a semiconductor device. It is possible to provide a method for manufacturing by a simple process.

[Brief explanation of the drawing]

FIGS. 1(a) to (h) are process cross-sectional views showing the conventional manufacturing of 0MO8, and FIGS. 2(=) to (j) are process cross-sectional views showing the manufacturing of 0MO8 in an embodiment of the present invention. DESCRIPTION OF SYMBOLS 101... P-type silicon substrate, 102... Thermal oxide film (insulating film), 103a, 703b-... Resist pattern, 104... P+ type inversion prevention layer, 106... Element isolation region, 108... ...Oxide layer, 112...Element region made of p-type nested crystal silicon, IJ, 9...Element region made of n-type single crystal silicon, 114. 1142...Dart electrode, 1161.1162 ・
- Source area, 117. ．． 117□...Drain region, I2θ~123...kl wiring. Applicant's agent Patent attorney Takehiko Suzue 18-Φ ni01
two

Claims (1)

[Claims] 1. A semiconductor substrate of a first conductivity type, an element isolation region made of an insulating material provided on this substrate, and one of a plurality of island-shaped substrate regions separated by this element isolation region. a first conductivity type provided in at least two adjacent regions, respectively;
an element region made of a single crystal silicon layer of a second conductivity type, and a part of the interface between the semiconductor substrate and the element region of the first conductivity type, or between the substrate and the element region of the second conductivity type; Complementary MO8 semiconductor device 02, first conductivity type, second conductivity type, characterized in that an insulating layer is interposed throughout the entire structure, and a first conductivity type high concentration impurity layer is provided on the substrate surface under the element isolation region. Complementary MO8 semiconductor device 03 according to claim 1, characterized in that the surface of the element region made of a conductive type single crystal silicon layer is approximately at the same level as the surface of the element isolation region, the semiconductor substrate is Claim 1, characterized in that the device is p-type, and an insulating layer is interposed in part or all of the interface between the p-type substrate and the n-type single crystal silicon layer. Complementary MO8+- conductor device. 4. Forming an insulating film to serve as an element isolation region on a semiconductor substrate of a first conductivity type, and ion-implanting impurities of a first conductivity type through the insulating film into a portion of the substrate where an element isolation region is to be formed. a step of forming a conductive type high concentration impurity layer; a step of selectively etching away the insulating film to form an element isolation region on the high concentration impurity layer on the surface of the substrate; A step of partially or entirely forming an insulating layer sufficiently thinner than the element isolation region on at least one of two adjacent regions of a plurality of island-shaped substrate regions, and a step of depositing a non-single crystal silicon layer on the entire surface. , a step of irradiating the non-single crystal silicon layer with an energy beam to form a single crystal, and etching and removing the single crystal silicon layer near the element isolation region, and then forming an island-like substrate region provided with an insulating layer and adjacent thereto. doping one of the single crystal silicon layers remaining in the other regions with impurities of the second conductivity type to form device regions of the first conductivity type and the second conductivity type in at least two adjacent island-shaped substrate regions; 1. A method for manufacturing a complementary MO8 semiconductor device, comprising the steps of: 5. The semiconductor substrate is p-type, and at least two adjacent regions of the plurality of island-like substrate regions separated by the device isolation region are provided with an insulating layer that is sufficiently thinner than the device isolation region to become the n-type device region. Complementary fi M according to claim 4, characterized in that it is partially or entirely formed by
A method for manufacturing an O8 semiconductor device.