JPS5950542A - Manufacture of semiconductor device - Google Patents

Abstract

PURPOSE:To increase the performance and integration degree by a method wherein the influence by the impurity diffusion of a field inversion preventing region is eliminated by compensating the area of an element forming region for its reduction, and then the upper surface of a field oxide film and the surface of the element forming region are formed nearly into the same flat. CONSTITUTION:A thermal oxide film 12 is formed by thermally oxidizing a P type Si substrate 11. An Si nitride film 13 is deposited as an oxidation resistant film, and a photo resist pattern 14 is formed. An Si nitride film 13' is formed by selectively etching and removing the Si nitride film 13. Next, boron ion implanted layers 15 are formed. Field oxide films 16 are formed by performing thermal oxidation. The P<+> type field inversion preventing regions 17 are formed thereunder. The substrate 11 is exposed by etching treatment. A P type single crystal Si layer 18 is so deposited on an island form part of the substrate 11 as to be at the same height as the upper surface of the field oxide films 16.

Description

DETAILED DESCRIPTION OF THE INVENTION [Technical Field of the Invention] The present invention relates to a method for manufacturing a semiconductor device, and more particularly to an improvement in element isolation technology.

[Technical background of the invention]

A selective oxidation method is conventionally known as one of element isolation techniques for semiconductor devices. This method will be explained with reference to FIGS. 1(a) to (C). First, a thermal oxide film 2 and an antioxidizing film, such as a silicon nitride film, are sequentially formed on the surface of a P-type silicon substrate 1, for example.

Next, a photoresist pattern not shown as Ig+ is formed on the planned element formation region, and then the silicon nitride film is etched away using this photoresist pattern as a mask to form a silicon nitride film pattern 3. Continuing,
After the bottom resist pattern is used as a mask, a P-type impurity for field inversion 1E, such as boron, is ion-implanted to form a boron ion-implanted layer 4, and then the photoresist pattern is removed (as shown in FIG. 11(a)). Next, a thermal oxidation process is performed using the silicon nitride film pattern as an oxidation-resistant mask to form a field oxide film 5, and at the same time, the boron in the boron ion implantation layer 4 is drowsily activated to form P below the field oxide film 5. A mold field inversion prevention region 6 is formed (as shown in FIG. 1(b)). Next, the silicon nitride film pattern 3 and the thermal oxide film 2 are sequentially etched away to expose the substrate 1, and island-shaped element formation regions separated by the field oxide film 6 are formed (see FIG. 1). C) As shown).

In addition, in this step, after the silicon nitride film pattern 3 and the thermal oxide film 2 are sequentially etched away, a thermal oxidation treatment is performed again to form a thermal oxide film (so-called pre-oxide film) on the exposed surface of the substrate 1. The thermally chewed film may be removed by etching.

Thereafter, according to the usual process, for example, a MOS is placed in the element formation area.
) form transistors and memory.

[Problems with background technology]

The conventional selective oxidation method described above has the following problems.

(1, 1 When forming the field oxide film 6 shown in FIG. 1(b), the substrate 1 under the silicon nitride film pattern 3 is also partially oxidized, so the area of the element formation region is This is substantially smaller than the area of the region covered by 3. This means that, for example, in the cell part of an M○S dynamic memory, the capacitor surface area λ is reduced.
This results in a decrease in g capacitor capacity.

(2) Similarly, when forming the field leveling film 6 in the step shown in FIG. 1(b), boron in the boron ion implantation layer 4 formed in the step shown in FIG. 1(a) is deposited in the element formation region. Since the P+ group field inversion prevention region 6 is formed by diffusion in a small area, a so-called narrow channel effect occurs, which deteriorates the characteristics of devices to be formed later.

(3) Since the field oxide film 6 is formed by directly oxidizing the substrate 1, the upper surface of the field oxide film 6 and the direction toward the element formation region are not on the same plane as shown in FIG. 1(C), resulting in a step difference. As a result, when photoresist is applied in the subsequent construction of the Shushi-dam construction bridge, the thickness of the photoresist varies above and below the step, so the width of the photoresist pattern formed by exposure 11 differs above and below the step. leading to a decrease in the degree of

[Purpose of the invention]

The present invention compensates for the decrease in the area of the element formation region, eliminates the influence of impurity diffusion in the field inversion prevention region, and forms the upper surface of the field oxide film and the surface of the element formation region substantially on the same plane. The present invention aims to provide a method for manufacturing high-performance, highly integrated semiconductor devices.

[Summary of the invention]

The method for manufacturing a semiconductor device of the present invention is to form a single crystal semiconductor layer by selective epitaxial growth on an island-shaped semiconductor substrate region (conventional element formation region) quadrupled with field oxide films formed by a conventional selective oxidation method. is deposited to form an element forming region. This method can solve the problems of conventional selective oxidation methods.

[Embodiments of the invention]

An embodiment in which the method of the present invention is applied to manufacturing an MO8 type semiconductor device will be described below with reference to FIGS. 2(a) to 2(e).

First, a P-type silicon substrate 11 having a surface index of (100) was thermally annealed in a dry oxygen atmosphere to form a thermal oxide film 12 having a width of 19 degrees and a height of 900 degrees. Next, for example, L PCVD (
Low Pressure Chemica], Va
A silicon nitride film 13 having a thickness of 2500 mm was deposited as an oxidation-resistant film by the porDeposition method.

Subsequently, a photoresist pattern I4 was formed on the planned element formation area (as shown in FIG. 2(a)).

Next, using the photoresist pattern z4 as a mask, the silicon nitride film 13 was selectively etched away to form a silicon nitride film pattern 13'. Next, using the photoresist pattern 14 as a mask, boron was accelerated with an energy of 80 k to prevent field inversion.
ev, under the condition of dose 11 x 10”/bias 1,
Ions were implanted into the substrate 11 through the thermal oxide film 12 to form a boron ion implantation layer 15, and then the photoresist pattern I4 was removed (as shown in Figure 21'J (b)).

Next, the silicon nitride film pattern 1. A field oxide film 16 is formed by performing thermal oxidation treatment in a wet oxygen atmosphere at 1000'C using y' as an oxidation-resistant mask, and at the same time, boron in the boron ion implantation layer 15 is electrically activated to form a field oxide film. 16, a KP+ type field inversion prevention region 17 was formed (as shown in FIG. 2(C)).
.

Next, the silicon nitride JIIE pattern 13' and the thermal oxide film 12 are sequentially etched away to form the substrate 11.
exposed. Subsequently, thermal oxidation treatment was performed in a dry oxygen atmosphere to form a thermal oxidation film (not shown) on the exposed surface of the substrate 11 (so-called pre-oxidation film), and this thermal oxidation film was removed (Fig. 2(d) ).

Next, on the island-shaped substrate 11 portion exposed from the field oxide film 16, P-type nest crystal silicon nitride 8, which will become the element formation region, is deposited by selective epitaxial growth so as to be at the same height as the upper surface of the field oxide film 16. I did it (second
Figure (e) shown). Hereinafter, according to the usual manufacturing process, the above P
A device was formed on the mold cavity crystalline silicon layer 18, and a UOS type semiconductor device was manufactured.

According to the method described above, the following effects can be obtained. That is, in the conventional selective oxidation method, the area of the element formation region was smaller than the area of the silicon nitride film pattern, whereas in the method of the present invention, the area of the device formation region was smaller than the area of the silicon nitride film pattern, whereas in the process shown in FIG. As shown in FIG. 2(e), a P-type nested crystalline silicon layer 18 is deposited on portion 11 (conventional element forming area), so that the area of the element forming area and the area of the silicon nitride film pattern 13' are approximately the same. It can be done. Therefore, it is possible to compensate for the reduction in area of the conventional element formation region, for example, I
It is possible to prevent the capacitor container from decreasing in the JO'S dynamic memory cell. Figure 2 (e
), the seepage region of the P-type field inversion prevention region 17 becomes the device formation region in the P-type nested crystalline silicon layer 1.
8, it is possible to prevent the characteristics of the if OS transistor from deteriorating due to the so-called narrow channel effect. Furthermore, Figure 2 (e
), the upper surface of field oxide film I6 and 24 m (single crystal silicon 7118 surface) are formed on approximately the same plane, and there is no difference in level between them, which improves the patterning accuracy of the photoresist and facilitates the following device manufacturing process. For example, the dimensional accuracy of the gate electrode or contact hole of a transistor (for example, IJOS) can be improved, and breakage of the twisted metal wiring can be prevented.

Note that in the above embodiment, the P-type nest crystal silicon layer 418
Although it is formed to have the same height as the upper surface of the field oxide film 16, the P-type nested crystalline silicon layer 18 may be formed thinner or thicker as long as the difference in level between the two does not cause any adverse effects.

Further, in the above-mentioned sister example, a silicon nitride film was used as the oxidation-resistant film, but A/20. Membrane 1. WO, membrane, etc. may also be used.

Furthermore, in the above embodiment, a P-type silicon substrate is used to create a UOS.
Although a type semiconductor device has been manufactured, it goes without saying that an N type silicon nail plate may be used, and a bipolar type semiconductor device can also be applied to the next manufacturing process.

〔Effect of the invention〕

According to the present invention, the reduction in area of the element formation region is compensated for, the influence of impurity diffusion in the field inversion prevention region is eliminated, and the top surface of the field oxide film and the surface of the element formation region are made substantially on the same plane. Accordingly, it is possible to provide a method for manufacturing a high-performance, highly integrated semiconductor device.

[Brief explanation of the drawing]

FIGS. 1(a) to (C) are cross-sectional views showing a method for manufacturing a semi-solid device using a conventional selective oxidation method (VC), and FIGS. 1 is a diagram illustrating the manufacturing method of a semiconductor device in Example V in the order of its steps. 11... P-type silicon substrate, 12... Thermal oxide film, 1
3... Silicon nitride film, 13'... Silicon nitride film pattern, 14... Photoresist pattern, No. 5...
・Boron ion implantation G116...field oxide film,
17...: P type field inversion prevention area, 18...
・P-type nest crystal silicon order. Figure 1 Figure 2

Claims (1)

[Claims] forming an insulating film on the surface of a semiconductor substrate of one conductivity type;
A step of forming an oxidation-resistant film pattern on the insulating film corresponding to the planned element formation region, and ionizing impurities of the same conductivity type as the substrate in areas other than the region covered with the oxidation-resistant film pattern. A step of implanting a field oxide film by performing thermal oxidation using the oxidation-resistant film pattern as a mask, and a step of sequentially removing the oxidation-resistant film pattern and the insulating film to form a part of the substrate. 1. A method for manufacturing a semiconductor device, comprising the steps of: exposing a substrate; and depositing a single crystal semiconductor layer on the exposed substrate by selective epitaxial growth.