JPS58173830A - Manufacture of semiconductor device - Google Patents
Manufacture of semiconductor deviceInfo
- Publication number
- JPS58173830A JPS58173830A JP5769882A JP5769882A JPS58173830A JP S58173830 A JPS58173830 A JP S58173830A JP 5769882 A JP5769882 A JP 5769882A JP 5769882 A JP5769882 A JP 5769882A JP S58173830 A JPS58173830 A JP S58173830A
- Authority
- JP
- Japan
- Prior art keywords
- region
- contact
- layer
- region layer
- type
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 title claims description 6
- 238000004519 manufacturing process Methods 0.000 title claims description 3
- 229910052796 boron Inorganic materials 0.000 claims abstract description 12
- -1 boron ions Chemical class 0.000 claims abstract description 7
- 238000002513 implantation Methods 0.000 claims abstract description 3
- 230000015572 biosynthetic process Effects 0.000 claims description 5
- 238000000034 method Methods 0.000 abstract description 7
- ZOXJGFHDIHLPTG-UHFFFAOYSA-N Boron Chemical compound [B] ZOXJGFHDIHLPTG-UHFFFAOYSA-N 0.000 abstract description 5
- 239000011248 coating agent Substances 0.000 abstract description 2
- 238000000576 coating method Methods 0.000 abstract description 2
- 238000009792 diffusion process Methods 0.000 abstract description 2
- 239000000758 substrate Substances 0.000 abstract 1
- 229910052782 aluminium Inorganic materials 0.000 description 9
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 9
- 238000010438 heat treatment Methods 0.000 description 7
- 238000005468 ion implantation Methods 0.000 description 7
- 238000000206 photolithography Methods 0.000 description 6
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 5
- 229910052710 silicon Inorganic materials 0.000 description 5
- 239000010703 silicon Substances 0.000 description 5
- 239000012535 impurity Substances 0.000 description 4
- 230000000694 effects Effects 0.000 description 2
- 229910052751 metal Inorganic materials 0.000 description 2
- 239000002184 metal Substances 0.000 description 2
- 238000007740 vapor deposition Methods 0.000 description 2
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 description 1
- 206010011732 Cyst Diseases 0.000 description 1
- 229910052802 copper Inorganic materials 0.000 description 1
- 239000010949 copper Substances 0.000 description 1
- 208000031513 cyst Diseases 0.000 description 1
- 238000005553 drilling Methods 0.000 description 1
- 230000001747 exhibiting effect Effects 0.000 description 1
- 230000003647 oxidation Effects 0.000 description 1
- 238000007254 oxidation reaction Methods 0.000 description 1
- 238000004544 sputter deposition Methods 0.000 description 1
- XLYOFNOQVPJJNP-UHFFFAOYSA-N water Substances O XLYOFNOQVPJJNP-UHFFFAOYSA-N 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
Landscapes
- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Electrodes Of Semiconductors (AREA)
Abstract
Description
【発明の詳細な説明】
この発明はP影領域層に安定したオーミックコンタクト
抵抗をもつコンタクト領域を形成する半導体装置に関す
るものである。DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a semiconductor device in which a contact region having stable ohmic contact resistance is formed in a P shadow region layer.
従来P影領域1へのオーミックコンタクトはP影領域層
をN形シリコン層中に形成し、同時に形成する熱酸化膜
もしくはその後の酸化膜生成で形成する酸化膜等の一部
に既知の写真製版技術を用いC穴をあけP影領域の表面
を露出させ、しかるのちたとえばアルミニウムを蒸着法
あるも)ζよス、fツタリング法により表面に付着せし
めアルミニウム峻を形成し、さらに既知の写真製版技術
を用いC所定の内F4i1r’、線パターンを形成し、
さらにこののちP形コンタクト領域層と内部配線金属で
ある例えばアルミニウムのオーミックコンタクトをせい
ぜい600”Cまでの熱処理をおこなうことにより“C
形成する。Conventionally, ohmic contact to the P shadow region 1 is made by forming a P shadow region layer in an N type silicon layer, and using known photolithography to form part of the thermal oxide film formed at the same time or the oxide film formed by subsequent oxide film formation. The surface of the P shadow area is exposed by drilling a C hole using a technique, and then, for example, aluminum is deposited on the surface by a vapor deposition method or by a tuttering method to form an aluminum slope, and further by a known photolithography technique. Use C to form a line pattern within the predetermined range F4i1r',
Furthermore, after this, the P-type contact region layer and the internal wiring metal, such as aluminum ohmic contacts, are heat-treated to a temperature of 600"C at most.
Form.
普通必要とするP影領域層は100Ω/口〜1000V
口であり、P形不純物濃度はlXl0”cllsの表面
濃度を有しCいる。安定したオーεツウコンタクトを形
成するには4X101’I:111以上のP形不純物表
面#度がのぞましくこれよりも表面濃度が低い場合はコ
ンタクト抵抗値のばらつきが大きく、コンタクト抵抗値
が不安定である。Normally required P shadow area layer is 100Ω/mouth ~ 1000V
The surface concentration of the P-type impurity is 1X10''clls.To form a stable Oε2 contact, the P-type impurity surface concentration of 4X101'I:111 or more is desirable. When the surface concentration is lower than this, the variation in contact resistance value is large and the contact resistance value is unstable.
このため従来のP影領域層はコンタクト抵抗値の不安定
さをさけるために、不純物の少ない低濃度領域層を形成
する場合のコンククト部へは表面′a度を高くするため
に高濃度領域域を特別に形成することが必要であるとい
う欠点があった。For this reason, in order to avoid instability of the contact resistance value, in the conventional P shadow region layer, when forming a low concentration region layer with few impurities, a high concentration region layer is used to increase the surface a degree. The disadvantage is that it requires special formation.
この発明は上記のような従来のものの欠点を除去するた
めになされたもので、コンタクト抵抗値の低い安定した
コンタクト領域をもつ半導体装1dを提供することを目
的としCいる。The present invention has been made to eliminate the drawbacks of the conventional devices as described above, and its object is to provide a semiconductor device 1d having a stable contact region with a low contact resistance value.
例えば、この発明の一例におい°Cは、P形領域層へ内
皿配線を用いたオーミックコン・タクトを形成するため
、P形領域中の該コンタクト領域以外を注入マスクで保
護し、該コンタクト領域にボロンをイオン注入したのち
、ひきつづき内皿配線を形成し、該コンタクト領域への
ボロンイオン注入後は600℃以上の熱処理を実施しな
いので、P影領域層中に内部配線層とのコンタクト領域
層を形成する。For example, in one example of the present invention, in order to form an ohmic contact to the P-type region layer using inner plate wiring, the P-type region other than the contact region is protected with an implantation mask, and the contact region is After implanting boron ions into the contact region, the inner plate wiring is subsequently formed, and heat treatment at 600°C or higher is not performed after the boron ion implantation into the contact region. form.
以下、この発明の一実施例を図につい゛C説明する。図
におい’r、+1)はN形シリコン層であり、(2)は
その中に形成されるP形領域層である。P形領域層の形
成はよく知られた写真製版方法と拡散方法とを用いC例
えばボロンを拡散することでおこなう。酸化膜(3)は
P形層形成詩の熱処理、またはその後の酸化膜生成等に
よつ°C形成したものである。写真製版方法によりレジ
スト(4)を塗布したのちP形領域層の表面にコンタク
ト領域(6)をあける。Hereinafter, one embodiment of the present invention will be explained with reference to the drawings. In the figure, 'r, +1) is an N-type silicon layer, and (2) is a P-type region layer formed therein. The P-type region layer is formed by diffusing C, for example boron, using well-known photolithography and diffusion methods. The oxide film (3) is formed at °C by heat treatment to form a P-type layer or subsequent oxide film formation. After applying a resist (4) by photolithography, a contact region (6) is formed on the surface of the P-type region layer.
あるいはまた、すでに酸化膜(3)にあけ°Cあるコン
タクト領域+5)に写真製版方法によりレジスト(4)
全塗布し、必要なP形領域層のコンタクト領域(6)の
みを露出させ、他のN形領域層のコンタクトまたは不要
なP水高濃度表面不純物層をレジストでおおい、イオン
注入マスクにする。Alternatively, the resist (4) can be applied to the contact area +5) which has already been opened in the oxide film (3) by photolithography.
After coating the entire layer, only the necessary contact region (6) of the P-type region layer is exposed, and the contact of other N-type region layers or unnecessary P water high concentration surface impurity layer is covered with resist, and used as an ion implantation mask.
ひきつづい゛Cボロンをイオン注入法により例えば50
KeV で10”n 打ち込む。打ち込みにあたツ°
U L/ シスト(4> トM化!!3)は所定のコン
タクト領域以外には注入するボロンイオンが到達しない
厚み、たとえば酸化膜(3)のみなら0.5μm程度、
また酸化1漠(3)がないならばレジスト(4)はl、
#m程度の厚みになるようにあらかじめ設定し°Cおく
。Subsequently, for example, 50% of C boron is added by ion implantation.
Drive 10”n at KeV.
U L/ Cyst (4> M!!3) has a thickness that prevents boron ions to be implanted from reaching areas other than the predetermined contact area, for example, if it is only the oxide film (3), it is about 0.5 μm,
Also, if there is no oxidation (1) (3), the resist (4) is l,
Set the thickness in advance to about #m and leave at °C.
イオン注入後はレジストが使用し°Cあれば除去し、表
面を清浄にしたのち熱処理をせずただちにたとえばアル
ミニウムを蒸着法あるいはスパッタリング法でつけ写真
製版技術でパターンを形成する。その後はじめCたとえ
ば460℃で熱処理をする。After ion implantation, if the resist is used, it is removed at °C, the surface is cleaned, and without heat treatment, for example, aluminum is immediately applied by vapor deposition or sputtering, and a pattern is formed by photolithography. Thereafter, heat treatment is first performed at, for example, 460°C.
以上の方法で製造されたP形領域層の表面は、イオン注
入によっ°c汲西面接触金属のコンタクト性が容易にと
りやすくなり1表面濃度の低いP影領域でもイオン注入
後の熱処理をおこなわずにアルitA形成後に400℃
から450 ℃で熱処理をすることにより安定し・た抵
いコンタクト抵抗を示すコンタクト領域を形成すること
ができる。The surface of the P-type region layer manufactured by the above method can be easily contacted with the contact metal on the west side by ion implantation, and heat treatment after ion implantation can be performed even in the P shadow region with a low surface concentration. 400℃ after AlitA formation
By performing heat treatment at temperatures ranging from 450° C. to 450° C., a contact region exhibiting stable contact resistance can be formed.
また上記実施例では配線−?Lb4はアルミニウムであ
ったが、これはシリコンを含んすごアルミニウムやまた
銅とシリコンを含んだアルミニウムなど一種以七の令喘
を含むアルミニウムの場合でも同様な効果をもつもので
ある。Also, in the above embodiment, the wiring -? Although Lb4 was aluminum, the same effect can be obtained in the case of aluminum containing one or more types of aluminum, such as aluminum containing silicon or aluminum containing copper and silicon.
以上のようにこの発明によれば、P形の低#度領域層へ
コンタクト領域を形成するのに高fIIIf領域層を必
要とせず、P形領域靭のコンタクト領域にボロンイオン
注入をおこなうのみで新たな熱処 □理を必要とせず
、容易に安定したコンタクト抵抗を持つコンタクト領域
が得られる51JJ果がある。As described above, according to the present invention, a high fIIIf region layer is not required to form a contact region in a P-type low-# region layer, and boron ions are only implanted into a contact region in a P-type region. New heat treatment □There is a 51JJ effect that allows a contact region with stable contact resistance to be easily obtained without the need for treatment.
図面は本発明の一実施例を示す半導体装{者の断面図で
ある。
図においr fl)はN形シリコン7F+、+2)はP
形領域層、(3)は酸化膜、(4)はレジスト、(5)
はコンタクト領域、↑印はボロンイオン注入がおこなわ
れる状態を示すO
代理人 葛 野 信 −
手続補正書(自発)
1.+j許庁長官殿
1、 1G件の表示 特願昭57−87698号
2、発明の名称
半導体装置の製造方法
3、補正をする者
6、 @正の対象
明細書の発明の詳細な説明の欄および図面の簡単な説明
の欄
6、補正の内容
(1)明細書中筒2頁第8行に「lXl0”am−”
J トhるのを[lXl0−”cIll−”〜lXl0
1・C11−”J&’lT正−する。
(2)同第8頁第9行に「実施しないので、」とあるの
を「実施せず、」と訂正する。
(3)同第6頁第8行に「↑印」とあるのを「↓印」と
訂正する。
以上The drawing is a sectional view of a semiconductor device showing an embodiment of the present invention. In the figure, r fl) is N-type silicon 7F+, +2) is P
shape region layer, (3) is oxide film, (4) is resist, (5)
indicates the contact area, and the ↑ mark indicates the state where boron ion implantation is performed. +J Dear Commissioner of the License Agency 1, Indication of 1G Patent Application No. 1987-87698 2, Name of the invention Method for manufacturing a semiconductor device 3, Person making the amendment 6, @Detailed description of the invention in the original subject specification and column 6 of the brief explanation of the drawings, contents of amendment (1) “lXl0”am-” in line 8 of page 2 of the central cylinder of the specification.
J Toru no [lXl0-"cIll-"~lXl0
1.C11-"J&'ITCorrect-. (2) On page 8, line 9 of the same page, correct the phrase "because it will not be implemented," to read "it will not be implemented." (3) In the 8th line of page 6, the ``↑ mark'' should be corrected to ``↓ mark.''that's all
Claims (1)
注入マスクで保護し該コンタクト領域にボロンをイオン
注入し′Cコンタクト領域を形成した後、内部配線を形
成することを特徴とする半導体装1stの製造方法。1. A first method of manufacturing a semiconductor device, which comprises protecting the Pt1J1 layer other than the ohmic contact formation region with an implantation mask, implanting boron ions into the contact region to form a C contact region, and then forming internal wiring.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP5769882A JPS58173830A (en) | 1982-04-05 | 1982-04-05 | Manufacture of semiconductor device |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP5769882A JPS58173830A (en) | 1982-04-05 | 1982-04-05 | Manufacture of semiconductor device |
Publications (1)
Publication Number | Publication Date |
---|---|
JPS58173830A true JPS58173830A (en) | 1983-10-12 |
Family
ID=13063151
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP5769882A Pending JPS58173830A (en) | 1982-04-05 | 1982-04-05 | Manufacture of semiconductor device |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPS58173830A (en) |
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH0750304A (en) * | 1994-04-15 | 1995-02-21 | Nippondenso Co Ltd | Semiconductor device |
Citations (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS5763507A (en) * | 1980-10-06 | 1982-04-17 | Seiko Epson Corp | Printer head driven by liquid crystal |
JPS5719947B2 (en) * | 1979-08-31 | 1982-04-26 | ||
JPS5770569A (en) * | 1980-10-20 | 1982-05-01 | Seiko Epson Corp | Imaging method |
-
1982
- 1982-04-05 JP JP5769882A patent/JPS58173830A/en active Pending
Patent Citations (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS5719947B2 (en) * | 1979-08-31 | 1982-04-26 | ||
JPS5763507A (en) * | 1980-10-06 | 1982-04-17 | Seiko Epson Corp | Printer head driven by liquid crystal |
JPS5770569A (en) * | 1980-10-20 | 1982-05-01 | Seiko Epson Corp | Imaging method |
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH0750304A (en) * | 1994-04-15 | 1995-02-21 | Nippondenso Co Ltd | Semiconductor device |
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