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DE69423299D1 - Serien-Parallel-Umsetzer mit Pseudozufallsrauschgenerator - Google Patents

Serien-Parallel-Umsetzer mit Pseudozufallsrauschgenerator

Info

Publication number
DE69423299D1
DE69423299D1 DE69423299T DE69423299T DE69423299D1 DE 69423299 D1 DE69423299 D1 DE 69423299D1 DE 69423299 T DE69423299 T DE 69423299T DE 69423299 T DE69423299 T DE 69423299T DE 69423299 D1 DE69423299 D1 DE 69423299D1
Authority
DE
Germany
Prior art keywords
pseudo
series
random noise
parallel converter
noise generator
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
DE69423299T
Other languages
English (en)
Other versions
DE69423299T2 (de
Inventor
Ryuji Ishida
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp filed Critical NEC Corp
Application granted granted Critical
Publication of DE69423299D1 publication Critical patent/DE69423299D1/de
Publication of DE69423299T2 publication Critical patent/DE69423299T2/de
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Classifications

    • GPHYSICS
    • G06COMPUTING; CALCULATING OR COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F7/00Methods or arrangements for processing data by operating upon the order or content of the data handled
    • G06F7/38Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation
    • G06F7/48Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation using non-contact-making devices, e.g. tube, solid state device; using unspecified devices
    • G06F7/57Arithmetic logic units [ALU], i.e. arrangements or devices for performing two or more of the operations covered by groups G06F7/483 – G06F7/556 or for performing logical operations
    • GPHYSICS
    • G06COMPUTING; CALCULATING OR COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F7/00Methods or arrangements for processing data by operating upon the order or content of the data handled
    • G06F7/58Random or pseudo-random number generators
    • G06F7/582Pseudo-random number generators
    • G06F7/584Pseudo-random number generators using finite field arithmetic, e.g. using a linear feedback shift register
    • GPHYSICS
    • G06COMPUTING; CALCULATING OR COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F2207/00Indexing scheme relating to methods or arrangements for processing data by operating upon the order or content of the data handled
    • G06F2207/58Indexing scheme relating to groups G06F7/58 - G06F7/588
    • G06F2207/581Generating an LFSR sequence, e.g. an m-sequence; sequence may be generated without LFSR, e.g. using Galois Field arithmetic
    • GPHYSICS
    • G06COMPUTING; CALCULATING OR COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F2207/00Indexing scheme relating to methods or arrangements for processing data by operating upon the order or content of the data handled
    • G06F2207/58Indexing scheme relating to groups G06F7/58 - G06F7/588
    • G06F2207/583Serial finite field implementation, i.e. serial implementation of finite field arithmetic, generating one new bit or trit per step, e.g. using an LFSR or several independent LFSRs; also includes PRNGs with parallel operation between LFSR and outputs

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Theoretical Computer Science (AREA)
  • Computational Mathematics (AREA)
  • Mathematical Analysis (AREA)
  • Mathematical Optimization (AREA)
  • Pure & Applied Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • Computing Systems (AREA)
  • Analogue/Digital Conversion (AREA)
DE69423299T 1993-11-26 1994-11-28 Serien-Parallel-Umsetzer mit Pseudozufallsrauschgenerator Expired - Fee Related DE69423299T2 (de)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP5296515A JPH07154214A (ja) 1993-11-26 1993-11-26 ディジタル信号処理回路

Publications (2)

Publication Number Publication Date
DE69423299D1 true DE69423299D1 (de) 2000-04-13
DE69423299T2 DE69423299T2 (de) 2000-07-20

Family

ID=17834543

Family Applications (1)

Application Number Title Priority Date Filing Date
DE69423299T Expired - Fee Related DE69423299T2 (de) 1993-11-26 1994-11-28 Serien-Parallel-Umsetzer mit Pseudozufallsrauschgenerator

Country Status (4)

Country Link
US (1) US5506796A (de)
EP (1) EP0656583B1 (de)
JP (1) JPH07154214A (de)
DE (1) DE69423299T2 (de)

Families Citing this family (12)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5696828A (en) * 1995-09-22 1997-12-09 United Technologies Automotive, Inc. Random number generating system and process based on chaos
US6201870B1 (en) * 1997-03-20 2001-03-13 Massachusetts Institue Of Technology Pseudorandom noise sequence generator
US6128681A (en) * 1997-08-07 2000-10-03 Avid Technology, Inc. Serial to parallel and parallel to serial, converter for a digital audio workstation
JP2980576B2 (ja) * 1997-09-12 1999-11-22 株式会社東芝 物理乱数発生装置及び方法並びに物理乱数記録媒体
US6285873B1 (en) * 1998-03-09 2001-09-04 Qualcomm Incorporated Method for generating a broadcast challenge value
DE60219155T2 (de) * 2002-07-22 2007-12-13 Texas Instruments Inc., Dallas Verfahren und Einrichtung zur Phasenjustierung zweier Taktsignale
EP1385308B1 (de) * 2002-07-22 2007-03-28 Texas Instruments Limited Verfahren und Einrichtung für die parallele Synchronisation von mehreren seriellen Datenströmen
JP4131937B2 (ja) * 2003-03-26 2008-08-13 株式会社東芝 テスト機能を有する論理回路
US8862900B2 (en) * 2010-01-08 2014-10-14 The Research Foundation For The State University Of New York Secure distributed storage system and method
US11128094B2 (en) * 2018-09-28 2021-09-21 Maxim Integrated Products, Inc. Pin encoded mode selection system
DE102019111805A1 (de) 2019-05-07 2020-11-12 OSRAM Opto Semiconductors Gesellschaft mit beschränkter Haftung Verfahren zum erzeugen eines pwm-signals und schaltung zum erzeugen eines pwm-signals
CN113539343B (zh) * 2021-07-28 2022-04-26 北京微纳星空科技有限公司 一种移位寄存器的多路输出方法、装置、设备及存储介质

Family Cites Families (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4531022A (en) * 1983-01-13 1985-07-23 International Standard Electric Corporation Device for generating binary digit pseudo-random sequences
GB8507613D0 (en) * 1985-03-23 1985-05-01 Int Computers Ltd Testing digital integrated circuits
JPS62261970A (ja) * 1986-05-09 1987-11-14 Mitsubishi Electric Corp 診断装置
DE3639577A1 (de) * 1986-11-20 1988-05-26 Siemens Ag Logikbaustein zur erzeugung von ungleich verteilten zufallsmustern fuer integrierte schaltungen
JPS63176021A (ja) * 1987-01-16 1988-07-20 Nec Corp 直列並列変換回路
JP2805301B2 (ja) * 1987-04-06 1998-09-30 クラリオン株式会社 擬似ランダム雑音符号発生器
US5105376A (en) * 1990-08-08 1992-04-14 Vlsi Technology, Inc. Linear feedback shift registers
JP2841882B2 (ja) * 1991-02-04 1998-12-24 日本電気株式会社 疑似乱数パタン発生器
JPH06182014A (ja) * 1992-12-21 1994-07-05 Matsushita Electric Works Ltd ゴルフ練習場

Also Published As

Publication number Publication date
EP0656583A1 (de) 1995-06-07
JPH07154214A (ja) 1995-06-16
EP0656583B1 (de) 2000-03-08
DE69423299T2 (de) 2000-07-20
US5506796A (en) 1996-04-09

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Legal Events

Date Code Title Description
8364 No opposition during term of opposition
8339 Ceased/non-payment of the annual fee