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CN1019720B - 半导体功率器件 - Google Patents

半导体功率器件

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CN1019720B
CN1019720B CN91101845A CN91101845A CN1019720B CN 1019720 B CN1019720 B CN 1019720B CN 91101845 A CN91101845 A CN 91101845A CN 91101845 A CN91101845 A CN 91101845A CN 1019720 B CN1019720 B CN 1019720B
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buffer layer
withstand voltage
composite buffer
power device
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CN1056018A (zh
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陈星弼
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3d Semiconductor Ltd By Share Ltd
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University of Electronic Science and Technology of China
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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/60—Insulated-gate field-effect transistors [IGFET]
    • H10D30/64—Double-diffused metal-oxide semiconductor [DMOS] FETs
    • H10D30/66—Vertical DMOS [VDMOS] FETs
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D10/00—Bipolar junction transistors [BJT]
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D12/00—Bipolar devices controlled by the field effect, e.g. insulated-gate bipolar transistors [IGBT]
    • H10D12/211—Gated diodes
    • H10D12/212—Gated diodes having PN junction gates, e.g. field controlled diodes
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/60—Insulated-gate field-effect transistors [IGFET]
    • H10D30/64—Double-diffused metal-oxide semiconductor [DMOS] FETs
    • H10D30/66—Vertical DMOS [VDMOS] FETs
    • H10D30/668—Vertical DMOS [VDMOS] FETs having trench gate electrodes, e.g. UMOS transistors
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D62/00—Semiconductor bodies, or regions thereof, of devices having potential barriers
    • H10D62/10—Shapes, relative sizes or dispositions of the regions of the semiconductor bodies; Shapes of the semiconductor bodies
    • H10D62/102—Constructional design considerations for preventing surface leakage or controlling electric field concentration
    • H10D62/103—Constructional design considerations for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse-biased devices
    • H10D62/105—Constructional design considerations for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse-biased devices by having particular doping profiles, shapes or arrangements of PN junctions; by having supplementary regions, e.g. junction termination extension [JTE] 
    • H10D62/109—Reduced surface field [RESURF] PN junction structures
    • H10D62/111—Multiple RESURF structures, e.g. double RESURF or 3D-RESURF structures
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D8/00—Diodes
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D62/00—Semiconductor bodies, or regions thereof, of devices having potential barriers
    • H10D62/10—Shapes, relative sizes or dispositions of the regions of the semiconductor bodies; Shapes of the semiconductor bodies
    • H10D62/113—Isolations within a component, i.e. internal isolations
    • H10D62/115—Dielectric isolations, e.g. air gaps
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D62/00—Semiconductor bodies, or regions thereof, of devices having potential barriers
    • H10D62/10—Shapes, relative sizes or dispositions of the regions of the semiconductor bodies; Shapes of the semiconductor bodies
    • H10D62/113—Isolations within a component, i.e. internal isolations
    • H10D62/115—Dielectric isolations, e.g. air gaps
    • H10D62/116—Dielectric isolations, e.g. air gaps adjoining the input or output regions of field-effect devices, e.g. adjoining source or drain regions
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D62/00—Semiconductor bodies, or regions thereof, of devices having potential barriers
    • H10D62/10—Shapes, relative sizes or dispositions of the regions of the semiconductor bodies; Shapes of the semiconductor bodies
    • H10D62/17—Semiconductor regions connected to electrodes not carrying current to be rectified, amplified or switched, e.g. channel regions
    • H10D62/393—Body regions of DMOS transistors or IGBTs 

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Abstract

含有一个P+区与n+区之间的耐压区的半导体功率器件，其特性是用包括有二种导电类型的材料相间排列组成的复合缓冲层(CB层)的耐压区代替了以往的一种导电类型的耐压区。本发明还提供了复合缓冲层不同图形的设计规范。采用本发明可以得到性能优良的各类新结构的半导体功率器件。器件单位面积的导通电阻与击穿电压的关系为Ron∝V1.3。所以采用本发明在改善导通电阻Ron(或正向正降)与器件耐压的矛盾方面有了重要突破。

Description

该发明属于半导体功率器件技术领域。
众所周之，现有半导体功率器件的耐压是靠一层较轻掺杂的单一导电类型的半导体材料（可以是外延或其它技术制成），这里称它为耐压区。对于高压功率器件，导通电阻（或正向压降）主要是由这耐压区决定。耐压区的耐压能力与它的掺杂浓度及厚度有关，浓度愈低，厚度愈大，则耐压愈高，但是导通电阻（或正向压降）则愈大。耐压高与导通电阻（或正向压降）小是功率器件的主要矛盾。例如，功率MOSFET中目前技术最先进的是RMOS（或称UMOS），其结构示意图见图1，它的耐压区是一层n-外延层，其单位面积导通电阻Ron∝V2.5 B，VB为器件所需的耐压，也就是n-外延层所需的最小耐压能力。功率MOSFET的耐压与导通电阻的关系见参考资料：（1）C.F.Wheatley，G.M.Dolny，Solid-State Technology，Nov.1985，PP.121-128;（2）C.Hu，IEEE Trans.Electron Devices，Vol.ED-26，No.3，PP.243-246（1979）;（3）D.Ueda，H.Takagi，G.Hano，IEEE Trans.Electron Devices，Vol.ED-34，PP.926-930（1987）;（4）H.R.Chang，R.D.Black et al.，IEEE Trans.Electron Devices，Vol.ED-34，PP.2329-2333（1987）。另外，有一美国专利：（5）Goodman et al.，United States Patent，4，366495，Dec.28，1982，在VDMOS的导通电阻Ron的改善方面有了进展，但是，没有超出极限关系Ron∝V2.5 B。当要求VB增加时，n-外延层掺杂浓度要降低、厚度要增加，则Ron随VB以2.5次方上升，这在高压 功率领域是很不利的。另一方面，纵向导电型功率器件的耐压区中，总有相间的区域对导电几乎没有贡献。例如，垂直导电的功率MOSFET的源极下方的区域;双极型晶体管的基极电极条下方的区域等。
本发明的任务在于提供一种新型结构的耐压区（这里称复合缓冲层：Com-posite    Buffer，缩写CB），在CB层上再制作功率器件，这样可以得到性能更优良的各类功率器件，其耐压与导通电阻的极限关系建立在一个新的基础上，可以大大缓解导通电阻（或正向压降）与器件耐压的矛盾。
依据发明的任务，本发明提供了新结构的耐压区，它是用包括有两种导电类型的材料相间排列组成的复合缓冲层（CB层）的耐压区代替以往的一种导电类型的耐压区。即在p+区相接的平面与n+区界面之间有p区与n区交替组合而成的复合缓冲层，复合缓冲层中的每个p区与每个n区均有与上述两个面相交的交接面，除这两个交接面外，复合缓冲层的每个p区被相邻的n区包围，每个n区被相邻的p区包围，如图2所示。这样，在CB层耗尽时，两种导电类型的材料（p区和n区），提供符号相反的电荷，其产生的电场大部分被互相抵消，这就使得p区及n区的掺杂浓度可高于通常的耐压区，而其导通电阻低于通常的耐压区。
CB层的p区与n区的安排方式称为其结构图形。这种图形可以是：1）条状，即叉指式，在CB层的横截面上，每个长条状n区的两旁是p区，反之亦然;2）六角形单元或方形单元或长方形单元或三角形单元的并接，在CB层的横截面上六角形或方形或长方形或三角形单元实行密堆集，每个单元的中央是圆形，或六角形，或方形，或长方形，或三角形的n区（或p区），其它部分是p区（或n区）;3）镶嵌式，在CB层的横截面上，p区及n区都是方形，或都是正三角形，或都是正六角形，p区与n区间隔排列。图3示意地示出这三种图形的 各一个例子。在各种图形中，p区及n区的尺寸（宽度或半径）愈小，则导通电阻愈低。而且各p区及各n区面积应近于相等，以得到最小的导通电阻。
本发明提供CB层的设计方法如下：如果要求耐压为VB〔伏〕，则CB层的厚度应为0.024V1.2 B〔微米〕。对于条状图形，当n区及p区的宽度相等为b〔微米〕;n区的有效施主浓度及p区的有效受主浓度均为7.2×1016·V-0.2 B/b[厘米-3]。对于方形镶嵌式结构图形，如每区的宽度为b[微米〕，则n区的有效施主浓度及p区的有效受主浓度均为9.1×1016·V-0.2 B/b〔厘米-3〕。对于其它图形，当每个n区及每个p区面积相等为A〔微米2〕时，有效施主及有效受主浓度为8.7×1016·V-0.2 B/√A。
本发明提供的上述浓度设计规则是为了得到最低的单位面积导通电阻Ron对条状图形，这时Ron＝6×10-7·b·V1.3 B〔欧姆·厘米2〕;对于方形镶嵌式结构图形，这时Ron＝4.7×10-7·b·V1.3 B。实际制造所得p区及n区杂质浓度如高于所给值，则击穿电压下降;如低于所给值，则导通电阻增加。
和上述设计规则有关的特征是，本发明要求n区有效施主总电荷与p区有效受主总电荷相等或接近，两种电荷相对差别如超过50%，则同样CB层厚度下的耐压明显下降。根据器件结构的要求和工艺条件的限制，n区和p区的横截面积的大小可以不等，或可以相等，但n区和p区的有效杂质总量应满足上述要求。
本发明提供的CB层，其中n区与p区之间並不需要载流子流动，因此也可以在每个n区和p区之间有介质层隔开，两个区中的电荷产生的电场仍然可以大部分相互抵消。另一方面，如果器件结构要求CB层中的n区为导电区，则CB层中的p区与n+之间可以有介质隔开;如果器件结构要求CB层中的p区为导电区，则n区与p+区之间可以有介质层相隔。这样既不影响CB层的导电能力，又对器件的耐压有利，同时对减小寄生效应也有利。
本发明还提出比上述均匀掺杂的n区及p区更优越的掺杂结构，可达到导 通电阻比上述方法再低25%。这种结构是在均匀掺杂的基础上再有一附加的杂质浓度梯度，它使n区靠近n+区处的施主浓度大于靠近p+区的，p区靠近n+区处的受主浓度小于靠近p+区的。这时CB层的厚度对条状图形应为0.019V1.2 B〔微米〕，对其它图形应为0.017V1.2 B〔微米〕，浓度梯度之值对条状图形为3.0×1020V-2.6 B〔厘米-4〕，对其它图形为4.6×1020·V-2.6 B〔厘米-4〕。
发明人对耐压区复合缓冲层结构的主要寄生效应：结型场效应管（JFET）效应进行了全面的计算，结果表明，复合缓冲层结构的夹断电流密度远远大于一般功率器件的工作电流密度，这说明寄生的JFET效应对本发明的器件的优越性並无明显的影响。
在本发明提供的复合缓冲层上，制作各种类型的功率器件，可以得到性能优良的各类新结构功率器件。
本发明提供了新结构的垂直导电型功率MOSFET，在p区和n区相间排列的复合缓冲层上，根据要求，制作各种结构的功率MOSFET。如图4所示的CB-RMOS结构;图5所示的CB-VDMOS结构;图6所示的CB-VVMOS结构，这些结构这里统称为复合缓冲层MOS管（CBMOS）。
本发明提供的另一类是双极型功率器件，其中一种是高压二极管结构（称为CB-Diode），如图7所示;另一种是高压双极型功率晶体管（称为CB-Bipolar），如图8所示。
本发明提供的第三类是复合缓冲层静电诱导晶体管（CB-SIT），在复合缓冲层上再外延和制作静电诱导结构，其栅可以采用埋栅，也可以是表面栅，如图9所示的是带复合缓冲层的表面栅静电诱导晶体管。
本发明提供的复合缓冲层耐压结构，除了可用于上述所列几类功率器件外，还可用于其它种类的功率器件，如晶闸管等，而且随着科学技术的发展， 在本发明所提供的复合缓冲层结构上可制出更多的新型功率器件。
本发明所提供的各类新结构的功率器件，由于耐压区为复合缓冲层结构，它由p区和n区相间排列而构成，因此有显著的优点。当外加电压使缓冲层耗尽时，p型区受主电荷与n型区施主电荷产生的电场大部分相抵消，因此，这两区对电场的作用接近于一个本征层的作用，从而在厚度相同的情况下，不仅耐压可以提高，而且掺杂浓度可以提高，使导通时电阻大大下降。
经过对CB-RMOS（图4所示）结构进行详细深入的理论计算，表明单位面积的导通电阻与击穿电压的关系为Ron∝V1.3 B，而原来结构的RMOS，其Ron∝V2.5 B。此外，本发明的单位面积的Ron与p区（及n区）的宽度b成正比，因此，随着微细加工技术的进步，Ron还可以不断减小。可见，本发明在改善导通电阻Ron（或正向压降）与器件耐压的矛盾方面有了突破，例如一个800V的带复合缓冲层结构的RMOS，在现在工艺水平下按本发明的均匀杂质分布，Ron只有原结构的百分之四，如按本发明的优化梯度分布，Ron只有原来结构的百分之二点八。
由于以上优点，使得具有本发明所提供的复合缓冲层结构的功率器件具有耐压高，导通电阻（或正向压降）小等特点，从而也可缓解其它参数的设计矛盾，得到高性能的各类功率器件。
本发明的附图说明：
图1是现有技术的RMOS结构示意图;
图2是本发明提供的复合缓冲层（CB层）耐压结构;
图3是本发明提供的CB层横截面上的几个典型图形。其中，图3-1为条状结构，图3-2为六角形结构，图3-3为方形镶嵌式结构。
图4是本发明的一种实施例-CB-RMOS单元结构剖面示意图;
图5是本发明的另一种实施例-CB-VDMOS单元结构剖面示意图;
图6是本发明第三种实施例-CB-VVMOS单元结构剖面示意图;
图7是本发明第四种实施例-CB二极管（CB-Diode）结构图;
图8是本发明第五种实施例-CB-Bipolar单元结构剖面图;
图9是本发明第六种实施例-CB-SIT单元结构图。
下面依据图1～图9对本发明作进一步的描述。
图1是现有技术制作的RMOS，它是在n+（或p+）衬底4上外延n-（或p-）层5，然后扩散形成p区（或n区）3，再掩蔽扩散或离子注入n+（或p+）2，接着进行开垂直槽，和进行栅氧化1，最后做金属电极D、S、G。
图2是本发明提供的复合缓冲层结构，实现的方法：一是n+（或p+）衬底4上外延一层n（或p）5，然后在5上进行选择开垂直槽，再进行外延填充p（或n），把槽填满;二是在衬底4上外延5后，利用中子照射，将部分区域的n（或p）嬗变成p（或n），形成n区6和p区7相间排列的复合缓冲层。在复合缓冲层上根据需要制作p+（或n+）区8。
图3是本发明所提供的复合缓冲层横截面上的几个典型图形，其中图3-1为条状结构，6为n区（或p区），7为p区（或n区）;图3-2为六角形结构，6为n区（或p区）、7为p区（或n区）;图3-3为方形镶嵌式图形，6为n区（或p区），7为p区（或n区）。
图4是本发明的一种最适合的实施例，称CB-RMOS，在衬底n+（或p+）4上外延n（或p）5，将5按图2的方法制成复合结构，其中6为n区（或p区），7为p区（或n区），再在5上外延或扩散一层p（或n）区3，然后进行源区2扩散或离子注入-n+（或p+），再开垂直槽，然后栅氧化1，最后做金属电极。其元胞图形可以是条状、方形、六角、三角、圆形等。其中6区与7区之 间可以有介质相隔，7区与4区之间也可以有介质相隔。
图5是本发明又一实施例，CB-VDMOS单元结构，制作方式与图4结构基本相同，只是不用开槽工艺，同样6区与7区之间可以有介质相隔，7区与4区之间也可以有介质相隔。
图6是本发明实施的带复合缓冲层的VVMOS（CB-VVMOS）结构单元，制作步骤和方法与图4的基本上一样，不同点是开槽工艺，这里开的是V形槽，这是利用不同晶向的异向腐蚀速率而得。
图7是本发明实施的复合缓冲层高压二极管（CB-Diode）示意图，在衬底n+（或p+）4上制作复合缓冲层5，其中6与7为二种不同导电类型的区域，掺杂较轻，然后扩散形成p+（或n+）区8，再上下做金属电极。
图8是本发明实施的带复合缓冲层的双极型晶体管（CB-Bipolar）结构示意图。衬底n+（或p+）4，外延后制作复合缓冲层5，其中6为n-（或p-）区，7为p-（或n-）区，然后扩散外基区p+（或n+）9，接着扩散内基区p区（或n区）10，然后扩散或注入形成发射区n+（或p+）区11，最后进行金属电极工艺。
图9是本发明实施的带复合缓冲层的静电诱导晶体管（CB-SIT），只是以表面栅结构为例，其中复合缓冲层制作与图2相同，在此基础上形成p+（或n+）区12，然后形成n+（或p+）区13，最后制作金属电极。
上述各实施例中的7与4之间可以有介质层相隔，6与7之间也可以有介质层相隔。

Claims (17)

1、半导体功率器件，它包括有一个P+区与n+区之间的耐压区，其特征在于：所述的耐压区中，在P+区相接的平面与n+区界面之间有由P区与n区交替组合而成的复合缓冲层，复合缓冲层中每个p区与每个n区均有与上述两个面相交的交接面，除这两个交接面外，不论复合缓冲层的结构图形如何，其中的每个p区被相邻的n区包围，每个n区被相邻的p区包围。
2、根据权利要求1所述的半导体功率器件，其特征在于：所述的耐压区的复合缓冲层中，n区有效施主总电荷与p区有效受主总电荷相对差别不超过50%。
3、根据权利要求2所述的半导体功率器件，其特征在于：所述耐压区的复合缓冲层中每个n区和每个p区的杂质分布是均匀的。
4、根据权利要求2所述的半导体功率器件，其特征在于：所述耐压区的复合缓冲层中每个n区和每个p区的杂质分布是不均匀的，其中，n区靠近n+区处的施主浓度大于靠近p+区的施主浓度，p区靠近p+区的受主浓度大于靠近n+区的受主浓度。
5、根据权利要求3所述的半导体功率器件，其特征在于：当耐压要求为VB〔伏〕、复合缓冲层结构图形为条状图形、其中n区与p区有同样宽度b（以微米计）时，则复合缓冲层厚度为0.024V1.2 B，〔微米〕，n区的有效施主浓度与p区的有效受浓度均为7.2×1016V-0.2 B/b〔厘米-3〕。
6、根据权利要求3所述的半导体功率器件，其特征在于，当耐压要求为VB〔伏〕、结构图形为方形镶嵌式，复合缓冲层中p区与n区有同样宽度b（以微米计）时，则复合缓冲层的厚度为0.024V1.2 B，〔微米〕，复合缓冲层每一区的有效杂质浓度为7.2×1016V-0.2 B/b〔厘米-3〕。
7、根据权利要求3所述的半导体功率器件，其特征在于：当耐压要求为VB〔伏〕，结构图形为三角形单元、六角形单元、圆形单元，并接而成时，则复合缓冲层的厚度为0.024V1.2 B，〔微米〕，复合缓冲层中p区与n区面积相等，每一区的有效杂质浓度为7.2×1016V-0.2 B/b〔厘米-3〕，其中b为每个区面积的平方根。
8、根据权利要求4所述的半导体功率器件，其特征在于：当耐压要求为VB〔伏〕，结构图形为条状图形，复合缓冲层中n区与p区有同样宽度b（以微米计）时，所述的每个n区和每个p区杂质分布不均匀，杂质浓度含一常数部分及一个线性部分，其常数部分为7.2×1016V-0.2 B/b〔厘米-3〕，其线性部分之梯度为3.0×1020V-0.2 B/b〔厘米-4〕，这时，复合缓冲层的厚度为0.019V1.2〔微米〕。
9、根据权利要求4所述的半导体功率器件，其特征在于：当耐压要求为VB〔伏〕，结构图形为方形镶嵌结构，复合缓冲层中复合缓冲层中n区与p区有同样宽度b（以微米计）时，所述的每个n区和每个p区杂质分布不均匀，杂质浓度含一常数部分及一个线性部分，其常数部分为7.2×1016V-0.2 B/b〔厘米-3〕，其线性部分之梯度为3.0×1020V-0.2 B/b〔厘米-4〕，这时，复合缓冲层的厚度为0.019V1.2 B〔微米〕。
10、根据权利要求4所述的半导体功率器件，其特征在于：当耐压要求为VB〔伏〕，结构图形为三角形单元、六角形单元、圆形单元并并接而成时，所述每个n区和每个p区杂质分布不均匀，杂质浓度含一常数部分及一个线性部分，其常数部分为7.2×1016V-0.2/b〔厘米-3〕，其线性部分之梯度为3.0×1020V-0.2/b〔厘米-4〕，这时，复合缓冲层的厚度为0.019V1.2 B〔微米〕。
11、根据权利要求2所述的半导体功率器件，其特征在于：所述的耐压区的复合缓冲层的两面与n+区及p+区是直接相接的。
12、根据权利要求2所述的半导体功率器件，其特征在于：所述的耐压区的复合缓冲层中的相邻的p区与n区是直接相接的。
13、根据权利要求2所述的半导体功率器件，其特征在于：所述的耐压区的复合缓冲层中的相邻的p区与n区之间隔有介质层。
14、根据权利要求2所述的半导体功率器件，其特征在于：所述的耐压区的复合缓冲层中的n区与p区的截面积是不相等的。
15、半导体功率器件，它包括有一个p+区与n+区之间的耐压区，其特征在于：所述的耐压区中，在p+区相接的平面与n+区界面之间有由p区与n区交替组合而成的复合缓冲层，复合缓冲层中n区为导电区，p区与n+区之间隔有介质层。
16、半导体功率器件，它包括有一个p+区与n+区之间的耐压区，其特征在于：所述的耐压区中，在p+区相接的平面与n+区界面之间有由p区与n区交替组合而成的复合缓冲层，复合缓冲层中n区为导电区，p区与n+区之间隔有介质层。
17、根据权利要求15或16所述的半导体功率器件，其特征在于：所述的耐压区的复合缓冲层中，n区有效地施主总电荷与p区有效受主总电荷相对差别不超过50%。
CN91101845A 1991-03-19 1991-03-19 半导体功率器件 Expired CN1019720B (zh)

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