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Aging- and Variation-Aware Delay Monitoring Using Representative Critical Path Selection

Published: 24 June 2015 Publication History

Abstract

Process together with runtime variations in temperature and voltage, as well as transistor aging, degrade path delay and may eventually induce circuit failure due to timing variations. Therefore, in-field tracking of path delays is essential, and to respond to this need, several delay sensor designs have been proposed in the literature. However, due to the significant overhead of these sensors and the large number of critical paths in today's IC, it is infeasible to monitor the delay of every critical path in silicon. We present an aging- and variationaware representative path selection technique based on machine learning that allows to measure the delay of a small set of paths and infer the delay of a larger pool of paths that are likely to fail due to delay variations. Simulation results for benchmark circuits highlight the accuracy of the proposed approach for predicting critical-path delay based on the selected representative paths.

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    cover image ACM Transactions on Design Automation of Electronic Systems
    ACM Transactions on Design Automation of Electronic Systems  Volume 20, Issue 3
    June 2015
    345 pages
    ISSN:1084-4309
    EISSN:1557-7309
    DOI:10.1145/2796316
    • Editor:
    • Naehyuck Chang
    Issue’s Table of Contents
    Permission to make digital or hard copies of all or part of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commercial advantage and that copies bear this notice and the full citation on the first page. Copyrights for components of this work owned by others than ACM must be honored. Abstracting with credit is permitted. To copy otherwise, or republish, to post on servers or to redistribute to lists, requires prior specific permission and/or a fee. Request permissions from [email protected]

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    Publication History

    Published: 24 June 2015
    Accepted: 01 March 2015
    Revised: 01 February 2015
    Received: 01 July 2014
    Published in TODAES Volume 20, Issue 3

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    Author Tags

    1. Reliability
    2. monitoring
    3. performance
    4. transistor aging
    5. variations

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    • (2022)Implementation of Aging Mechanism Analysis and Prediction for XILINX 7-Series FPGAs with a 28-nm ProcessSensors10.3390/s2212443922:12(4439)Online publication date: 12-Jun-2022
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