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In-field aging measurement and calibration for power-performance optimization

Published: 05 June 2011 Publication History

Abstract

Aging of transistors has become a major reliability concern especially when the VLSI circuits are in the nanometer regime. In this paper, we propose a novel methodology to address circuit aging in the field. On-chip aging sensor is designed to monitor transitions on functional paths capturing functional mode workload. Path delay is then accurately measured and converted to a digital value. Diagnosis and calibration are performed in the field, thereby achieving power-performance optimization throughout the entire lifetime. Simulation results demonstrate the efficiency of the proposed structure.

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Cited By

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  • (2020)On-Chip Health Monitoring Based on DE-Cluster in 2.5D ICsBio-inspired Computing: Theories and Applications10.1007/978-981-15-3425-6_40(517-526)Online publication date: 2-Apr-2020
  • (2019)Potential Critical Path Selection Based on a Time-Varying Statistical Timing Analysis FrameworkIEEE Transactions on Very Large Scale Integration (VLSI) Systems10.1109/TVLSI.2019.2893020(1-12)Online publication date: 2019
  • (2017)Coarse-Grained Online Monitoring of BTI Aging by Reusing Power-Gating InfrastructureIEEE Transactions on Very Large Scale Integration (VLSI) Systems10.1109/TVLSI.2016.262621825:4(1397-1407)Online publication date: 1-Apr-2017
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    cover image ACM Conferences
    DAC '11: Proceedings of the 48th Design Automation Conference
    June 2011
    1055 pages
    ISBN:9781450306362
    DOI:10.1145/2024724
    Permission to make digital or hard copies of all or part of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commercial advantage and that copies bear this notice and the full citation on the first page. Copyrights for components of this work owned by others than ACM must be honored. Abstracting with credit is permitted. To copy otherwise, or republish, to post on servers or to redistribute to lists, requires prior specific permission and/or a fee. Request permissions from [email protected]

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    Publication History

    Published: 05 June 2011

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    Author Tags

    1. aging
    2. on-chip measurement
    3. path delay measurement
    4. performance calibration
    5. power-performance optimization

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    Overall Acceptance Rate 1,770 of 5,499 submissions, 32%

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    Cited By

    View all
    • (2020)On-Chip Health Monitoring Based on DE-Cluster in 2.5D ICsBio-inspired Computing: Theories and Applications10.1007/978-981-15-3425-6_40(517-526)Online publication date: 2-Apr-2020
    • (2019)Potential Critical Path Selection Based on a Time-Varying Statistical Timing Analysis FrameworkIEEE Transactions on Very Large Scale Integration (VLSI) Systems10.1109/TVLSI.2019.2893020(1-12)Online publication date: 2019
    • (2017)Coarse-Grained Online Monitoring of BTI Aging by Reusing Power-Gating InfrastructureIEEE Transactions on Very Large Scale Integration (VLSI) Systems10.1109/TVLSI.2016.262621825:4(1397-1407)Online publication date: 1-Apr-2017
    • (2017)An Access Mechanism for Embedded Sensors in Modern SoCsJournal of Electronic Testing: Theory and Applications10.1007/s10836-017-5669-633:4(397-413)Online publication date: 1-Aug-2017
    • (2015)Aging- and Variation-Aware Delay Monitoring Using Representative Critical Path SelectionACM Transactions on Design Automation of Electronic Systems10.1145/274623720:3(1-23)Online publication date: 24-Jun-2015
    • (2014)Life after failure2014 Reliability and Maintainability Symposium10.1109/RAMS.2014.6798522(1-7)Online publication date: Jan-2014
    • (2014)Chip Health Monitoring Using Machine LearningProceedings of the 2014 IEEE Computer Society Annual Symposium on VLSI10.1109/ISVLSI.2014.119(280-283)Online publication date: 9-Jul-2014
    • (2014)Distributed minimum energy point tracking for systems-on-chipIEEE International Conference on Electro/Information Technology10.1109/EIT.2014.6871770(246-251)Online publication date: Jun-2014
    • (2014)SAM: A comprehensive mechanism for accessing embedded sensors in modern SoCs2014 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems (DFT)10.1109/DFT.2014.6962097(240-245)Online publication date: Oct-2014
    • (2013)Representative critical-path selection for aging-induced delay monitoring2013 IEEE International Test Conference (ITC)10.1109/TEST.2013.6651924(1-10)Online publication date: Sep-2013
    • Show More Cited By

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