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Journal of Electronic Testing, Volume 33
Volume 33, Number 1, February 2017
- Vishwani D. Agrawal:
Editorial. 1-3 - Test Technology Newsletter. 5-6
- Breeta SenGupta, Dimitar Nikolov, Urban Ingelsson, Erik Larsson
:
Test Planning for Core-based Integrated Circuits under Power Constraints. 7-23 - Imran Wali, Bastien Deveautour, Arnaud Virazel
A Low-Cost Reliability vs. Cost Trade-Off Methodology to Selectively Harden Logic Circuits. 25-36 - Konstantin O. Petrosyants, Lev M. Sambursky
Radiation-Induced Fault Simulation of SOI/SOS CMOS LSI's Using Universal Rad-SPICE MOSFET Model. 37-51 - Serhiy Avramenko
A High-Level Approach to Analyze the Effects of Soft Errors on Lossless Compression Algorithms. 53-64 - Stefano Esposito, Massimo Violante:
On the Consolidation of Mixed Criticalities Applications on Multicore Architectures. 65-76 - Christian Bartsch, Carlos Villarraga
A HW/SW Cross-Layer Approach for Determining Application-Redundant Hardware Faults in Embedded Systems. 77-92 - Abdurrahman A. Nasr, Mohamed Z. Abdulmageed:
An Efficient Reverse Engineering Hardware Trojan Detector Using Histogram of Oriented Gradients. 93-105 - Tamzidul Hoque
Golden-Free Hardware Trojan Detection with High Sensitivity Under Process Noise. 107-124 - R. Jothin
High Speed Energy Efficient Static Segment Adder for Approximate Computing Applications. 125-132 - Junjie Gu, Haipeng Fu
Fast and Automated Electromigration Analysis for CMOS RF PA Design. 133-140
Volume 33, Number 2, April 2017
- Vishwani D. Agrawal:
Editorial. 141 - Test Technology Newsletter. 143-145
- Michal Tadeusiewicz
A Systematic Method for Arranging Diagnostic Tests in Linear Analog DC and AC Circuits. 147-156 - Ding Deng, Yang Guo, Zhentao Li:
A Parallel Test Application Method towards Power Reduction. 157-169 - Vijay Sheshadri, Vishwani D. Agrawal, Prathima Agrawal:
Power-Aware Optimization of SoC Test Schedules Using Voltage and Frequency Scaling. 171-187 - Hadi Jahanirad
Reliability Model for Multiple-Error Protected Static Memories. 189-207 - Babak Aghaei
Link Testing: a Survey of Current Trends in Network on Chip. 209-225 - Biswajit Bhowmik, Jatindra Kumar Deka, Santosh Biswas:
A Time-Optimized Scheme Towards Analysis of Channel-Shorts in on-Chip Networks. 227-254 - Jiongjiong Mo
Total Ionizing Dose Effect and Single Event Burnout of VDMOS with Different Inter Layer Dielectric and Passivation. 255-259 - Zhe Liu, Xiaopeng Yu, Teng-long Fan, Cheng Cao, Wen-quan Sui:
A Bridged Contactless Measurement Technique for LC Tank Based Voltage-Controlled Oscillator. 261-266 - L. E. Seixas Jr
VI-Based Measurement System Focusing on Space Applications. 267-274
Volume 33, Number 3, June 2017
- Vishwani D. Agrawal:
Editorial. 275 - Past TTTC Events. 277-279
- Manuel J. Barragán, William R. Eisenstadt
Guest Editorial: Analog, Mixed-Signal and RF Testing. 281-282 - Peter Sarson
An ATE Filter Characterization ToolKit Using a Discrete Chirped Excitation Signal as Stimulus. 283-294 - Peter Sarson
Using Distortion Shaping Technique to Equalize ADC THD Performance Between ATEs. 295-303 - Yuming Zhuang
ADC Spectral Testing with Signal Amplitude Drift and Simultaneous Non-coherent Sampling. 305-313 - Álvaro Gómez-Pau
Multi-Directional Space Tessellation to Improve the Decision Boundary in Indirect Mixed-Signal Testing. 315-328 - Mangal Hemant Dhend
Fault Diagnosis of Smart Grid Distribution System by Using Smart Sensors and Symlet Wavelet Function. 329-338 - Hui Luo
A New Test Point Selection Method for Analog Continuous Parameter Fault. 339-352 - Jasbir N. Patel
A Passive Authentication System Based on Optical Variable Nano/Micro-Structures. 353-364 - Anthony Deluthault, Vincent Kerzerho, Serge Bernard
New Calibration Technique of Contact-less Resonant Biosensor. 365-375
Volume 33, Number 4, August 2017
- Vishwani D. Agrawal:
Editorial. 377-378 - Test Technology Newsletter. 379-380
- Amin Bazzazi, Mohammad Taghi Manzuri Shalmani
Hardware Trojan Detection Based on Logical Testing. 381-395 - Miao Tony He
An Access Mechanism for Embedded Sensors in Modern SoCs. 397-413 - Chenglin Yang, Fang Chen, Shulin Tian:
Grouped Genetic Algorithm Based Optimal Tests Selection for System with Multiple Operation Modes. 415-429 - Alfonso Martínez-Cruz
An Automatic Functional Coverage for Digital Systems Through a Binary Particle Swarm Optimization Algorithm with a Reinitialization Mechanism. 431-447 - Rahebeh Niaraki Asli, Shiva Taghipour
A Near-Threshold Soft Error Resilient 7T SRAM Cell with Low Read Time for 20 nm FinFET Technology. 449-462 - Mauricio D. Gutierrez
Susceptible Workload Evaluation and Protection using Selective Fault Tolerance. 463-477 - Bharat Garg, G. K. Sharma:
ACM: An Energy-Efficient Accuracy Configurable Multiplier for Error-Resilient Applications. 479-489 - Yuling Shang, Liyuan Sun
Test of Mechanical Failure for Via Holes and Solder Joints of Complex Interconnect Structure. 491-499 - Babak Aghaei
A New BIST-based Test Approach with the Fault Location Capability for Communication Channels in Network-on-Chip. 501-513 - Amit Karel
Resistive Bridging Defect Detection in Bulk, FDSOI and FinFET Technologies. 515-527 - Ayan Palchaudhuri
Built-In Fault Localization Circuitry for High Performance FPGA Based Implementations. 529-537
Volume 33, Number 5, October 2017
- Vishwani D. Agrawal:
Editorial. 539-540 - Test Technology Newsletter. 541-542
- Yong Deng
Soft Fault Diagnosis in Analog Circuits Based on Bispectral Models. 543-557 - Liyue Yan
A Novel Noise-assisted Prognostic Method for Linear Analog Circuits. 559-572 - Bei Zhang, Vishwani D. Agrawal:
Three-Stage Optimization of Pre-Bond Diagnosis of TSV Defects. 573-589 - Hafiz Md. Hasan Babu, Md. Solaiman Mia
Efficient Techniques for Fault Detection and Correction of Reversible Circuits. 591-605 - Ghaith Bany Hamad
Formal Methods Based Synthesis of Single Event Transient Tolerant Combinational Circuits. 607-620 - Vineeta Shukla
Offline Error Detection in MEDA-Based Digital Microfluidic Biochips Using Oscillation-Based Testing Methodology. 621-635 - M. Tulio Martins, G. Cardoso Medeiros, Thiago Copetti, Fabian Vargas, Marcus Pohls:
Analysing NBTI Impact on SRAMs with Resistive Defects. 637-655 - Vijaypal Singh Rathor
New Light Weight Threshold Voltage Defined Camouflaged Gates for Trustworthy Designs. 657-668 - Il-Woo Jung, Bonggu Sung, Byoungdeog Choi
Novel Method for Nondestructive Body Effect Measurement in Dynamic Random Access Memory. 669-674 - S. Geetha
High Speed Error Tolerant Adder for Multimedia Applications. 675-688
Volume 33, Number 6, December 2017
- Vishwani D. Agrawal:
Editorial. 689-690 - 2016 JETTA-TTTC Best Paper Award - Masahiro Ishida, Toru Nakura, Takashi Kusaka, Satoshi Komatsu and Kunihiro Asada, "Dynamic Power Integrity Control of ATE for Eliminating Overkills and Underkills in Device Testing, " Journal of Electronic Testing: Theory and Applications, Volume 32, Number 3, pp. 247-271. June 2016. 691-692
- 2016-2017 JETTA Reviewers. 693-694
- Test Technology Newsletter. 695-696
- Zhijie Yuan, Yigang He, Lifen Yuan, Zhen Cheng:
A Diagnostics Method for Analog Circuits Based on Improved Kernel Entropy Component Analysis. 697-707 - Yan Duan, Tao Chen
A Low-cost Dithering Method for Improving ADC Linearity Test Applied in uSMILE Algorithm. 709-720 - Ankush Srivastava
A Reliability-Aware Methodology to Isolate Timing-Critical Paths under Aging. 721-739 - Gengxin Tian, Jun Li, Xiaofang Liu, Lixi Wan, Liqiang Cao:
Study on Magnetic Probe Calibration in Near-field Measurement System for EMI Application. 741-750 - Pascal Raiola
Evaluating the Effectiveness of D-chains in SAT-based ATPG and Diagnostic TPG. 751-767 - Tengyue Yi
A Study of PN Junction Diffusion Capacitance of MOSFET in Presence of Single Event Transient. 769-773 - Nantian Wang, Xiaoyu Ma, Xiaobin Xu, Ziqiao Rui:
A Low Power Online Test Method for FPGA Single Solder Joint Resistance. 775-780
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