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Jatindra Kumar Deka
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2020 – today
- 2023
- [j11]Kunwer Mrityunjay Singh
, Jatindra Kumar Deka, Santosh Biswas:
Incomplete Testing of SOC. J. Electron. Test. 39(3): 387-402 (2023) - 2021
- [j10]Sisir Kumar Jena
Retesting Defective Circuits to Allow Acceptable Faults for Yield Enhancement. J. Electron. Test. 37(5): 633-652 (2021) - [c31]Biswajit Bhowmik, Jatindra Kumar Deka, Santosh Biswas:
Selective Fault-Masking for Improving Yield and Performance of On-Chip Networks. SMC 2021: 3336-3341 - [c30]Nanu Alan Kachari
Conversion of Virtual Lab Experiments using FOSS: A Case Study of Virtual Labs by NMEICT. TALE 2021: 318-324 - [c29]Kunwer Mrityunjay Singh, Santosh Biswas, Jatindra Kumar Deka:
ATPG for Incomplete Testing of SOC Considering Bridging Faults. TENCON 2021: 323-328 - 2020
- [j9]Mousum Handique, Jatindra Kumar Deka, Santosh Biswas
An Efficient Test Set Construction Scheme for Multiple Missing-Gate Faults in Reversible Circuits. J. Electron. Test. 36(1): 105-122 (2020) - [c28]Biswajit Bhowmik, Jatindra Kumar Deka, Santosh Biswas:
Reliability Monitoring in a Smart NoC Component. ICECS 2020: 1-4 - [c27]Biswajit Bhowmik, Santosh Biswas, Jatindra Kumar Deka, Bhargab B. Bhattacharya:
Locating Open-Channels in Octagon Networks on Chip-Microprocessors. ISVLSI 2020: 200-205 - [c26]Biswajit Bhowmik, Jatindra Kumar Deka, Santosh Biswas:
Improving Reliability in Spidergon Network on Chip-Microprocessors. MWSCAS 2020: 474-477 - [c25]Biswajit Bhowmik, Santosh Biswas, Jatindra Kumar Deka:
Test Methodology for Analysis of Coexistent Logic-Level Faults in NoC Channels. SMC 2020: 2339-2344 - [c24]Mousum Handique, Jatindra Kumar Deka, Santosh Biswas:
A Fault Detection Scheme for Reversible Circuits using -Ve Control k-CNOT Based Circuit. TENCON 2020: 1-6 - [c23]Sisir Kumar Jena, Santosh Biswas, Jatindra Kumar Deka:
Maximizing Yield through Retesting of Rejected Circuits using Approximation Technique. TENCON 2020: 182-187 - [c22]Sisir Kumar Jena
Approximate Testing of Digital VLSI Circuits using Error Significance based Fault Analysis. VDAT 2020: 1-6
2010 – 2019
- 2019
- [j8]Biswajit Bhowmik
A Low-Cost Test Solution for Reliable Communication in Networks-on-Chip. J. Electron. Test. 35(2): 215-243 (2019) - [j7]Mousum Handique, Santosh Biswas
Test Generation for Bridging Faults in Reversible Circuits Using Path-Level Expressions. J. Electron. Test. 35(4): 441-457 (2019) - [j6]Biswajit Bhowmik
Performance-Aware Test Scheduling for Diagnosing Coexistent Channel Faults in Topology-Agnostic Networks-on-Chip. ACM Trans. Design Autom. Electr. Syst. 24(2): 17:1-17:29 (2019) - [c21]Sisir Kumar Jena
Systematic Design of Approximate Adder Using Significance Based Gate-Level Pruning (SGLP) for Image Processing Application. PReMI (2) 2019: 561-570 - 2018
- [j5]Biswajit Bhowmik, Jatindra Kumar Deka, Santosh Biswas:
On-Line Analysis of Stuck-at Faults in On-Chip Network Interconnects. J. Circuits Syst. Comput. 27(13): 1850203:1-1850203:13 (2018) - [j4]Biswajit Bhowmik
Reliability-Aware Test Methodology for Detecting Short-Channel Faults in On-Chip Networks. IEEE Trans. Very Large Scale Integr. Syst. 26(6): 1026-1039 (2018) - 2017
- [j3]Biswajit Bhowmik, Jatindra Kumar Deka, Santosh Biswas:
A Time-Optimized Scheme Towards Analysis of Channel-Shorts in on-Chip Networks. J. Electron. Test. 33(2): 227-254 (2017) - [c20]Biswajit Bhowmik, Jatindra Kumar Deka, Santosh Biswas:
Charka: A reliability-aware test scheme for diagnosis of channel shorts beyond mesh NoCs. DATE 2017: 214-219 - 2016
- [c19]Biswajit Bhowmik, Santosh Biswas, Jatindra Kumar Deka:
A Reliability-Aware Topology-Agnostic Test Scheme for Detecting, and Diagnosing Interconnect Shorts in On-chip Networks. HPCC/SmartCity/DSS 2016: 530-537 - [c18]Biswajit Bhowmik, Jatindra Kumar Deka, Santosh Biswas:
When Clustering Shows Optimality towards Analyzing Stuck-at Faults in Channels of On-chip Networks. HPCC/SmartCity/DSS 2016: 868-875 - [c17]Biswajit Bhowmik, Jatindra Kumar Deka, Santosh Biswas:
An on-line test solution for addressing interconnect shorts in on-chip networks. IOLTS 2016: 9-12 - [c16]Biswajit Bhowmik, Santosh Biswas, Jatindra Kumar Deka:
An odd-even scheme to prevent a packet from being corrupted and dropped in fault tolerant NoCs. IOLTS 2016: 195-198 - [c15]Biswajit Bhowmik, Jatindra Kumar Deka, Santosh Biswas:
Towards a Scalable Test Solution for the Analysis of Interconnect Shorts in On-chip Networks. MASCOTS 2016: 394-399 - [c14]Biswajit Bhowmik, Jatindra Kumar Deka, Santosh Biswas, Bhargab B. Bhattacharya:
A topology-agnostic test model for link shorts in on-chip networks. SMC 2016: 4561-4566 - [c13]Biswajit Bhowmik, Jatindra Kumar Deka, Santosh Biswas, Bhargab B. Bhattacharya:
On-line detection and diagnosis of stuck-at faults in channels of NoC-based systems. SMC 2016: 4567-4572 - [c12]Biswajit Bhowmik, Santosh Biswas, Jatindra Kumar Deka, Bhargab B. Bhattacharya:
Detecting and diagnosing open faults in NoC channels on activation of diagonal nodes. SMC 2016: 4573-4578 - [c11]Biswajit Bhowmik, Santosh Biswas, Jatindra Kumar Deka, Bhargab B. Bhattacharya:
One poison is antidote against another poison. SMC 2016: 4579-4584 - 2015
- [c10]Biswajit Bhowmik, Jatindra Kumar Deka, Santosh Biswas:
Reliability on Top of Best Effort Delivery: Maximal Connectivity Test on NoC Interconnects. COMPUTE 2015: 19-28 - [c9]Biswajit Bhowmik, Santosh Biswas, Jatindra Kumar Deka:
A packet address driven test strategy for stuck-at faults in networks-on-chip interconnects. MED 2015: 176-183 - [c8]Biswajit Bhowmik, Jatindra Kumar Deka, Santosh Biswas:
Directed Symbolic Execution for VLSI Circuits. SMC 2015: 50-55 - [c7]Biswajit Bhowmik, Santosh Biswas, Jatindra Kumar Deka:
An Optimal Diagnosis of NoC Interconnects on Activation of Diagonal Routers. SMC 2015: 755-760 - 2014
- [c6]Biswajit Bhowmik, Santosh Biswas, Jatindra Kumar Deka:
Detection of faulty interswitch links in 2-D mesh network-on-chips. IEEE ANTS 2014: 1-6 - 2010
- [c5]Khan Ajoy, Kushagra Misra, Santosh Biswas, Jatindra Kumar Deka, Hemangee K. Kapoor:
Fair diagnosability in PN-based DES models. ICCA 2010: 2166-2171
2000 – 2009
- 2005
- [c4]Moi Riba, Jatindra Kumar Deka:
Variable Ordering of BDDs using Genetic Algorithm. IICAI 2005: 198-208 - 2003
- [c3]Jatindra Kumar Deka:
Reasoning about Extremal Properties of Events. TIME 2003: 26-36 - 2001
- [j2]Pallab Dasgupta, P. P. Chakrabarti, Jatindra Kumar Deka, Sriram Sankaranarayanan:
Min-max Computation Tree Logic. Artif. Intell. 127(1): 137-162 (2001) - [c2]Jatindra Kumar Deka, S. Chaki, Pallab Dasgupta, P. P. Chakrabarti:
Abstractions for model checking of event timings. ISCAS (5) 2001: 125-128 - 2000
- [j1]Pallab Dasgupta, Jatindra Kumar Deka, Partha Pratim Chakrabarti:
Model checking on timed-event structures. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 19(5): 601-611 (2000)
1990 – 1999
- 1999
- [c1]Jatindra Kumar Deka, Pallab Dasgupta, P. P. Chakrabarti:
An Efficiently Checkable Subset of TCTL for Formal Verification of Transition Systems with Delays. VLSI Design 1999: 294-299
Coauthor Index
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