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A Time-Optimized Scheme Towards Analysis of Channel-Shorts in on-Chip Networks

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Abstract

With the continuous growth in technology, the role of nano-electronic systems is rapidly expanding in every facet of modern life. Subsequently, the demand of high performance computations and communications by many applications in order to interact with environment and users has become a compulsion. Traditional integrated circuit-based systems, e.g., bus-based systems-on-chip (SoCs), as a consequence are turned into networks- on-chips (NoCs) because of the communication bottleneck by the SoCs. Though, the NoCs visibly move the concern and meet the requirements by the applications but fabricating such NoCs without any defect in channels or logics has eventually evolved into a major challenge. Indeed, one of the major demand nowadays for such systems is to design a time-efficient mechanism for the pre- and post-manufacturing testing of NoC functional components, in order to guarantee outgoing quality while not sacrificing yield and reliability. This paper presents a cost effective and distributed on-line test mechanism that addresses channel-shorts in NoC-based systems. The proposed mechanism detects and diagnoses both intra- and inter-channel short faults. The test mechanism additionally targets transient and stuck-at faults in channels. A convenient test scheduling and energy model are presented. The scheduling scheme offers constant test time with little hardware area and performance overheads on the NoCs irrespective of their topologies and sizes. The proposed test solution is evaluated with fault injection campaign in channels of a set of NoC architectures. Fault simulation detects all modeled faults in channels resulting 100% test and fault coverage metrics. On-line evaluation of the proposed solution reveals insights of the effect of channel-shorts on various performance metrics at large amount of traffic. Furthermore, the proposed solution improves various quality metrics on the set of NoCs, for instance, the test area overhead is reduced up to 28% while the proposed model becomes 16 × faster. Also, improvement on the performance overhead is noticed. The packet latency for instance, is improved by 14.98–50.67% while packet flit energy consumption is reduced by 6.83–43.89%. Such improvements are found to grow with NoC size.

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Notes

  1. Detection of stuck-at and transient faults in a test iteration are attempted followed by the short fault detection.

  2. Other test vectors such as, A1, Ao, etc. are used for stuck-at and transient faults.

  3. A hop is single channel-length.

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Authors and Affiliations

  1. Department of Computer Science and Engineering, Indian Institute of Technology Guwahati, Assam –, 781039, India

    Biswajit Bhowmik, Jatindra Kumar Deka & Santosh Biswas

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  1. Biswajit Bhowmik
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  2. Jatindra Kumar Deka
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  3. Santosh Biswas
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Correspondence to Biswajit Bhowmik.

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Responsible Editor: K. Chakrabarty

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Bhowmik, B., Deka, J.K. & Biswas, S. A Time-Optimized Scheme Towards Analysis of Channel-Shorts in on-Chip Networks. J Electron Test 33, 227–254 (2017). https://doi.org/10.1007/s10836-017-5655-z

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