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IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, Volume 32
Volume 32, Number 1, January 2013
- Sachin S. Sapatnekar
:
Editorial. 1 - Puneet Gupta
Underdesigned and Opportunistic Computing in Presence of Hardware Variability. 8-23 - Fang Gong, Sina Basir-Kazeruni, Lei He, Hao Yu
Stochastic Behavioral Modeling and Analysis for Analog/Mixed-Signal Circuits. 24-33 - Junwhan Ahn, Kiyoung Choi:
Isomorphism-Aware Identification of Custom Instructions With I/O Serialization. 34-46 - Ajay N. Bhoj, Rajiv V. Joshi, Niraj K. Jha:
Efficient Methodologies for 3-D TCAD Modeling of Emerging Devices and Circuits. 47-58 - Yan Luo, Krishnendu Chakrabarty
Error Recovery in Cyberphysical Digital Microfluidic Biochips. 59-72 - Aadithya V. Karthik, Alper Demir
Accurate Prediction of Random Telegraph Noise Effects in SRAMs and DRAMs. 73-86 - Ing-Chao Lin, Chin-Hung Lin, Kuan-Hui Li:
Leakage and Aging Optimization Using Transmission Gate-Based Technique. 87-99 - Farshad Firouzi, Saman Kiamehr, Mehdi Baradaran Tahoori:
Power-Aware Minimum NBTI Vector Selection Using a Linear Programming Approach. 100-110 - Jongyoon Jung, Taewhan Kim:
Statistical Viability Analysis for Detecting False Paths Under Delay Variation. 111-123 - Vaibhav Gupta, Debabrata Mohapatra, Anand Raghunathan
Low-Power Digital Signal Processing Using Approximate Adders. 124-137 - Tak-Yung Kim, Taewhan Kim:
Resource Allocation and Design Techniques of Prebond Testable 3-D Clock Tree. 138-151 - Wei-Cheng Lien
Counter-Based Output Selection for Test Response Compaction. 152-164 - Shyue-Kung Lu, Huan-Hua Huang, Jiun-Lang Huang, Pony Ning:
Synergistic Reliability and Yield Enhancement Techniques for Embedded SRAMs. 165-169
Volume 32, Number 2, February 2013
- Jiang Hu, Cheng-Kok Koh:
Guest editorial: Special section on cross-domain physical optimization. 173-174 - Jackey Z. Yan, Chris Chu:
SDS: An Optimal Slack-Driven Block Shaping Algorithm for Fixed-Outline Floorplanning. 175-188 - Shao-Yun Fang, Wei-Yu Chen, Yao-Wen Chang
Graph-Based Subfield Scheduling for Electron-Beam Photomask Fabrication. 189-201 - Rani S. Ghaida, Kanak B. Agarwal, Sani R. Nassif, Xin Yuan, Lars Liebmann, Puneet Gupta
Layout Decomposition and Legalization for Double-Patterning Technology. 202-215 - Jia-Wen Chang, Sheng-Han Yeh, Tsung-Wei Huang, Tsung-Yi Ho
Integrated Fluidic-Chip Co-Design Methodology for Digital Microfluidic Biochips. 216-227 - Samuel I. Ward, Myung-Chul Kim, Natarajan Viswanathan, Zhuo Li, Charles J. Alpert, Earl E. Swartzlander Jr., David Z. Pan:
Structure-Aware Placement Techniques for Designs With Datapaths. 228-241 - Chih-Long Chang, Iris Hui-Ru Jiang:
Pulsed-Latch Replacement Using Concurrent Time Borrowing and Clock Gating. 242-246 - Junghee Lee
Preemptible I/O Scheduling of Garbage Collection for Solid State Drives. 247-260 - Xiaoming Chen, Yu Wang
NICSLU: An Adaptive Sparse Matrix Solver for Parallel Circuit Simulation. 261-274 - Guoyong Shi:
Graph-Pair Decision Diagram Construction for Topological Symbolic Circuit Analysis. 275-288 - Ozgur Sinanoglu
Scan to Nonscan Conversion via Test Cube Analysis. 289-300 - Daniel Arumí
Diagnosis of Interconnect Full Open Defects in the Presence of Gate Leakage Currents. 301-312 - Fabio L. Traversa
Selective Determination of Floquet Quantities for the Efficient Assessment of Limit Cycle Stability and Oscillator Noise. 313-317 - Mengmeng Li
A Multilevel FFT Method for the 3-D Capacitance Extraction. 318-322
Volume 32, Number 3, March 2013
- Jie Wu, Jia Wang, Kun Li, Hai Zhou, Qin Lv, Li Shang, Yihe Sun:
Large-Scale Energy Storage System Design and Optimization for Emerging Electric-Drive Vehicles. 325-338 - Antoine Morvan, Steven Derrien, Patrice Quinton:
Polyhedral Bubble Insertion: A Method to Improve Nested Loop Pipelining for High-Level Synthesis. 339-352 - Wenjian Yu, Hao Zhuang, Chao Zhang, Gang Hu, Zhi Liu:
RWCap: A Floating Random Walk Solver for 3-D Capacitance Extraction of Very-Large-Scale Integration Interconnects. 353-366 - Bing Li, Ning Chen, Yang Xu, Ulf Schlichtmann
On Timing Model Extraction and Hierarchical Statistical Timing Analysis. 367-380 - Ching-Yu Chin, Chung-Yi Kuan, Tsung-Ying Tsai, Hung-Ming Chen, Yoji Kajitani:
Escaped Boundary Pins Routing for High-Speed Boards. 381-391 - Kyoung-Hwan Lim, Deokjin Joo, Taewhan Kim:
An Optimal Allocation Algorithm of Adjustable Delay Buffers and Practical Extensions for Clock Skew Optimization in Multiple Power Mode Designs. 392-405 - Wei Liu, Andrea Calimera
Layout-Driven Post-Placement Techniques for Temperature Reduction and Thermal Gradient Minimization. 406-418 - Po-Hsun Wu, Mark Po-Hung Lin
1-D Cell Generation With Printability Enhancement. 419-432 - Iftekhar Ibne Basith, Nabeeh Kandalaft, Rashid Rashidzadeh, Majid Ahmadi:
Charge-Controlled Readout and BIST Circuit for MEMS Sensors. 433-441 - Irith Pomeranz:
Generation of Functional Broadside Tests for Logic Blocks With Constrained Primary Input Sequences. 442-452 - Kuntal Nanshi, Fabio Somenzi:
Using Abstraction to Guide the Search for Long Error Traces. 453-466 - Shao-Lun Huang, Wei-Hsun Lin, Po-Kai Huang, Chung-Yang Huang:
Match and Replace: A Functional ECO Engine for Multierror Circuit Rectification. 467-478 - Pedro Reviriego, Salvatore Pontarelli
A Method to Construct Low Delay Single Error Correction Codes for Protecting Data Bits Only. 479-483
Volume 32, Number 4, April 2013
- Yuan Xie, Gabriel H. Loh:
Guest Editorial. 485-486 - Wei Yao, Siming Pan, Brice Achkir, Jun Fan
Modeling and Application of Multi-Port TSV Networks in 3-D IC. 487-496 - Meng-Kai Hsu, Valeriy Balabanov, Yao-Wen Chang
TSV-Aware Analytical Placement for 3-D IC Designs Based on a Novel Weighted-Average Wirelength Model. 497-509 - Guojie Luo, Yiyu Shi, Jason Cong:
An Analytical Placement Framework for 3-D ICs and Its Extension on Thermal Awareness. 510-523 - Mohamed M. Sabry, Arvind Sridhar, Jie Meng, Ayse K. Coskun, David Atienza:
GreenCool: An Energy-Efficient Liquid Cooling Design Technique for 3-D MPSoCs Via Channel Width Modulation. 524-537 - Nabeeh Kandalaft, Rashid Rashidzadeh, Majid Ahmadi:
Testing 3-D IC Through-Silicon-Vias (TSVs) by Direct Probing. 538-546 - Brandon Noia, Krishnendu Chakrabarty
Pre-Bond Probing of Through-Silicon Vias in 3-D Stacked ICs. 547-558 - Li Jiang, Qiang Xu
On Effective Through-Silicon Via Repair for 3-D-Stacked ICs. 559-571 - Che-Wei Chou, Yu-Jen Huang, Jin-Fu Li:
A Built-In Self-Repair Scheme for 3-D RAMs With Interdie Redundancy. 572-583 - Yaoyao Ye, Jiang Xu
3-D Mesh-Based Optical Network-on-Chip for Multiprocessor System-on-Chip. 584-596 - Christian Weis, Igor Loi, Luca Benini
Exploration and Optimization of 3-D Integrated DRAM Subsystems. 597-610 - Jonathan Valamehr, Timothy Sherwood
A 3-D Split Manufacturing Approach to Trustworthy System Development. 611-615 - Cristian Ferent, Alex Doboli:
Symbolic Matching and Constraint Generation for Systematic Comparison of Analog Circuits. 616-629 - Cheng Zhuo, Dennis Sylvester, David T. Blaauw:
A Statistical Framework for Post-Fabrication Oxide Breakdown Reliability Prediction and Management. 630-643
Volume 32, Number 5, May 2013
- Daesung Lee, W. Scott Lee, Chen Chen, Farzan Fallah, J. Provine, Soogine Chong, John Watkins, Roger T. Howe
Combinational Logic Design Using Six-Terminal NEM Relays. 653-666 - Bill Teng, Jason Helge Anderson:
Latch-Based Performance Optimization for Field-Programmable Gate Arrays. 667-680 - Mirjana Stojilovic
Selective Flexibility: Creating Domain-Specific Reconfigurable Arrays. 681-694 - Sangyoung Park
Accurate Modeling of the Delay and Energy Overhead of Dynamic Voltage and Frequency Scaling in Modern Microprocessors. 695-708 - Wen-Hao Liu, Wei-Chun Kao, Yih-Lang Li, Kai-Yuan Chao:
NCTU-GR 2.0: Multithreaded Collision-Aware Global Routing With Bounded-Length Maze Routing. 709-722 - Fangming Ye, Zhaobo Zhang, Krishnendu Chakrabarty
Board-Level Functional Fault Diagnosis Using Artificial Neural Networks, Support-Vector Machines, and Weighted-Majority Voting. 723-736 - Yu-Hsiang Lin, Shi-Yu Huang, Kun-Han Tsai, Wu-Tung Cheng, Stephen K. Sunter, Yung-Fa Chou, Ding-Ming Kwai:
Parametric Delay Test of Post-Bond Through-Silicon Vias in 3-D ICs via Variable Output Thresholding Analysis. 737-747 - Xiao Liu, Qiang Xu
On Multiplexed Signal Tracing for Post-Silicon Validation. 748-759 - Abdul Naeem, Axel Jantsch
Scalability Analysis of Memory Consistency Models in NoC-Based Distributed Shared Memory SoCs. 760-773 - Alessandro Cimatti
Software Model Checking SystemC. 774-787 - Jayanand Asok Kumar, Shobha Vasudevan:
Formal Probabilistic Timing Verification in RTL. 788-801 - Quan Chen, Wim Schoenmaker, Guan-Hua Chen, Lijun Jiang, Ngai Wong:
A Numerically Efficient Formulation for Time-Domain Electromagnetic-Semiconductor Cosimulation for Fast-Transient Systems. 802-806
Volume 32, Number 6, June 2013
- Yibo Guo, Qingfeng Zhuge, Jingtong Hu
Data Placement and Duplication for Embedded Multicore Systems With Scratch Pad Memory. 809-817 - Matthew Amy, Dmitri Maslov
A Meet-in-the-Middle Algorithm for Fast Synthesis of Depth-Optimal Quantum Circuits. 818-830 - Omid Sarbishei, Katarzyna Radecka:
On the Fixed-Point Accuracy Analysis and Optimization of Polynomial Specifications. 831-844 - Dusung Kim, Maciej J. Ciesielski, Seiyang Yang:
MULTES: Multilevel Temporal-Parallel Event-Driven Simulation. 845-857 - Haotian Liu, Ngai Wong:
Autonomous Volterra Algorithm for Steady-State Analysis of Nonlinear Circuits. 858-868 - Hamed Abrishami, Safar Hatami, Massoud Pedram:
Design and Multicorner Optimization of the Energy-Delay Product of CMOS Flip-Flops Under the Negative Bias Temperature Instability Effect. 869-881 - Tao Huang, Evangeline F. Y. Young:
ObSteiner: An Exact Algorithm for the Construction of Rectilinear Steiner Minimum Trees in the Presence of Complex Rectilinear Obstacles. 882-893 - Andrzej Kozik
Fully Dynamic Evaluation of Sequence Pair. 894-904 - Krit Athikulwongse, Jae-Seok Yang, David Z. Pan, Sung Kyu Lim
Impact of Mechanical Stress on the Full Chip Timing for Through-Silicon-Via-based 3-D ICs. 905-917 - Ashutosh Chakraborty, David Z. Pan:
Skew Management of NBTI Impacted Gated Clock Trees. 918-927 - Yu-Fu Yeh, Hsin-Cheng Lin, Chung-Yang Huang:
An Ultrasynchronization Checking Method With Trace-Driven Simulation for Fast and Accurate MPSoC Virtual Platform Simulation. 928-939 - Wooyoung Jang, David Z. Pan:
Chemical-Mechanical Polishing-Aware Application-Specific 3D NoC Design. 940-951 - Samuel Hertz, David Sheridan, Shobha Vasudevan:
Mining Hardware Assertions With Guidance From Static Analysis. 952-965 - Andrei B. Khlopotine, Vikram Jandhyala, Desmond Kirkpatrick:
A Variant of Parallel Plane Sweep Algorithm for Multicore Systems. 966-970 - Chia-Yuan Chang, Kuan-Yu Liao, Sheng-Chang Hsu, James Chien-Mo Li, Jiann-Chyi Rau:
Compact Test Pattern Selection for Small Delay Defect. 971-975
Volume 32, Number 7, July 2013
- Leyi Yin, Yue Deng, Peng Li:
Simulation-Assisted Formal Verification of Nonlinear Mixed-Signal Circuits With Bayesian Inference Guidance. 977-990 - Mark Po-Hung Lin
Common-Centroid Capacitor Layout Generation Considering Device Matching and Parasitic Minimization. 991-1002 - Qing Xie, Yanzhi Wang, Younghyun Kim
Charge Allocation in Hybrid Electrical Energy Storage Systems. 1003-1016 - Donghwa Shin, Younghyun Kim
Dynamic Driver Supply Voltage Scaling for Organic Light Emitting Diode Displays. 1017-1030 - Vidyabhushan Mohan, Trevor Bunker, Laura M. Grupp, Sudhanva Gurumurthi, Mircea R. Stan
Modeling Power Consumption of NAND Flash Memories Using FlashPower. 1031-1044 - Chuan Xu, Seshadri K. Kolluri, Kazuhiko Endo
Analytical Thermal Model for Self-Heating in Advanced FinFET Devices With Implications for Design and Reliability. 1045-1058 - Xuanxing Xiong, Jia Wang:
Verifying RLC Power Grids With Transient Current Constraints. 1059-1071 - Wangyang Zhang, Karthik Balakrishnan, Xin Li, Duane S. Boning, Sharad Saxena, Andrzej J. Strojwas, Rob A. Rutenbar
Efficient Spatial Pattern Analysis for Variation Decomposition Via Robust Sparse Regression. 1072-1085 - Mohammad Rahman, Hiran Tennakoon, Carl Sechen:
Library-Based Cell-Size Selection Using Extended Logical Effort. 1086-1099 - Chiao-Ling Lung, Yu-Shih Su, Hsih-Hsiu Huang, Yiyu Shi, Shih-Chieh Chang:
Through-Silicon Via Fault-Tolerant Clock Networks for 3-D ICs. 1100-1109 - Shervin Sharifi, Dilip Krishnaswamy, Tajana Simunic Rosing:
PROMETHEUS: A Proactive Method for Thermal Management of Heterogeneous MPSoCs. 1110-1123 - Abishek Ramdas, Ozgur Sinanoglu
Testing Chips With Spare Identical Cores. 1124-1135
Volume 32, Number 8, August 2013
- Jen-Wei Hsieh, Yu-Cheng Zheng, Yong-Sheng Peng, Po-Hung Yeh:
VAST: Virtually Associative Sector Translation for MLC Storage Systems. 1137-1150 - Ying-Han Chen, Chung-Lun Hsu, Li-Chen Tsai, Tsung-Wei Huang, Tsung-Yi Ho
A Reliability-Oriented Placement Algorithm for Reconfigurable Digital Microfluidic Biochips Using 3-D Deferred Decision Making Technique. 1151-1162 - Mihir R. Choudhury, Kartik Mohanram:
Low Cost Concurrent Error Masking Using Approximate Logic Circuits. 1163-1176 - Dan Burke, Tom J. Smy:
Thermal Models for Optical Circuit Simulation Using a Finite Cloud Method and Model Reduction Techniques. 1177-1186 - Ehsan K. Ardestani, Francisco J. Mesa-Martinez, Gabriel Southern, Elnaz Ebrahimi, Jose Renau:
Sampling in Thermal Simulation of Processors: Measurement, Characterization, and Evaluation. 1187-1200 - Chris Yakopcic, Tarek M. Taha, Guru Subramanyam, Robinson E. Pino:
Generalized Memristive Device SPICE Model and its Application in Circuit Design. 1201-1214 - Ulrich Brenner:
BonnPlace Legalization: Minimizing Movement by Iterative Augmentation. 1215-1227 - Zigang Xiao, Yuelin Du, Hongbo Zhang, Martin D. F. Wong
A Polynomial Time Exact Algorithm for Overlay-Resistant Self-Aligned Double Patterning (SADP) Layout Decomposition. 1228-1239 - Peter van Stralen, Andy D. Pimentel
Fitness Prediction Techniques for Scenario-Based Design Space Exploration. 1240-1253 - Wei-Cheng Lien
An Efficient On-Chip Test Generation Scheme Based on Programmable and Multiple Twisted-Ring Counters. 1254-1264 - Shi-Yu Huang, Yu-Hsiang Lin, Li-Ren Huang, Kun-Han Tsai, Wu-Tung Cheng:
Programmable Leakage Test and Binning for TSVs With Self-Timed Timing Control. 1265-1273 - Srobona Mitra, Ansuman Banerjee, Pallab Dasgupta, Priyankar Ghosh, Harish Kumar:
Formal Guarantees for Localized Bug Fixes. 1274-1287 - Andrew B. Kahng, Seokhyeong Kang, Tajana Simunic Rosing, Richard D. Strong:
Many-Core Token-Based Adaptive Power Gating. 1288-1292
Volume 32, Number 9, September 2013
- Andrea Acquaviva, Nicola Bombieri
Semi-Automatic Generation of Device Drivers for Rapid Embedded Platform Development. 1293-1306 - Yan Luo, Krishnendu Chakrabarty
Design of Pin-Constrained General-Purpose Digital Microfluidic Biochips. 1307-1320 - Suming Lai, Boyuan Yan, Peng Li:
Localized Stability Checking and Design of IC Power Delivery With Distributed Voltage Regulators. 1321-1334 - Yibo Chen, Eren Kursun, Dave Motschman, Charles Johnson, Yuan Xie:
Through Silicon Via Aware Design Planning for Thermally Efficient 3-D Integrated Circuits. 1335-1346 - Yuan-Kai Ho, Hsu-Chieh Lee, Yao-Wen Chang
Escape Routing for Staggered-Pin-Array PCBs. 1347-1356 - Xiang Qiu, Malgorzata Marek-Sadowska:
Routing Challenges for Designs With Super High Pin Density. 1357-1368 - Vasileios Tenentes
High-Quality Statistical Test Compression With Narrow ATE Interface. 1369-1382 - John Liaperdos
Adjustable RF Mixers' Alternate Test Efficiency Optimization by the Reduction of Test Observables. 1383-1394 - Naghmeh Karimi, Krishnendu Chakrabarty
Detection, Diagnosis, and Recovery From Clock-Domain Crossing Failures in Multiclock SoCs. 1395-1408 - Jinpeng Lv, Priyank Kalla, Florian Enescu:
Efficient Gröbner Basis Reductions for Formal Verification of Galois Field Arithmetic Circuits. 1409-1420 - Yi-Ting Chung, Jie-Hong Roland Jiang:
Functional Timing Analysis Made Fast and General. 1421-1434 - Zuochang Ye:
Noise Companion State-Space Passive Macromodeling for RF/mm-Wave Circuit Design. 1435-1439 - Li-Ren Huang, Shi-Yu Huang, Stephen K. Sunter, Kun-Han Tsai, Wu-Tung Cheng:
Oscillation-Based Prebond TSV Test. 1440-1444 - Irith Pomeranz:
Functional Broadside Tests With Incompletely Specified Scan-In States. 1445-1449
Volume 32, Number 10, October 2013
- David Z. Pan, Bei Yu, Jhih-Rong Gao:
Design for Manufacturing With Emerging Nanolithography. 1453-1472 - Yung-Chih Chen, Chun-Yao Wang, Ching-Yi Huang:
Verification of Reconfigurable Binary Decision Diagram-Based Single-Electron Transistor Arrays. 1473-1483 - Juinn-Dar Huang
Reactant and Waste Minimization in Multitarget Sample Preparation on Digital Microfluidic Biochips. 1484-1494 - Morteza Damavandpeyma, Sander Stuijk
Schedule-Extended Synchronous Dataflow Graphs. 1495-1508 - Seungwook Paek, Wongyu Shin, Jaehyeong Sim
PowerField: A Probabilistic Approach for Temperature-to-Power Conversion Based on Markov Random Field Theory. 1509-1519 - Youngae Han, Jinsong Zhao:
Accurate Substrate Analysis Based on a Novel Finite Difference Method via Synchronization Method on Layered and Adaptive Meshing. 1520-1532 - Zheng Zhang
Stochastic Testing Method for Transistor-Level Uncertainty Quantification Based on Generalized Polynomial Chaos. 1533-1545 - Xu He, Tao Huang, Linfu Xiao, Haitong Tian, Evangeline F. Y. Young:
Ripple: A Robust and Effective Routability-Driven Placer. 1546-1556 - Fong-Yuan Chang, Ren-Song Tsay, Wai-Kei Mak, Sheng-Hsiung Chen:
MANA: A Shortest Path Maze Algorithm Under Separation and Minimum Length NAnometer Rules. 1557-1568 - Nikita Nikitin, Javier de San Pedro
Architectural Exploration of Large-Scale Hierarchical Chip Multiprocessors. 1569-1582 - Fang Bao, Ke Peng, Mohammad Tehranipoor, Krishnendu Chakrabarty
Generation of Effective 1-Detect TDF Patterns for Detecting Small-Delay Defects. 1583-1594 - Xiaofei Guo, Ramesh Karri
Recomputing with Permuted Operands: A Concurrent Error Detection Approach. 1595-1608 - Brian Keng, Andreas G. Veneris:
Path-Directed Abstraction and Refinement for SAT-Based Design Debugging. 1609-1622 - Rupesh S. Shelar, Marek Patyra:
Impact of Local Interconnects on Timing and Power in a High Performance Microprocessor. 1623-1627 - Jieyi Long, Dawei Li, Seda Ogrenci Memik, Semail Ülgen
Theory and Analysis for Optimization of On-Chip Thermoelectric Cooling Systems. 1628-1632 - Chao Zhang, Wenjian Yu:
Efficient Space Management Techniques for Large-Scale Interconnect Capacitance Extraction With Floating Random Walks. 1633-1637
Volume 32, Number 11, November 2013
- Ricardo Martins
LAYGEN II - Automatic Layout Generation of Analog Integrated Circuits. 1641-1654 - Jia-Wen Chang, Sheng-Han Yeh, Tsung-Wei Huang, Tsung-Yi Ho
An ILP-Based Routing Algorithm for Pin-Constrained EWOD Chips With Obstacle Avoidance. 1655-1667 - Gayatri Mehta, Krunalkumar Patel, Natalie Parde
Data-Driven Mapping Using Local Patterns. 1668-1681 - Hans Georg Brachtendorf, Kai Bittner:
Grid Size Adapted Multistep Methods for High $Q$ Oscillators. 1682-1693 - Moongon Jung, David Z. Pan, Sung Kyu Lim
Chip/Package Mechanical Stress Impact on 3-D IC Reliability and Mobility Variations. 1694-1707 - Jordi Cortadella
Area-Optimal Transistor Folding for 1-D Gridded Cell Design. 1708-1721 - Hua-Yu Chang, Iris Hui-Ru Jiang, Yao-Wen Chang
ECO Optimization Using Metal-Configurable Gate-Array Spare Cells. 1722-1733 - Sai Manoj Pudukotai Dinakarrao
Reliable 3-D Clock-Tree Synthesis Considering Nonlinear Capacitive TSV Model With Electrical-Thermal-Mechanical Coupling. 1734-1747 - Jinho Lee
Mapping and Scheduling of Tasks and Communications on Many-Core SoC Under Local Memory Constraint. 1748-1761 - Panagiotis Sismanoglou, Dimitris Nikolos:
Input Test Data Compression Based on the Reuse of Parts of Dictionary Entries: Static and Dynamic Approaches. 1762-1775 - Jakub Janicki, Mark Kassab, Grzegorz Mrugalski, Nilanjan Mukherjee, Janusz Rajski, Jerzy Tyszer:
Test Time Reduction in EDT Bandwidth Management for SoC Designs. 1776-1786 - Chandan Karfa
Verification of Loop and Arithmetic Transformations of Array-Intensive Behaviors. 1787-1800 - Aritra Hazra, Rajdeep Mukherjee, Pallab Dasgupta, Ajit Pal, Kevin Harer, Ansuman Banerjee, Subhankar Mukherjee:
POWER-TRUCTOR: An Integrated Tool Flow for Formal Verification and Coverage of Architectural Power Intent. 1801-1813 - Libo Huang, Zhiying Wang, Nong Xiao, Yongwen Wang, Qiang Dou:
Dynamic Streamization Model Execution for SIMD Engines on Multicore Architectures. 1814-1818 - Aayush Prakash, Hiren D. Patel:
An Instruction Scratchpad Memory Allocation for the Precision Timed Architecture. 1819-1823 - Subhadip Kundu, Sankhadeep Pal, Santanu Chattopadhyay, Indranil Sengupta, Rohit Kapur:
A Metric for Test Set Characterization and Customization Toward Fault Diagnosis. 1824-1828 - Predrag Teodorovic
Recursive Boolean Formula Minimization Algorithms for Implication Logic. 1829-1833
Volume 32, Number 12, December 2013
- Sachin S. Sapatnekar
Editorial. 1837-1838 - Yan Luo, Krishnendu Chakrabarty
Real-Time Error Recovery in Cyberphysical Digital-Microfluidic Biochips Using a Compact Dictionary. 1839-1852 - Shervin Vakili
Enhanced Precision Analysis for Accuracy-Aware Bit-Width Optimization Using Affine Arithmetic. 1853-1865 - Seong-I Lei, Wai-Kei Mak:
Simultaneous Constrained Pin Assignment and Escape Routing Considering Differential Pairs for FPGA-PCB Co-Design. 1866-1878 - Domenic Forte
Improving the Quality of Delay-Based PUFs via Optical Proximity Correction. 1879-1891 - Young-Joon Lee, Sung Kyu Lim
Ultrahigh Density Logic Designs Using Monolithic 3-D Integration. 1892-1905 - Young-Jin Yoon, Nicola Concer, Michele Petracca, Luca P. Carloni
Virtual Channels and Multiple Physical Networks: Two Alternatives to Improve NoC Performance. 1906-1919 - De Ma, Rongjie Yan, Kai Huang, Min Yu, Siwen Xiu, Haitong Ge, Xiaolang Yan, Ahmed Amine Jerraya:
Performance Estimation Techniques With MPSoC Transaction-Accurate Models. 1920-1933 - Ender Yilmaz, Sule Ozev, Kenneth M. Butler:
Efficient Process Shift Detection and Test Realignment. 1934-1942 - Huan Chen, João Marques-Silva:
A Two-Variable Model for SAT-Based ATPG. 1943-1956 - Irith Pomeranz:
Non-Test Cubes for Test Generation Targeting Hard-to-Detect Faults. 1957-1965 - Amitabh Das, Baris Ege, Santosh Ghosh, Lejla Batina, Ingrid Verbauwhede
Security Analysis of Industrial Test Compression Schemes. 1966-1977 - Srobona Mitra, Ansuman Banerjee, Pallab Dasgupta, Harish Kumar:
Counterexample Ranking Using Mined Invariants. 1978-1991 - Tsung-Po Liu, Shuo-Ren Lin, Jie-Hong R. Jiang:
Software Workarounds for Hardware Errors: Instruction Patch Synthesis. 1992-2003 - Liping Wang, Andrew R. Brown, Binjie Cheng, Asen Asenov:
Analytical Models for Three-Dimensional Ion Implantation Profiles in FinFETs. 2004-2008 - Shahkar Ahmad Nahvi
Piece-wise Quasi-linear Approximation for Nonlinear Model Reduction. 2009-2013 - Wenjian Yu, Tao Zhang, Xiaolong Yuan, Haifeng Qian
Fast 3-D Thermal Simulation for Integrated Circuits With Domain Decomposition Method. 2014-2018 - Smarjeet Sharma, Nicolas G. Constantin:
Formulations for the Estimation of IMD Levels in an Envelope Feedback RFIC Amplifier: An Extension to Dynamic AM and PM Behavior. 2019-2023
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