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Ing-Chao Lin
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2020 – today
- 2024
- [j25]Yu-Guang Chen
, Chieh-Shih Wang, Ing-Chao Lin
Aging-Aware Energy-Efficient Task Deployment of Heterogeneous Multicore Systems. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 43(5): 1580-1593 (2024) - [j24]Chun-Lin Chu
AttentionRC: A Novel Approach to Improve Locality Sensitive Hashing Attention on Dual-Addressing Memory. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 43(11): 3925-3936 (2024) - [c22]Mengnan Jiang, Jingcun Wang, Amro Eldebiky, Xunzhao Yin, Cheng Zhuo, Ing-Chao Lin, Grace Li Zhang:
Class-Aware Pruning for Efficient Neural Networks. DATE 2024: 1-6 - [c21]Yu-Guang Chen, Hsiu-Yi Yang, Ing-Chao Lin:
GNN-Based INC and IVC Co-Optimization for Aging Mitigation. ETS 2024: 1-4 - [i5]Amro Eldebiky, Grace Li Zhang, Xunzhao Yin, Cheng Zhuo, Ing-Chao Lin, Ulf Schlichtmann, Bing Li:
BasisN: Reprogramming-Free RRAM-Based In-Memory-Computing by Basis Combination for Deep Neural Networks. CoRR abs/2407.03738 (2024) - [i4]Jingcun Wang, Yu-Guang Chen, Ing-Chao Lin, Bing Li, Grace Li Zhang:
Basis Sharing: Cross-Layer Parameter Sharing for Large Language Model Compression. CoRR abs/2410.03765 (2024) - 2023
- [c20]Wei-Lun Chen, Fang-Yi Gu, Ing-Chao Lin, Grace Li Zhang, Bing Li, Ulf Schlichtmann:
A Novel and Efficient Block-Based Programming for ReRAM-Based Neuromorphic Computing. ICCAD 2023: 1-9 - [i3]Hoang-Hiep Le, Md. Aftab Baig, Wei-Chen Hong, Cheng-Hsien Tsai, Cheng-Jui Yeh, Fu-Xiang Liang, I-Ting Huang, Wei-Tzu Tsai, Ting-Yin Cheng, Sourav De, Nan-Yow Chen, Wen-Jay Lee, Ing-Chao Lin, Da-Wei Chang, Darsen D. Lu:
CIMulator: A Comprehensive Simulation Platform for Computing-In-Memory Circuit Macros with Low Bit-Width and Real Memory Materials. CoRR abs/2306.14649 (2023) - [i2]Mengnan Jiang, Jingcun Wang, Amro Eldebiky, Xunzhao Yin, Cheng Zhuo, Ing-Chao Lin, Grace Li Zhang:
Class-Aware Pruning for Efficient Neural Networks. CoRR abs/2312.05875 (2023) - 2022
- [j23]Fang-Yi Gu
A Low-Power and High-Accuracy Approximate Multiplier With Reconfigurable Truncation. IEEE Access 10: 60447-60458 (2022) - [j22]Wei Cheng
An Efficient Implementation of Convolutional Neural Network With CLIP-Q Quantization on FPGA. IEEE Trans. Circuits Syst. I Regul. Pap. 69(10): 4093-4102 (2022) - [c19]Po-Yuan Chen, Fang-Yi Gu, Yu-Hong Huang, Ing-Chao Lin:
WRAP: Weight RemApping and Processing in RRAM-based Neural Network Accelerators Considering Thermal Effect. DATE 2022: 1245-1250 - [c18]Wei Cheng
GraphRC: Accelerating Graph Processing on Dual-Addressing Memory with Vertex Merging. ICCAD 2022: 21:1-21:9 - [c17]Yu-Guang Chen, Chi-Hsu Wang, Ing-Chao Lin:
An Aging Detection and Tolerance Framework for 8T SRAM Dot Product CIM Engine. ISOCC 2022: 161-162 - 2021
- [j21]Yu-Guang Chen, Ing-Chao Lin
An efficient NBTI-aware wake-up strategy: Concept, design, and manipulation. Integr. 80: 60-71 (2021) - [j20]Jilan Lin
Rescuing RRAM-Based Computing From Static and Dynamic Faults. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 40(10): 2049-2062 (2021) - [j19]Ing-Chao Lin
A Novel, Efficient Implementation of a Local Binary Convolutional Neural Network. IEEE Trans. Circuits Syst. II Express Briefs 68(4): 1413-1417 (2021) - [c16]Yu-Guang Chen, Ing-Chao Lin, Yong-Che Wei:
A Novel NBTI-Aware Chip Remaining Lifetime Prediction Framework Using Machine Learning. ISQED 2021: 476-481 - [i1]Honggang Yu, Shihfeng Zeng, Teng Zhang, Ing-Chao Lin, Yier Jin:
Exploring Adversarial Examples for Efficient Active Learning in Machine Learning Classifiers. CoRR abs/2109.10770 (2021) - 2020
- [j18]Ing-Chao Lin
Global Clean Page First Replacement and Index-Aware Multistream Prefetcher in Hybrid Memory Architecture. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 39(9): 1750-1763 (2020) - [j17]Ing-Chao Lin
A Novel Comparison-Free 1-D Median Filter. IEEE Trans. Circuits Syst. II Express Briefs 67-II(7): 1329-1333 (2020) - [c15]Ing-Chao Lin, Ulf Schlichtmann, Tsung-Wei Huang, Mark Po-Hung Lin
Overview of 2020 CAD Contest at ICCAD. ICCAD 2020: 67:1-67:3 - [c14]Yu-Guang Chen, Yu-Yi Lin, Ing-Chao Lin:
An NBTI-aware Task Parallelism Scheme for Improving Lifespan of Multi-core Systems. ISQED 2020: 117-122
2010 – 2019
- 2019
- [j16]Jing-Yuan Luo
TAP: Reducing the Energy of Asymmetric Hybrid Last-Level Cache via Thrashing Aware Placement and Migration. IEEE Trans. Computers 68(12): 1704-1719 (2019) - [j15]Da-Wei Chang
OCMAS: Online Page Clustering for Multibank Scratchpad Memory. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 38(2): 220-233 (2019) - [j14]Ing-Chao Lin
Infection-Based Dead Page Prediction in Hybrid Memory Architecture. IEEE Trans. Very Large Scale Integr. Syst. 27(10): 2401-2412 (2019) - [c13]Yu-Guang Chen, Ing-Chao Lin, Jian-Ting Ke:
ROAD: Improving Reliability of Multi-core System via Asymmetric Aging. ICCAD 2019: 1-8 - [c12]Ulf Schlichtmann
Overview of 2019 CAD Contest at ICCAD. ICCAD 2019: 1-2 - 2018
- [j13]Ing-Chao Lin
Mitigating BTI-Induced Degradation in STT-MRAM Sensing Schemes. IEEE Trans. Very Large Scale Integr. Syst. 26(1): 50-62 (2018) - [c11]Kun-Wei Chiu, Yu-Guang Chen, Ing-Chao Lin:
An efficient NBTI-aware wake-up strategy for power-gated designs. DATE 2018: 901-904 - 2017
- [j12]Da-Wei Chang, Ing-Chao Lin
ROHOM: Requirement-Aware Online Hybrid On-Chip Memory Management for Multicore Systems. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 36(3): 357-369 (2017) - [c10]Yun Kae Law, Ing-Chao Lin, Cheng-Chien Lin:
Reducing aging on scratchpad memory using temporal- and FSM-based power management. VLSI-DAT 2017: 1-4 - 2016
- [j11]Ing-Chao Lin, Yen-Han Lee, Sheng-Wei Wang:
Reducing Aging Effects on Ternary CAM. IEICE Trans. Electron. 99-C(7): 878-891 (2016) - 2015
- [j10]Ing-Chao Lin, Yu-Hung Cho, Yi-Ming Yang:
Aging-Aware Reliable Multiplier Design With Adaptive Hold Logic. IEEE Trans. Very Large Scale Integr. Syst. 23(3): 544-556 (2015) - [j9]Ing-Chao Lin, Yi-Ming Yang, Cheng-Chian Lin:
High-Performance Low-Power Carry Speculative Addition With Variable Latency. IEEE Trans. Very Large Scale Integr. Syst. 23(9): 1591-1603 (2015) - [j8]Ing-Chao Lin, Jeng-Nian Chiou:
High-Endurance Hybrid Cache Design in CMP Architecture With Cache Partitioning and Access-Aware Policies. IEEE Trans. Very Large Scale Integr. Syst. 23(10): 2149-2161 (2015) - 2014
- [j7]Ing-Chao Lin, Shun-Ming Syu, Tsung-Yi Ho
NBTI tolerance and leakage reduction using gate sizing. ACM J. Emerg. Technol. Comput. Syst. 11(1): 4:1-4:12 (2014) - [j6]Yi-Hua Li, Wei-Cheng Lien
Capture-Power-Safe Test Pattern Determination for At-Speed Scan-Based Testing. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 33(1): 127-138 (2014) - [j5]Kai-Chiang Wu, Ing-Chao Lin
BTI-Aware Sleep Transistor Sizing Algorithm for Reliable Power Gating Designs. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 33(10): 1591-1595 (2014) - [j4]Da-Wei Chang, Ing-Chao Lin, Yu-Shiang Chien, Ching-Lun Lin, Alvin W. Y. Su, Chung-Ping Young:
CASA: Contention-Aware Scratchpad Memory Allocation for Online Hybrid On-Chip Memory Management. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 33(12): 1806-1817 (2014) - [j3]Ing-Chao Lin, Kuan-Hui Li, Chia-Hao Lin, Kai-Chiang Wu:
NBTI and Leakage Reduction Using ILP-Based Approach. IEEE Trans. Very Large Scale Integr. Syst. 22(9): 2034-2038 (2014) - [c9]Ing-Chao Lin, Yao-Te Wang, Shuen-Shiang Yang, Yi-Luen Wu:
Analyzing the BTI Effect on Multi-bit Retention Registers. ICS 2014: 269-278 - 2013
- [j2]Ing-Chao Lin, Chin-Hung Lin, Kuan-Hui Li:
Leakage and Aging Optimization Using Transmission Gate-Based Technique. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 32(1): 87-99 (2013) - [c8]Shun-Ming Syu, Yu-Hui Shao, Ing-Chao Lin:
High-endurance hybrid cache design in CMP architecture with cache partitioning and access-aware policy. ACM Great Lakes Symposium on VLSI 2013: 19-24 - [c7]Chia-Hao Lin, Ing-Chao Lin:
High accuracy approximate multiplier with error correction. ICCD 2013: 33-38 - [c6]Yen-Han Lee, Ing-Chao Lin, Sheng-Wei Wang:
Impacts of NBTI and PBTI effects on ternary CAM. ISQED 2013: 38-45 - 2012
- [c5]Yu-Hung Cho, Ing-Chao Lin, Yi-Ming Yang:
Aging-aware reliable multiplier design. SoCC 2012: 322-327 - 2011
- [c4]Shi-Qun Zheng, Ing-Chao Lin, Yen-Han Lee:
Analyzing throughput of power and thermal-constraint multicore processor under NBTI effect. ACM Great Lakes Symposium on VLSI 2011: 415-418 - [c3]Chin-Hung Lin, Ing-Chao Lin, Kuan-Hui Li:
TG-based technique for NBTI degradation and leakage optimization. ISLPED 2011: 133-138
2000 – 2009
- 2006
- [c2]Ing-Chao Lin, Suresh Srinivasan, Narayanan Vijaykrishnan, Nagu R. Dhanwada:
Transaction Level Error Susceptibility Model for Bus Based SoC Architectures. ISQED 2006: 775-780 - 2005
- [j1]Nagu R. Dhanwada, Reinaldo A. Bergamaschi, William W. Dungan, Indira Nair, Paul Gramann, William E. Dougherty, Ing-Chao Lin:
Transaction-level modeling for architectural and power analysis of PowerPC and CoreConnect-based systems. Des. Autom. Embed. Syst. 10(2-3): 105-125 (2005) - [c1]Nagu R. Dhanwada, Ing-Chao Lin, Vijaykrishnan Narayanan:
A power estimation methodology for systemC transaction level models. CODES+ISSS 2005: 142-147
Coauthor Index
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last updated on 2024-12-02 21:28 CET by the dblp team
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