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Carl Sechen
Carl M. Sechen
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2020 – today
- 2024
- [c74]Apurva Jain, Thomas Broadfoot, Carl Sechen, Yiorgos Makris:
Testing a Transistor-Level Programmable Fabric: Challenges and Solutions. VTS 2024: 1-7 - 2023
- [c73]Apurva Jain, Thomas Broadfoot, Yiorgos Makris, Carl Sechen:
Quo Vadis Signal? Automated Directionality Extraction for Post-Programming Verification of a Transistor-Level Programmable Fabric. DATE 2023: 1-2 - 2020
- [c72]Bo Hu, Mustafa M. Shihab, Yiorgos Makris
, Benjamin Carrión Schäfer, Carl Sechen:
An Efficient MILP-Based Aging-Aware Floorplanner for Multi-Context Coarse-Grained Runtime Reconfigurable FPGAs. DATE 2020: 1526-1531 - [c71]Vibhav Kumarswami Salimath
Optimal Standard Cell Library Composition for 7nm. ISCAS 2020: 1-5 - [c70]Mustafa M. Shihab, Bharath Ramanidharan, Gaurav Rajavendra Reddy, Jingxiang Tian, William Swartz, Carl Sechen, Yiorgos Makris:
CASPER: CAD Framework for a Novel Transistor-Level Programmable Fabric. ISCAS 2020: 1-5 - [c69]Mustafa Munawar Shihab, Bharath Ramanidharan, Suraag Sunil Tellakula, Gaurav Rajavendra Reddy, Jingxiang Tian, Carl Sechen, Yiorgos Makris
ATTEST: Application-Agnostic Testing of a Novel Transistor-Level Programmable Fabric. VTS 2020: 1-6
2010 – 2019
- 2019
- [c68]Tutu Ajayi, Vidya A. Chhabria
Toward an Open-Source Digital Flow: First Learnings from the OpenROAD Project. DAC 2019: 76 - [c67]Mustafa M. Shihab, Jingxiang Tian, Gaurav Rajavendra Reddy, Bo Hu, William Swartz, Benjamin Carrión Schäfer
Design Obfuscation through Selective Post-Fabrication Transistor-Level Programming. DATE 2019: 528-533 - [c66]Bo Hu, Jingxiang Tian, Mustafa M. Shihab, Gaurav Rajavendra Reddy, William Swartz, Yiorgos Makris
Functional Obfuscation of Hardware Accelerators through Selective Partial Design Extraction onto an Embedded FPGA. ACM Great Lakes Symposium on VLSI 2019: 171-176 - [c65]Bo Hu, Mustafa M. Shihab, Yiorgos Makris
Extending the Lifetime of Coarse-Grained Runtime Reconfigurable FPGAs by Balancing Processing Element Usage. FPT 2019: 291-294 - 2017
- [j21]Meisam Heidarpour Roshan
A MEMS-Assisted Temperature Sensor With 20-µK Resolution, Conversion Rate of 200 S/s, and FOM of 0.04 pJK2. IEEE J. Solid State Circuits 52(1): 185-197 (2017) - [c64]Anitha Kumari Yella, Gunturi Srivatsa, Carl Sechen:
Are standalone gate size and VT optimization tools useful? CCECE 2017: 1-6 - [c63]Jingxiang Tian, Gaurav Rajavendra Reddy, Jiajia Wang, William Swartz, Yiorgos Makris
A field programmable transistor array featuring single-cycle partial/full dynamic reconfiguration. DATE 2017: 1336-1341 - [c62]Thomas Broadfoot, Carl Sechen, Jeyavijayan (JV) Rajendran:
On designing optimal camouflaged layouts. HOST 2017: 169 - 2016
- [c61]Meisam Heidarpour Roshan, Samira Zali Asl, Kimo Joo, Kamran Souri, Rajkumar Palwai, Lijun Will Chen, Sudhakar Pamarti
11.1 Dual-MEMS-resonator temperature-to-digital converter with 40 K resolution and FOM of 0.12pJK2. ISSCC 2016: 200-201 - 2015
- [j20]Zhao Wang, Xiao He, Carl Sechen:
A New Approach for Gate-Level Delay-Insensitive Asynchronous Logic. Circuits Syst. Signal Process. 34(5): 1431-1459 (2015) - 2014
- [c60]Zhao Wang, Xiao He, Carl M. Sechen:
TonyChopper: a desynchronization package. ICCAD 2014: 446-453 - 2013
- [j19]Mohammad Rahman, Hiran Tennakoon, Carl Sechen:
Library-Based Cell-Size Selection Using Extended Logical Effort. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 32(7): 1086-1099 (2013) - [c59]Akshay Sridharan, Carl Sechen, Roozbeh Jafari
Low-voltage low-overhead asynchronous logic. ISLPED 2013: 261-266 - 2012
- [c58]Mohammad Rahman, Carl Sechen:
Post-synthesis leakage power minimization. DATE 2012: 99-104 - 2011
- [c57]Mohammad Rahman, Ryan Afonso, Hiran Tennakoon, Carl Sechen:
Power reduction via separate synthesis and physical libraries. DAC 2011: 627-632 - [c56]Mohammad Rahman, Hiran Tennakoon, Carl Sechen:
Power reduction via near-optimal library-based cell-size selection. DATE 2011: 867-870 - [c55]Chiu-wei Pan, Zhao Wang, Yuanchen Song, Carl Sechen:
Power efficient partial product compression. ACM Great Lakes Symposium on VLSI 2011: 347-350
2000 – 2009
- 2008
- [j18]Hiran Tennakoon, Carl Sechen:
Nonconvex Gate Delay Modeling and Delay Optimization. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 27(9): 1583-1594 (2008) - 2007
- [c54]Sheng Sun, Carl Sechen:
Post-layout comparison of high performance 64b static adders in energy-delay space. ICCD 2007: 401-408 - 2006
- [c53]Jinyao Zhang, Miodrag Vujkovic, David Wadkins, Carl Sechen:
Post-layout energy-delay analysis of parallel multipliers. ISCAS 2006 - [c52]Kian Haur Chong, Larry McMurchie, Carl Sechen:
A 64b adder using self-calibrating differential output prediction logic. ISSCC 2006: 1745-1754 - 2005
- [c51]Xinyu Guo, Carl Sechen:
A high throughput divider implementation. CICC 2005: 507-510 - [c50]Hiran Tennakoon, Carl Sechen:
Efficient and accurate gate sizing with piecewise convex delay models. DAC 2005: 807-812 - [c49]Xinyu Guo, Carl Sechen:
High Speed Redundant Adder and Divider in Output Prediction Logic. ISVLSI 2005: 34-41 - [c48]Sheng Sun, Yi Han, Xinyu Guo, Kian Haur Chong, Larry McMurchie, Carl Sechen:
409ps 4.7 FO4 64b Adder Based on Output Prediction Logic in 0.18um CMOS. ISVLSI 2005: 52-58 - [c47]Miodrag Vujkovic, David Wadkins, Carl Sechen:
Efficient Post-layout Power-Delay Curve Generation. PATMOS 2005: 393-403 - 2004
- [c46]Yi Han, Larry McMurchie, Carl Sechen:
A high performance CMOS programmable logic core. CICC 2004: 439-442 - [c45]Miodrag Vujkovic, David Wadkins, William Swartz, Carl Sechen:
Efficient timing closure without timing driven placement and routing. DAC 2004: 268-273 - 2003
- [j17]Jovanka Ciric, Carl Sechen:
Efficient canonical form for Boolean matching of complex functions in large libraries. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 22(5): 535-544 (2003) - [j16]T. J. Thorp, G. S. Yee, Carl M. Sechen:
Design and synthesis of dynamic circuits. IEEE Trans. Very Large Scale Integr. Syst. 11(1): 141-149 (2003) - [c44]Carl Sechen, Barbara Chappel, Jim Hogan, Andrew Moore, Tadahiko Nakamura, Gregory A. Northrop, Anjaneya Thakar:
Libraries: lifejacket or straitjacket. DAC 2003: 642-643 - [c43]Su Kio, Kian Haur Chong, Carl Sechen:
A low power delayed-clocks generation and distribution system. ISCAS (5) 2003: 445-448 - 2002
- [j15]Gregg N. Hoyer, Gin Yee, Carl Sechen:
Locally clocked pipelines and dynamic logic. IEEE Trans. Very Large Scale Integr. Syst. 10(1): 58-62 (2002) - [c42]Miodrag Vujkovic, Carl Sechen:
Optimized power-delay curve generation for standard cell ICs. ICCAD 2002: 387-394 - [c41]Hiran Tennakoon, Carl Sechen:
Gate sizing using Lagrangian relaxation combined with a fast gradient-based pre-processing step. ICCAD 2002: 395-402 - [c40]Larry McMurchie, Carl Sechen:
WTA: waveform-based timing analysis for deep submicron circuits. ICCAD 2002: 625-631 - [c39]Miodrag Vujkovic, Carl Sechen:
Optimized Power-Delay Curve Generation for Standard Cell ICs. IWLS 2002: 413-418 - 2001
- [j14]Hsiao-Ping Tseng, Louis Scheffer, Carl Sechen:
Timing- and crosstalk-driven area routing. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 20(4): 528-544 (2001) - [c38]Sheng Sun, Larry McMurchie, Carl Sechen:
A High-Performance 64-bit Adder Implemented in Output Prediction Logic. ARVLSI 2001: 213-223 - [c37]Rob A. Rutenbar, Max Baron, Thomas Daniel, Rajeev Jayaraman, Zvi Or-Bach, Jonathan Rose, Carl Sechen:
Panel: (When) Will FPGAs Kill ASICs? DAC 2001: 321-322 - [c36]Tatjana Serdar, Carl Sechen:
Automatic datapath tile placement and routing. DATE 2001: 552-559 - [c35]Jovanka Ciric, Carl Sechen:
Efficient Canonical Form for Boolean Matching of Complex Functions in Large Libraries. ICCAD 2001: 610-617 - 2000
- [j13]Gin Yee, Carl Sechen:
Clock-delayed domino for dynamic circuit design. IEEE Trans. Very Large Scale Integr. Syst. 8(4): 425-430 (2000) - [c34]Gregg N. Hoyer, Carl Sechen:
A locally-clocked dynamic logic serial/parallel multiplier. CICC 2000: 481-484 - [c33]Jovanka Ciric, Gin Yee, Carl Sechen:
Delay Minimization and Technology Mapping of Two-Level Structures and Implementation Using Clock-Delayed Domino Logic. DATE 2000: 277-282 - [c32]Larry McMurchie, Su Kio, Gin Yee, Tyler Thorp, Carl Sechen:
Output Prediction Logic: A High-Performance CMOS Design Technique. ICCD 2000: 247-254 - [c31]Gin Yee, Tyler Thorp, Ron Christopherson, Ban P. Wang, Carl Sechen:
An Automated Shielding Algorithm and Tool For Dynamic Circuits. ISQED 2000: 369-374
1990 – 1999
- 1999
- [j12]Le-Chin Eugene Liu, Carl Sechen:
Multilayer chip-level global routing using an efficient graph-based Steiner tree heuristic. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 18(10): 1442-1451 (1999) - [j11]Le-Chin Eugene Liu, Carl Sechen:
Multilayer pin assignment for macro cell circuits. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 18(10): 1452-1461 (1999) - [j10]Hsiao-Ping Tseng, Carl Sechen:
A gridless multilayer router for standard cell circuits using CTMcells. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 18(10): 1462-1479 (1999) - [c30]Tatjana Serdar, Carl Sechen:
AKORD: transistor level and mixed transistor/gate level placement tool for digital data paths. ICCAD 1999: 91-97 - [c29]Tyler Thorp, Gin Yee, Carl Sechen:
Design and Synthesis of Monotonic Circuits. ICCD 1999: 569-572 - 1998
- [c28]Hsiao-Ping Tseng, Louis Scheffer, Carl Sechen:
Timing and Crosstalk Driven Area Routing. DAC 1998: 378-381 - [c27]Tyler Thorp, Gin Yee, Carl Sechen:
Domino logic synthesis using complex static gates. ICCAD 1998: 242-247 - [c26]Le-Chin Eugene Liu, Hsiao-Ping Tseng, Carl Sechen:
Chip-level area routing. ISPD 1998: 197-204 - 1997
- [j9]Qicheng Yu, Carl Sechen:
Efficient approximation of symbolic network functions using matroid intersection algorithms. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 16(10): 1073-1081 (1997) - [j8]Wern-Jieh Sun, Carl Sechen:
A parallel standard cell placement algorithm. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 16(11): 1342-1357 (1997) - [c25]Martin Lefebvre, David Marple, Carl Sechen:
The Future of Custom Cell Generation in Physical Synthesis. DAC 1997: 446-451 - [c24]Le-Chin Eugene Liu, Carl Sechen:
Multi-layer chip-level global routing using an efficient graph-based Steiner tree heuristic. ED&TC 1997: 311-318 - [c23]Hsiao-Ping Tseng, Carl Sechen:
A gridless multi-layer router for standard cell circuits using CTM cells. ED&TC 1997: 319-326 - 1996
- [j7]Qicheng Yu, Carl Sechen:
Generation of colour-constrained spanning trees with application in symbolic circuit analysis. Int. J. Circuit Theory Appl. 24(5): 597-603 (1996) - [j6]Kalapi Roy-Neogi, Bingzhong Guan, Carl Sechen:
A Sea-of-Gates Style FPGA Placement Algorithm. VLSI Design 4(4): 293-307 (1996) - [j5]Kalapi Roy-Neogi, Carl Sechen:
A Timing-Driven Partitioning System for Multiple FPGAs. VLSI Design 4(4): 309-328 (1996) - [c22]Gin Yee, Carl Sechen:
Clock-Delayed Domino for Adder and Combinational Logic Desig. ICCD 1996: 332-337 - [c21]Bingzhong Guan, Carl Sechen:
Large Standard Cell Libraries and Their Impact on Layout Area and Circuit Performanc. ICCD 1996: 378-383 - 1995
- [j4]Wern-Jieh Sun, Carl Sechen:
Efficient and effective placement for very large circuits. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 14(3): 349-359 (1995) - [j3]Ted Stanion, Debashis Bhattacharya, Carl Sechen:
An efficient method for generating exhaustive test sets. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 14(12): 1516-1525 (1995) - [c20]Ted Stanion, Carl Sechen:
Quasi-algebraic decompositions of switching functions. ARVLSI 1995: 358-367 - [c19]Ted Stanion, Carl Sechen:
A Method for Finding Good Ashenhurst Decompositions and Its Application to FPGA Synthesis. DAC 1995: 60-64 - [c18]William Swartz, Carl Sechen:
Timing Driven Placement for Large Standard Cell Circuits. DAC 1995: 211-215 - [c17]Kalapi Roy-Neogi, Carl Sechen:
Multiple FPGA Partitioning with Performance Optimization. FPGA 1995: 146-152 - [c16]Jer-Jaw Hsu, Carl Sechen:
Accurate Extraction of Simplified Symbolic Pole/Zero Expressions for Large Analog IC's. ISCAS 1995: 2083-2087 - [c15]Qicheng Yu, Carl Sechen:
Efficient Approximation of Symbolic Network Function Using Matroid Intersection Algorithms. ISCAS 1995: 2088-2091 - 1994
- [j2]Ted Stanion, Carl Sechen:
Boolean division and factorization using binary decision diagrams. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 13(9): 1179-1184 (1994) - [c14]Qicheng Yu, Carl Sechen:
Generation of color-constrained spanning trees with application in symbolic circuit analysis. Great Lakes Symposium on VLSI 1994: 252-255 - [c13]Wern-Jieh Sun, Carl Sechen:
A loosely coupled parallel algorithm for standard cell placement. ICCAD 1994: 137-144 - [c12]Qicheng Yu, Carl Sechen:
Approximate symbolic analysis of large analog integrated circuits. ICCAD 1994: 664-671 - [c11]Kalapi Roy-Neogi, Bingzhong Guan, Carl Sechen:
A Sea-of-Gates Style FPGA Placement Algorithm. VLSI Design 1994: 221-224 - 1993
- [c10]Wern-Jieh Sun, Carl Sechen:
Efficient and effective placement for very large circuits. ICCAD 1993: 170-177 - [c9]William Swartz, Carl Sechen:
A new generalized row-based global router. ICCAD 1993: 491-498 - [c8]Ted Stanion, Carl Sechen:
Maximum projections of don't care conditions in a Boolean network. ICCAD 1993: 674-679 - 1991
- [c7]Kai-Win Lee, Carl Sechen:
A global router for sea-of-gates circuits. EURO-DAC 1991: 237-241 - [c6]Dahe Chen, Carl Sechen:
Mickey: a macro cell global router. EURO-DAC 1991: 248-252 - 1990
- [c5]William Swartz, Carl Sechen:
New Algorithms for the Placement and Routing of Macro Cells. ICCAD 1990: 336-339
1980 – 1989
- 1988
- [j1]Carl Sechen, Douglas Braun, Alberto L. Sangiovanni-Vincentelli:
ThunderBird: a complete standard cell layout package. IEEE J. Solid State Circuits 23(2): 410-420 (1988) - [c4]Carl Sechen:
Chip-Planning, Placement, and Global Routing of Macro/Custom Cell Integrated Circuits Using Simulated Annealing. DAC 1988: 73-80 - [c3]Kai-Win Lee, Carl Sechen:
A new global router for row-based layout. ICCAD 1988: 180-183 - [c2]Carl Sechen, Dahe Chen:
An improved objective function for mincut circuit partitioning. ICCAD 1988: 502-505 - 1986
- [c1]Carl Sechen, Alberto L. Sangiovanni-Vincentelli:
TimberWolf3.2: a new standard cell placement and global routing package. DAC 1986: 432-439
Coauthor Index
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