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VLSIC 2012: Honolulu, HI, USA
- Symposium on VLSI Circuits, VLSIC 2012, Honolulu, HI, USA, June 13-15, 2012. IEEE 2012, ISBN 978-1-4673-0848-9
- Ajith Amerasekera, Makoto Nagata
:
Foreword. 1-2 - Nick Ilyadis:
The evolution of next-generation data center networks for high capacity computing. 1-5 - Akira Maeda:
Technology innovations for smart cities. 6-9 - Dongha Shim, Dimitrios Koukis, Daniel J. Arenas, David B. Tanner, Eunyoung Seok, Joe E. Brewer, Kenneth K. O:
Components for generating and phase locking 390-GHz signal in 45-nm CMOS. 10-11 - Wei-Zen Chen, Tai-You Lu, Yan-Ting Wang, Jhong-Ting Jian, Yi-Hung Yang, Guo-Wei Huang, Wen-De Liu, Chih-Hua Hsiao, Shu-Yu Lin, Jung Yen Liao:
A 160-GHz receiver-based phase-locked loop in 65 nm CMOS technology. 12-13 - Keng-Jan Hsiao:
A 32.4 ppm/°C 3.2-1.6V self-chopped relaxation oscillator with adaptive supply generation. 14-15 - Takashi Tokairin, Koichi Nose, Koichi Takeda, Koichiro Noguchi, Tadashi Maeda, Kazuyoshi Kawai, Masayuki Mizuno:
A 280nW, 100kHz, 1-cycle start-up time, on-chip CMOS relaxation oscillator employing a feedforward period control scheme. 16-17 - Xicheng Jiang, Jungwoo Song, Minsheng Wang, Jianlong Chen, Sasi Kumar Arunachalam, Todd L. Brooks:
Circuit techniques to overcome Class-D audio amplifier limitations in mobile devices. 18-19 - Shon-Hang Wen, Cheng-Chung Yang:
A 5.2mW, 0.0016% THD up to 20kHz, ground-referenced audio decoder with PSRR-enhanced class-AB 16Ω headphone amplifiers. 20-21 - Shinya Sano, Yasuhiko Takahashi, Masashi Horiguchi, Moriyoshi Ota:
A sub-1V 3.9µW bandgap reference with a 3σ inaccuracy of ±0.34% from -50°C to +150°C using piecewise-linear-current curvature compensation. 22-23 - Zhichao Tan, Youngcheol Chae, Roel Daamen, Aurelie Humbert, Youri V. Ponomarev, Michiel A. P. Pertijs:
A 1.2V 8.3nJ energy-efficient CMOS humidity sensor for RFID applications. 24-25 - Yun-Shiang Shu:
A 6b 3GS/s 11mW fully dynamic flash ADC in 40nm CMOS with reduced number of comparators. 26-27 - Colin Weltin-Wu, Yannis P. Tsividis:
An event-driven, alias-free ADC with signal-dependent resolution. 28-29 - Bibhudatta Sahoo, Behzad Razavi:
A 10-bit 1-GHz 33-mW CMOS ADC. 30-31 - Benjamin P. Hershberg, Skyler Weaver, Kazuki Sobue, Seiji Takeuchi, Koichi Hamashita, Un-Ku Moon:
A 61.5dB SNDR pipelined ADC using simple highly-scalable ring amplifiers. 32-33 - Arun Paidimarri
A 440pJ/bit 1Mb/s 2.4GHz multi-channel FBAR-based TX and an integrated pulse-shaping PA. 34-35 - Vahid Majidzadeh, Alexandre Schmid
An 8-PPM, 45 pJ/bit UWB transmitter with reduced number of PA elements. 36-37 - Akira Saito, Kentaro Honda, Yun Fei Zheng, Shunta Iguchi, Kazunori Watanabe, Takayasu Sakurai, Makoto Takamiya:
An all 0.5V, 1Mbps, 315MHz OOK transceiver with 38-µW career-frequency-free intermittent sampling receiver and 52-µW class-F transmitter in 40-nm CMOS. 38-39 - Ronghua Ni, Kartikeya Mayaram, Terri S. Fiez:
A 2.4GHz hybrid PPF based BFSK receiver with ±180ppm frequency offset tolerance for wireless sensor networks. 40-41 - Xiaoyong Xue, W. X. Jian, Jianguo Yang, F. J. Xiao, G. Chen, X. L. Xu, Y. F. Xie, Yinyin Lin, R. Huang, Q. T. Zhou, J. G. Wu:
A 0.13µm 8Mb logic based CuxSiyO resistive memory with self-adaptive yield enhancement and operation power reduction. 42-43 - Shoun Matsunaga, Sadahiko Miura, Hiroaki Honjou, Keizo Kinoshita, Shoji Ikeda
A 3.14 um2 4T-2MTJ-cell fully parallel TCAM based on nonvolatile logic-in-memory architecture. 44-45 - Takashi Ohsawa
1Mb 4T-2MTJ nonvolatile STT-RAM for embedded memories using 32b fine-grained power gating technique with 1.0ns/200ps wake-up/power-off times. 46-47 - Jung-Dong Park, Shinwon Kang, Siva V. Thyagarajan, Elad Alon, Ali M. Niknejad:
A 260 GHz fully integrated CMOS transceiver for wireless chip-to-chip communication. 48-49 - Naoko Ono, Mizuki Motoyoshi, Kyoya Takano
135 GHz 98 mW 10 Gbps ASK transmitter and receiver chipset in 40 nm CMOS. 50-51 - Lingkai Kong, Elad Alon:
A 21.5mW 10+Gb/s mm-Wave phased-array transmitter in 65nm CMOS. 52-53 - Chang-Ming Lai, Kai-Wen Tan, Liu-Yuan Yu, Yen-Ju Chen, Jun-Wei Huang, Shr-Chau Lai, Feng-Hsu Chung, Chia-Fung Yen, Jen-Ming Wu, Po-Chiun Huang, Keh-Jeng Chang, Shi-Yu Huang, Ta-Shun Chu:
A UWB IR timed-array radar using time-shifted direct-sampling architecture. 54-55 - Amin Arbabian, Shinwon Kang, Steven Callender, Jun-Chau Chien, Bagher Afshar, Ali M. Niknejad:
A 94GHz mm-wave to baseband pulsed-radar for imaging and gesture recognition. 56-57 - Noriaki Maeda, Shigenobu Komatsu, Masao Morimoto, Yasuhisa Shimazaki:
A 0.41µA standby leakage 32Kb embedded SRAM with Low-Voltage resume-standby utilizing all digital current comparator in 28nm HKMG CMOS. 58-59 - Shinichi Moriwaki, Yasuhiro Yamamoto, Atsushi Kawasumi, Toshikazu Suzuki, Shinji Miyano, Takayasu Sakurai, Hirofumi Shinohara:
A 13.8pJ/Access/Mbit SRAM with charge collector circuits for effective use of non-selected bit line charges. 60-61 - Peter Kuoyuan Hsu, Yukit Tang, Derek Tao, Ming-Chieh Huang, Min-Jer Wang, C. H. Wu, Quincy Lee:
A SRAM cell array with adaptive leakage reduction scheme for data retention in 28nm high-k metal-gate CMOS. 62-63 - Robin Lee, Jung-Ping Yang, Chia-En Huang, Chih-Chieh Chiu, Wei-Shuo Kao, Hong-Chen Cheng, Hong-Jen Liao, Jonathan Chang:
A 28nm high-k metal-gate SRAM with Asynchronous Cross-Couple Read Assist (AC2RA) circuitry achieving 3x reduction on speed variation for single ended arrays. 64-65 - Marcus Yip, Jose L. Bohorquez, Anantha P. Chandrakasan:
A 0.6V 2.9µW mixed-signal front-end for ECG monitoring. 66-67 - Srinjoy Mitra, Jiawei Xu, Akinori Matsumoto, Kofi A. A. Makinwa, Chris Van Hoof
A 700µW 8-channel EEG/contact-impedance acquisition system for dry-electrodes. 68-69 - Hyo-Gyuem Rhew, Jaehun Jeong, Jeffrey A. Fredenburg, Sunjay Dodani, Parag G. Patil, Michael P. Flynn:
A wirelessly powered log-based closed-loop deep brain stimulation SoC with two-way wireless telemetry for treatment of neurological disorders. 70-71 - Daniel J. Yeager, William Biederman, Nathan Narevsky, Elad Alon, Jan M. Rabaey:
A fully-integrated 10.5µW miniaturized (0.125mm2) wireless neural sensor. 72-73 - Daisuke Miyashita, Kenichi Agawa, Hirotsugu Kajihara, Kenichi Sami, Masaomi Iwanaga, Yosuke Ogasawara, Tomohiko Ito, Daisuke Kurose, Naotaka Koide, Toru Hashimoto, Hiroki Sakurai, Takafumi Yamaji, Takashi Kurihara, Kazumi Sato, Ichiro Seto, Hiroshi Yoshida, Ryuichi Fujimoto, Yasuo Unekawa:
A -70dBm-sensitivity 522Mbps 0.19nJ/bit-TX 0.43nJ/bit-RX transceiver for TransferJet™ SoC in 65nm CMOS. 74-75 - Yulin Tan, Jon Duster, Chang-Tsung Fu, Erkan Alpman, Ajay Balankutty, Chun C. Lee, Ashoke Ravi, Stefano Pellerano, Kailash Chandrashekar, Hyung Seok Kim, Brent R. Carlton, Satoshi Suzuki, M. Shafi, Yorgos Palaskas, Hasnain Lakdawala:
A 2.4GHz WLAN transceiver with fully-integrated highly-linear 1.8V 28.4dBm PA, 34dBm T/R switch, 240MS/s DAC, 320MS/s ADC, and DPLL in 32nm SoC CMOS. 76-77 - Kohei Onizuka, Shigehito Saigusa, Shoji Otaka:
A +30.5 dBm CMOS Doherty power amplifier with reliability enhancement technique. 78-79 - Joung Won Park, Behzad Razavi:
A harmonic-rejecting CMOS LNA for broadband radios. 80-81 - Mohyee Mikhemar, Ahmad Mirzaei, Amir Hadji-Abdolhamid, Janice Chiu, Hooman Darabi:
A 13.5mA sub-2.5dB NF multi-band receiver. 82-83 - Dusan Stepanovic, Borivoje Nikolic
A 2.8GS/s 44.6mW time-interleaved ADC achieving 50.9dB SNDR and 3dB effective resolution bandwidth of 1.5GHz in 65nm CMOS. 84-85 - Chi-Hang Chan, Yan Zhu, Sai-Weng Sin
A 3.8mW 8b 1GS/s 2b/cycle interleaving SAR ADC with compact DAC structure. 86-87 - Yuan-Ching Lien:
A 4.5-mW 8-b 750-MS/s 2-b/step asynchronous subranged SAR ADC in 28-nm CMOS technology. 88-89 - Yan Zhu, Chi-Hang Chan, Sai-Weng Sin
A 34fJ 10b 500 MS/s partial-interleaving pipelined SAR ADC. 90-91 - Hung-Yen Tai, Hung-Wei Chen, Hsin-Shu Chen
A 3.2fJ/c.-s. 0.35V 10b 100KS/s SAR ADC in 90nm CMOS. 92-93 - Keith A. Bowman
A 22nm dynamically adaptive clock distribution for voltage droop tolerance. 94-95 - Michael S. Floyd, Alan J. Drake, Robert W. Berry, Harold Chase, Richard L. Willaman, Jarom Peña:
Voltage droop reduction using throttling controlled by timing margin feedback. 96-97 - Mozhgan Mansuri, Bryan Casper, Frank O'Mahony:
An on-die all-digital delay measurement circuit with 250fs accuracy. 98-99 - Atsushi Kawasumi, Yasuhisa Takeyama, Osamu Hirabayashi, Keiichi Kushida, Fumihiko Tachibana, Yusuke Niki, Shinichi Sasaki, Tomoaki Yabe:
A 47% access time reduction with a worst-case timing-generation scheme utilizing a statistical method for ultra low voltage SRAMs. 100-101 - Thomas Toifl, Michael Ruegg, Rajesh Inti, Christian Menolfi, Matthias Braendli
A 3.1mW/Gbps 30Gbps quarter-rate triple-speculation 15-tap SC-DFE RX data path in 32nm CMOS. 102-103 - Jafar Savoj, Kenny C.-H. Hsieh, Parag Upadhyaya, Fu-Tai An, Ade Bekele, Stanley Chen, Xuewen Jiang, Kang Wei Lai, Chi Fung Poon, Aman Sewani, Didem Turker, Karthik Venna, Zhaoyin Daniel Wu, Bruce Xu, Elad Alon, Ken Chang:
A wide common-mode fully-adaptive multi-standard 12.5Gb/s backplane transceiver in 28nm CMOS. 104-105 - Takashi Takemoto, Hiroki Yamashita, Takehito Kamimura, Fumio Yuki, Noboru Masuda, Hidehiro Toyoda, Norio Chujo, Kenji Kogo, Yong Lee, Shinji Tsuji, Shinji Nishimura:
A 25-Gb/s 2.2-W optical transceiver using an analog FE tolerant to power supply noise and redundant data format conversion in 65-nm CMOS. 106-107 - Tamer A. Ali, Won Ho Park, Preeti Mulage, E-Hung Chen, Ron Ho, Chih-Kong Ken Yang:
A 100+ meter 12Gb/s/lane copper cable link based on clock-forwarding. 108-109 - John Barth, Don Plass, Adis Vehabovic, Rajiv V. Joshi, Rouwaida Kanj, Steven Burns, Todd Weaver:
Isolated Preset Architecture for a 32nm SOI embedded DRAM macro. 110-111 - Ming-Pin Chen, Lai-Fu Chen, Meng-Fan Chang, Shu-Meng Yang, Yao-Jen Kuo, Jui-Jen Wu, Mon-Shu Ho, Hsiu-Yun Su, Yuan-Hua Chu, Wen-Chin Wu, Tzu-Yi Yang, Hiroyuki Yamauchi
A 260mV L-shaped 7T SRAM with bit-line (BL) Swing expansion schemes based on boosted BL, asymmetric-VTH read-port, and offset cell VDD biasing techniques. 112-113 - Youn Sung Park, David T. Blaauw, Dennis Sylvester, Zhengya Zhang
A 1.6-mm2 38-mW 1.5-Gb/s LDPC decoder enabled by refresh-free embedded DRAM. 114-115 - Igor Arsovski, Travis Hebig, Daniel Dobson, Reid Wistort:
1Gsearch/sec Ternary Content Addressable Memory compiler with silicon-aware Early-Predict Late-Correct single-ended sensing. 116-117 - Steven Hsu, Amit Agarwal, Mark A. Anders, Himanshu Kaul, Sanu Mathew, Farhana Sheikh
A 2.8GHz 128-entry × 152b 3-read/2-write multi-precision floating-point register file and shuffler in 32nm CMOS. 118-119 - Yingzhe Hu, Warren Rieutort-Louis, Josue Sanz-Robinson, Katherine W. Song
High-resolution sensing sheet for structural-health monitoring via scalable interfacing of flexible electronics with high-performance ICs. 120-121 - Hamed Mazhab-Jafari, Leyla Soleymani, Karim Abdelhalim, Edward H. Sargent, Shana O. Kelley
Nanostructured CMOS wireless ultra-wideband label-free DNA analysis SoC. 122-123 - Che-Wei Huang, Yu-Jie Huang, Pei-Wen Yen, Hsiao-Ting Hsueh, Chia-Yi Lin, Min-Cheng Chen, Chia-Hua Ho, Fu-Liang Yang, Hann-Huei Tsai, Hsin-Hao Liao, Ying-Zong Juang, Chorng-Kuang Wang, Chih-Ting Lin
A fully integrated hepatitis B virus DNA detection SoC based on monolithic polysilicon nanowire CMOS process. 124-125 - Arun Manickam, Rituraj Singh, Nicholas Wood, Bingling Li, Andrew D. Ellington, Arjang Hassibi:
A fully-electronic charge-based DNA sequencing CMOS biochip. 126-127 - Arnaud Peizerat, Jean-Pierre Rostaing, Noureddine Zitouni, Nicolas Baier, Fabrice Guellec
An 88dB SNR, 30µm pixel pitch Infra-Red image sensor with a 2-step 16 bit A/D conversion. 128-129 - Seung-Hwan Song, Ki Chul Chun, Chris H. Kim:
A logic-compatible embedded flash memory featuring a multi-story high voltage switch and a selective refresh scheme. 130-131 - Seung-Hwan Shin, Dong-Kyo Shim, Jaeyong Jeong, Ohsuk Kwon, Sangyong Yoon, Myung-Hoon Choi, Tae-Young Kim, Hyun Wook Park, Hyun-Jun Yoon, Youngsun Song, Yoon-Hee Choi, Sang-Won Shim, Yang-Lo Ahn, Ki-Tae Park, Jin-Man Han, Kyehyun Kyung, Young-Hyun Jun:
A new 3-bit programming algorithm using SLC-to-TLC migration for 8MB/s high performance TLC NAND flash memory. 132-133 - Hiroki Fujii, Kousuke Miyaji, Koh Johguchi, Kazuhide Higuchi, Chao Sun, Ken Takeuchi:
x11 performance increase, x6.9 endurance enhancement, 93% energy reduction of 3D TSV-integrated hybrid ReRAM/MLC NAND SSDs by data fragmentation suppression. 134-135 - Yong-Sung Cho, Il-Han Park, Sangyong Yoon, Nam-Hee Lee, Sang-Hyun Joo, Ki-Whan Song, Kihwan Choi, Jin-Man Han, Kyehyun Kyung, Young-Hyun Jun:
Adaptive multi-pulse program scheme based on tunneling speed classification for next generation multi-bit/cell NAND FLASH. 136-137 - Jun Won Jung, Behzad Razavi:
A 25-Gb/s 5-mWCMOS CDR/deserializer. 138-139 - Taehyoun Oh, Ramesh Harjani:
4×12 Gb/s 0.96 pJ/b/lane analog-IIR crosstalk cancellation and signal reutilization receiver for single-ended I/Os in 65 nm CMOS. 140-141 - Kiichi Niitsu
A clock jitter reduction circuit using gated phase blending between self-delayed clock edges. 142-143 - Sang-Hye Chung, Lee-Sup Kim:
1.22mW/Gb/s 9.6Gb/s data jitter mixing forwarded-clock receiver robust against power noise with 1.92ns latency mismatch between data and clock in 65nm CMOS. 144-145 - Daniel Fainstein, Sami Rosenblatt, Alberto Cestero, Norman Robson, Toshiaki Kirihata, Subramanian S. Iyer:
Dynamic intrinsic chip ID using 32nm high-K/metal gate SOI embedded DRAM. 146-147 - Arijit Raychowdhury, Dinesh Somasekhar, James W. Tschanz, Vivek De:
A fully-digital phase-locked low dropout regulator in 32nm CMOS. 148-149 - Hui Xu, Jun Tanabe, Hiroyuki Usui, Soichiro Hosoda, Toru Sano, Kazumasa Yamamoto, Takeshi Kodaka, Nobuhiro Nonogaki, Nau Ozaki, Takashi Miyamori:
A low power many-core SoC with two 32-core clusters connected by tree based NoC for multimedia applications. 150-151 - Yi-Min Tsai, Tien-Ju Yang, Chih-Chung Tsai, Keng-Yen Huang, Liang-Gee Chen
A 69mW 140-meter/60fps and 60-meter/300fps intelligent vision SoC for versatile automotive applications. 152-153 - Dajiang Zhou, Gang He, Wei Fei, Zhixiang Chen, Jinjia Zhou
A 4320p 60fps H.264/AVC intra-frame encoder chip with 1.41Gbins/s CABAC. 154-155 - Shu-Yu Hsu, Yingchieh Ho, Yuhwai Tseng, Ting-You Lin
A sub-100µW multi-functional cardiac signal processor for mobile healthcare applications. 156-157 - Tsung-Te Liu, Jan M. Rabaey:
A 0.25V 460nW asynchronous neural signal processor with inherent leakage suppression. 158-159 - Kazuo Matsukawa, Koji Obata, Yosuke Mitani, Shiro Dosho:
A 10 MHz BW 50 fJ/conv. continuous time ΔΣ modulator with high-order single opamp integrator using optimization-based design method. 160-161 - Taehwan Oh, Nima Maghari, Un-Ku Moon:
A 5MHz BW 70.7dB SNDR noise-shaped two-step quantizer based ΔΣ ADC. 162-163 - Seung-Chul Lee, Brian Elies, Yun Chiu
An 85dB SFDR 67dB SNDR 8OSR 240MS/s ΔΣ ADC with nonlinear memory error calibration. 164-165 - Gerry Taylor, Ian Galton:
A reconfigurable mostly-digital ΔΣ ADC with a worst-case FOM of 160dB. 166-167 - Manideep Gande, Nima Maghari, Taehwan Oh, Un-Ku Moon:
A 71dB dynamic range third-order ΔΣ TDC using charge-pump. 168-169 - Liang-Teck Pang, Phillip J. Restle, Matthew R. Wordeman, Joel A. Silberman, Robert L. Franch, Gary W. Maier:
A shorted global clock design for multi-GHz 3D stacked chips. 170-171 - Hamid Partovi, Alfred Yeung, Luca Ravezzi, Mark Horowitz:
A 3-stage Pseudo Single-phase Flip-flop family. 172-173 - Sudhir Satpathy, Dennis Sylvester, David T. Blaauw:
A standard cell compatible bidirectional repeater with thyristor assist. 174-175 - Mark A. Ferriss, Jean-Olivier Plouchart, Arun Natarajan, Alexander V. Rylyakov, Benjamin D. Parker, Aydin Babakhani, Soner Yaldiz, Bodhisatwa Sadhu
An integral path self-calibration scheme for a 20.1-26.7GHz dual-loop PLL in 32nm SOI CMOS. 176-177 - Yu-Huei Lee, Shen-Yu Peng, Alex Chun-Hsien Wu, Chao-Chang Chiu, Yao-Yi Yang, Ming-Hsin Huang, Ke-Horng Chen
A 50nA quiescent current asynchronous digital-LDO with PLL-modulated fast-DVS power management in 40nm CMOS for 5.6 times MIPS performance. 178-179 - Sung-Wan Hong, Tae-Hwang Kong, Seungchul Jung, Sungwoo Lee, Se-Won Wang, Jong-Pil Im, Gyu-Hyeong Cho:
High area-efficient DC-DC converter using Time-Mode Miller Compensation (TMMC). 180-181 - Qadeer Khan, Amr Elshazly, Sachin Rao, Rajesh Inti, Pavan Kumar Hanumolu:
A 900mA 93% efficient 50µA quiescent current fixed frequency hysteretic buck converter using a highly digital hybrid voltage- and current-mode control. 182-183 - Yi Zhang, Hai Chen, Dongsheng Ma:
A 198-ns/V VO-hopping reconfigurable RGB LED driver with automatic ΔVO detection and quasi-constant-frequency predictive peak current control. 184-185 - Chun-Yuan Cheng, Jinn-Shyan Wang, Cheng-Tai Yeh, Jenn-Shyan Sheu:
Design of a 2.5-GHz, 3-ps jitter, 8-locking-cycle, all-digital delay-locked loop with cycle-by-cycle phase adjustment. 186-187 - Amr Elshazly, Rajesh Inti, Mrunmay Talegaonkar, Pavan Kumar Hanumolu:
A 1.5GHz 1.35mW -112dBc/Hz in-band noise digital phase-locked loop with 50fs/mV supply-noise sensitivity. 188-189 - Toshihiro Konishi, Keisuke Okuno, Shintaro Izumi, Masahiko Yoshimoto, Hiroshi Kawaguchi
A 61-dB SNDR 700 µm2 second-order all-digital TDC with low-jitter frequency shift oscillators and dynamic flipflops. 190-191 - KwangSeok Kim, Young-Hwa Kim, Wonsik Yu, SeongHwan Cho:
A 7b, 3.75ps resolution two-step time-to-digital converter in 65nm CMOS using pulse-train time amplifier. 192-193 - Xin Zhang, Po-Hung Chen, Yoshikatsu Ryu, Koichi Ishida, Yasuyuki Okuma, Kazunori Watanabe, Takayasu Sakurai, Makoto Takamiya:
A 0.45-V input on-chip gate boosted (OGB) buck converter in 40-nm CMOS with more than 90% efficiency in load range from 2µW to 50µW. 194-195 - Hao-Yen Tang, Po-Shuan Weng, Po-Chih Ku, Liang-Hung Lu:
A fully electrical startup batteryless boost converter with 50mV input voltage for thermoelectric energy harvesting. 196-197 - Liechao Huang, Warren Rieutort-Louis, Yingzhe Hu, Josue Sanz-Robinson, Sigurd Wagner, James C. Sturm, Naveen Verma:
Integrated all-silicon thin-film power electronics on flexible sheets for ubiquitous wireless charging stations based on solar-energy harvesting. 198-199 - Yen-Po Chen, Matthew Fojtik, David T. Blaauw, Dennis Sylvester:
A 2.98nW bandgap voltage reference using a self-tuning low leakage sample and hold. 200-201 - Inhee Lee, Suyoung Bang, Yoonmyung Lee
A 635pW battery voltage supervisory circuit for miniature sensor nodes. 202-203
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