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  e.g., sig matches "SIGIR" as well as "signal"
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Update May 7, 2017: Please note that we had to disable the phrase search operator (.) and the boolean not operator (-) due to technical problems. For the time being, phrase search queries will yield regular prefix search result, and search terms preceded by a minus will be interpreted as regular (positive) search terms.

found 101 matches

• 2012
• 
  Yan Zhu, Chi-Hang Chan, Sai-Weng Sin, Seng-Pan U, Rui Paulo Martins:
  A 34fJ 10b 500 MS/s partial-interleaving pipelined SAR ADC. VLSIC 2012: 90-91
• 
  Tamer A. Ali, Won Ho Park, Preeti Mulage, E-Hung Chen, Ron Ho, Chih-Kong Ken Yang:
  A 100+ meter 12Gb/s/lane copper cable link based on clock-forwarding. VLSIC 2012: 108-109
• 
  Ajith Amerasekera, Makoto Nagata:
  Foreword. VLSIC 2012: 1-2
• 
  Amin Arbabian, Shinwon Kang, Steven Callender, Jun-Chau Chien, Bagher Afshar, Ali M. Niknejad:
  A 94GHz mm-wave to baseband pulsed-radar for imaging and gesture recognition. VLSIC 2012: 56-57
• 
  Igor Arsovski, Travis Hebig, Daniel Dobson, Reid Wistort:
  1Gsearch/sec Ternary Content Addressable Memory compiler with silicon-aware Early-Predict Late-Correct single-ended sensing. VLSIC 2012: 116-117
• 
  John Barth, Don Plass, Adis Vehabovic, Rajiv V. Joshi, Rouwaida Kanj, Steven Burns, Todd Weaver:
  Isolated Preset Architecture for a 32nm SOI embedded DRAM macro. VLSIC 2012: 110-111
• 
  Keith A. Bowman, Carlos Tokunaga, Tanay Karnik, Vivek K. De, Jim Tschanz:
  A 22nm dynamically adaptive clock distribution for voltage droop tolerance. VLSIC 2012: 94-95
• 
  Chi-Hang Chan, Yan Zhu, Sai-Weng Sin, Seng-Pan U, Rui Paulo Martins:
  A 3.8mW 8b 1GS/s 2b/cycle interleaving SAR ADC with compact DAC structure. VLSIC 2012: 86-87
• 
  Ming-Pin Chen, Lai-Fu Chen, Meng-Fan Chang, Shu-Meng Yang, Yao-Jen Kuo, Jui-Jen Wu, Mon-Shu Ho, Hsiu-Yun Su, Yuan-Hua Chu, Wen-Chin Wu, Tzu-Yi Yang, Hiroyuki Yamauchi:
  A 260mV L-shaped 7T SRAM with bit-line (BL) Swing expansion schemes based on boosted BL, asymmetric-VTH read-port, and offset cell VDD biasing techniques. VLSIC 2012: 112-113
• 
  Yen-Po Chen, Matthew Fojtik, David T. Blaauw, Dennis Sylvester:
  A 2.98nW bandgap voltage reference using a self-tuning low leakage sample and hold. VLSIC 2012: 200-201
• 
  Wei-Zen Chen, Tai-You Lu, Yan-Ting Wang, Jhong-Ting Jian, Yi-Hung Yang, Guo-Wei Huang, Wen-De Liu, Chih-Hua Hsiao, Shu-Yu Lin, Jung Yen Liao:
  A 160-GHz receiver-based phase-locked loop in 65 nm CMOS technology. VLSIC 2012: 12-13
• 
  Chun-Yuan Cheng, Jinn-Shyan Wang, Cheng-Tai Yeh, Jenn-Shyan Sheu:
  Design of a 2.5-GHz, 3-ps jitter, 8-locking-cycle, all-digital delay-locked loop with cycle-by-cycle phase adjustment. VLSIC 2012: 186-187
• 
  Yong-Sung Cho, Il-Han Park, Sangyong Yoon, Nam-Hee Lee, Sang-Hyun Joo, Ki-Whan Song, Kihwan Choi, Jin-Man Han, Kyehyun Kyung, Young-Hyun Jun:
  Adaptive multi-pulse program scheme based on tunneling speed classification for next generation multi-bit/cell NAND FLASH. VLSIC 2012: 136-137
• 
  Sang-Hye Chung, Lee-Sup Kim:
  1.22mW/Gb/s 9.6Gb/s data jitter mixing forwarded-clock receiver robust against power noise with 1.92ns latency mismatch between data and clock in 65nm CMOS. VLSIC 2012: 144-145
• 
  Amr Elshazly, Rajesh Inti, Mrunmay Talegaonkar, Pavan Kumar Hanumolu:
  A 1.5GHz 1.35mW -112dBc/Hz in-band noise digital phase-locked loop with 50fs/mV supply-noise sensitivity. VLSIC 2012: 188-189
• 
  Daniel Fainstein, Sami Rosenblatt, Alberto Cestero, Norman Robson, Toshiaki Kirihata, Subramanian S. Iyer:
  Dynamic intrinsic chip ID using 32nm high-K/metal gate SOI embedded DRAM. VLSIC 2012: 146-147
• 
  Mark A. Ferriss, Jean-Olivier Plouchart, Arun Natarajan, Alexander V. Rylyakov, Benjamin D. Parker, Aydin Babakhani, Soner Yaldiz, Bodhisatwa Sadhu, Alberto Valdes-Garcia, José A. Tierno, Daniel J. Friedman:
  An integral path self-calibration scheme for a 20.1-26.7GHz dual-loop PLL in 32nm SOI CMOS. VLSIC 2012: 176-177
• 
  Michael S. Floyd, Alan J. Drake, Robert W. Berry, Harold Chase, Richard L. Willaman, Jarom Peña:
  Voltage droop reduction using throttling controlled by timing margin feedback. VLSIC 2012: 96-97
• 
  Hiroki Fujii, Kousuke Miyaji, Koh Johguchi, Kazuhide Higuchi, Chao Sun, Ken Takeuchi:
  x11 performance increase, x6.9 endurance enhancement, 93% energy reduction of 3D TSV-integrated hybrid ReRAM/MLC NAND SSDs by data fragmentation suppression. VLSIC 2012: 134-135
• 
  Manideep Gande, Nima Maghari, Taehwan Oh, Un-Ku Moon:
  A 71dB dynamic range third-order ΔΣ TDC using charge-pump. VLSIC 2012: 168-169
• 
  Benjamin P. Hershberg, Skyler Weaver, Kazuki Sobue, Seiji Takeuchi, Koichi Hamashita, Un-Ku Moon:
  A 61.5dB SNDR pipelined ADC using simple highly-scalable ring amplifiers. VLSIC 2012: 32-33
• 
  Sung-Wan Hong, Tae-Hwang Kong, Seungchul Jung, Sungwoo Lee, Se-Won Wang, Jong-Pil Im, Gyu-Hyeong Cho:
  High area-efficient DC-DC converter using Time-Mode Miller Compensation (TMMC). VLSIC 2012: 180-181
• 
  Keng-Jan Hsiao:
  A 32.4 ppm/°C 3.2-1.6V self-chopped relaxation oscillator with adaptive supply generation. VLSIC 2012: 14-15
• 
  Steven Hsu, Amit Agarwal, Mark A. Anders, Himanshu Kaul, Sanu Mathew, Farhana Sheikh, Ram Krishnamurthy, Shekhar Borkar:
  A 2.8GHz 128-entry × 152b 3-read/2-write multi-precision floating-point register file and shuffler in 32nm CMOS. VLSIC 2012: 118-119
• 
  Shu-Yu Hsu, Yingchieh Ho, Yuhwai Tseng, Ting-You Lin, Po-Yao Chang, Jen-Wei Lee, Ju-Hung Hsiao, Siou-Ming Chuang, Tze-Zheng Yang, Po-Chun Liu, Ten-Fang Yang, Ray-Jade Chen, Chauchin Su, Chen-Yi Lee:
  A sub-100µW multi-functional cardiac signal processor for mobile healthcare applications. VLSIC 2012: 156-157
• 
  Peter Kuoyuan Hsu, Yukit Tang, Derek Tao, Ming-Chieh Huang, Min-Jer Wang, C. H. Wu, Quincy Lee:
  A SRAM cell array with adaptive leakage reduction scheme for data retention in 28nm high-k metal-gate CMOS. VLSIC 2012: 62-63
• 
  Yingzhe Hu, Warren Rieutort-Louis, Josue Sanz-Robinson, Katherine W. Song, James C. Sturm, Sigurd Wagner, Naveen Verma:
  High-resolution sensing sheet for structural-health monitoring via scalable interfacing of flexible electronics with high-performance ICs. VLSIC 2012: 120-121
• 
  Che-Wei Huang, Yu-Jie Huang, Pei-Wen Yen, Hsiao-Ting Hsueh, Chia-Yi Lin, Min-Cheng Chen, Chia-Hua Ho, Fu-Liang Yang, Hann-Huei Tsai, Hsin-Hao Liao, Ying-Zong Juang, Chorng-Kuang Wang, Chih-Ting Lin, Shey-Shi Lu:
  A fully integrated hepatitis B virus DNA detection SoC based on monolithic polysilicon nanowire CMOS process. VLSIC 2012: 124-125
• 
  Liechao Huang, Warren Rieutort-Louis, Yingzhe Hu, Josue Sanz-Robinson, Sigurd Wagner, James C. Sturm, Naveen Verma:
  Integrated all-silicon thin-film power electronics on flexible sheets for ubiquitous wireless charging stations based on solar-energy harvesting. VLSIC 2012: 198-199
• 
  Nick Ilyadis:
  The evolution of next-generation data center networks for high capacity computing. VLSIC 2012: 1-5

skipping 71 more matches