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Marcel A. Kossel
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2020 – today
- 2024
- [j25]Donggeon Kim, Yujin Choi, Jaewon Lee, Seoyoung Jang, Sungyu Song, Matthias Braendli, Thomas Morf, Marcel A. Kossel, Pier Andrea Francese, Gain Kim:
A Loop-Break Decision Feedback Equalizer for DAC/ADC-DSP-Based Wireline Transceivers. IEEE Trans. Circuits Syst. I Regul. Pap. 71(11): 5115-5128 (2024) - [j24]Jaewon Lee
, Seoyoung Jang, Yujin Choi, Donggeon Kim, Serdar A. Yonar, Matthias Braendli
A DAC/ADC-Based Wireline Transceiver Datapath Functional Verification on RFSoC Platform. IEEE Trans. Circuits Syst. II Express Briefs 71(7): 3318-3322 (2024) - [j23]Jaewon Lee, Seoyoung Jang
A 2-Lane Discrete Multitone Wireline Receiver Datapath With Far-End Crosstalk Cancellation on RFSoC Platform. IEEE Trans. Circuits Syst. II Express Briefs 71(11): 4738-4742 (2024) - [c49]Timothy O. Dickson, Zeynep Toprak Deniz, Martin Cochet, John F. Bulzacchelli, Marcel A. Kossel, Pier Andrea Francese, Thomas Morf, Jonathan E. Proesel, Herschel A. Ainspan, Matthias Brändli, Mounir Meghelli:
Digital-to-Analog Converters for 100+ Gb/s Wireline Transmitters: Architectures, Circuits, and Calibration. CICC 2024: 1-8 - [c48]Jaewon Lee, Seoyoung Jang, Yujin Choi, Donggeon Kim, Matthias Braendli, Marcel A. Kossel, Andrea Ruffino, Thomas Morf, Pier Andrea Francese, Gain Kim:
A 4×4 MIMO Discrete Multitone Wireline Transceiver With Far-End Crosstalk Cancellation For ADC-Based High-Speed Serial Links. ISCAS 2024: 1-5 - 2023
- [j22]Timothy O. Dickson
A 72-GS/s, 8-Bit DAC-Based Wireline Transmitter in 4-nm FinFET CMOS for 200+ Gb/s Serial Links. IEEE J. Solid State Circuits 58(4): 1074-1086 (2023) - [j21]Sandro Widmer, Marcel A. Kossel
Design of Time-Encoded Spiking Neural Networks in 7-nm CMOS Technology. IEEE Trans. Circuits Syst. II Express Briefs 70(9): 3639-3643 (2023) - [c47]Serdar A. Yonar, Pier Andrea Francese
An 8b 1.0-to-1.25GS/s 0.7-to-0.8V Single-Stage Time-Based Gated-Ring-Oscillator ADC with $2\times$ Interpolating Sense-Amplifier-Latches. ISSCC 2023: 266-267 - 2022
- [c46]Mridula Prathapan, Peter Mueller
A cryogenic SRAM based arbitrary waveform generator in 14 nm for spin qubit control. ESSCIRC 2022: 57-60 - [c45]Timothy O. Dickson, Zeynep Toprak Deniz, Martin Cochet, Marcel A. Kossel, Thomas Morf, Young-Ho Choi, Pier Andrea Francese
A 72GS/s, 8-bit DAC-based Wireline Transmitter in 4nm FinFET CMOS for 200+Gb/s Serial Links. VLSI Technology and Circuits 2022: 28-29 - [c44]Serdar S. Yonar, Pier Andrea Francese
An 8-bit 56GS/s 64x Time-Interleaved ADC with Bootstrapped Sampler and Class-AB Buffer in 4nm CMOS. VLSI Technology and Circuits 2022: 168-169 - [i1]Mridula Prathapan, Peter Mueller, David Heim, Maria Vittoria Oropallo, Matthias Braendli
A system design approach toward integrated cryogenic quantum control systems. CoRR abs/2211.02081 (2022) - 2021
- [c43]Asma Chabane, Mridula Prathapan, Peter Mueller
Cryogenic Characterization and Modeling of 14 nm Bulk FinFET Technology. ESSCIRC 2021: 67-70 - [c42]Asma Chabane, Mridula Prathapan, Peter Mueller, Eunjung Cha, Pier Andrea Francese
Cryogenic Characterization and Modeling of 14 nm Bulk FinFET Technology. ESSDERC 2021: 67-70 - [c41]Marcel A. Kossel, Vishal Khatri, Matthias Braendli
An 8b DAC-Based SST TX Using Metal Gate Resistors with 1.4pJ/b Efficiency at 112Gb/s PAM-4 and 8-Tap FFE in 7iim CMOS. ISSCC 2021: 130-132 - 2020
- [j20]Gain Kim, Marcel A. Kossel, Alessandro Cevrero, Ilter Özkaya, Andreas Burg
A 161-mW 56-Gb/s ADC-Based Discrete Multitone Wireline Receiver Data-Path in 14-nm FinFET. IEEE J. Solid State Circuits 55(1): 38-48 (2020) - [c40]Yang You, Glen A. Wiedemeier, Chad Marquart, Chris Steffen, Erik English, Dereje Yilma, Thomas Pham, Venkat Nammi, Jeffrey Okyere, Nathan Blanchard, Akil Sutton, Ze Zhang, David Friend, Diego Barba, Tyler Bohlke, Michael Spear, Vikram Raj, James Crugnale, Daniel Dreps, Pier Andrea Francese
A 25×50Gb/s 2.22pJ/b NRZ RX with Dual-Bank and 3-Tap Speculative DFE for Microprocessor Application in 7nm FinFET CMOS. VLSI Circuits 2020: 1-2
2010 – 2019
- 2019
- [c39]Gain Kim, Lukas Kull, Danny Luu, Matthias Braendli
A 4.8pJ/b 56Gb/s ADC-Based PAM-4 Wireline Receiver Data-Path with Cyclic Prefix in 14nm FinFET. A-SSCC 2019: 239-240 - [c38]Alessandro Cevrero, Ilter Özkaya, Pier Andrea Francese
A 100Gb/s 1.1pJ/b PAM-4 RX with Dual-Mode 1-Tap PAM-4 / 3-Tap NRZ Speculative DFE in 14nm CMOS FinFET. ISSCC 2019: 112-114 - [c37]Gain Kim, Lukas Kull, Danny Luu, Matthias Braendli
A 161mW 56Gb/s ADC-Based Discrete Multitone Wireline Receiver Data-Path in 14nm FinFET. ISSCC 2019: 476-478 - 2018
- [j19]Cosimo Aprile, Alessandro Cevrero, Pier Andrea Francese
An Eight-Lane 7-Gb/s/pin Source Synchronous Single-Ended RX With Equalization and Far-End Crosstalk Cancellation for Backplane Channels. IEEE J. Solid State Circuits 53(3): 861-872 (2018) - [j18]Ilter Özkaya, Alessandro Cevrero, Pier Andrea Francese
A 60-Gb/s 1.9-pJ/bit NRZ Optical Receiver With Low-Latency Digital CDR in 14-nm CMOS FinFET. IEEE J. Solid State Circuits 53(4): 1227-1237 (2018) - [j17]Danny Luu, Lukas Kull, Thomas Toifl, Christian Menolfi, Matthias Braendli
A 12-bit 300-MS/s SAR ADC With Inverter-Based Preamplifier and Common-Mode-Regulation DAC in 14-nm CMOS FinFET. IEEE J. Solid State Circuits 53(11): 3268-3279 (2018) - [j16]Lukas Kull, Danny Luu, Christian Menolfi, Matthias Brändli
A 24-72-GS/s 8-b Time-Interleaved SAR ADC With 2.0-3.3-pJ/Conversion and >30 dB SNDR at Nyquist in 14-nm CMOS FinFET. IEEE J. Solid State Circuits 53(12): 3508-3516 (2018) - [j15]Hazar Yueksel, Matthias Braendli
Design Techniques for High-Speed Multi-Level Viterbi Detectors and Trellis-Coded-Modulation Decoders. IEEE Trans. Circuits Syst. I Regul. Pap. 65-I(10): 3529-3542 (2018) - [c36]Gain Kim, Lukas Kull, Danny Luu, Matthias Braendli
Parallel Implementation Technique of Digital Equalizer for Ultra-High-Speed Wireline Receiver. ISCAS 2018: 1-5 - [c35]Christian Menolfi, Matthias Braendli
A 112Gb/S 2.6pJ/b 8-Tap FFE PAM-4 SST TX in 14nm CMOS. ISSCC 2018: 104-106 - [c34]Ilter Özkaya, Alessandro Cevrero, Pier Andrea Francese
A 56Gb/s burst-mode NRZ optical receiver with 6.8ns power-on and CDR-Lock time for adaptive optical links in 14nm FinFET CMOS. ISSCC 2018: 266-268 - [c33]Lukas Kull, Danny Luu, Christian Menolfi, Matthias Braendli
A 24-to-72GS/s 8b time-interleaved SAR ADC with 2.0-to-3.3pJ/conversion and >30dB SNDR at nyquist in 14nm CMOS FinFET. ISSCC 2018: 358-360 - [c32]Thomas Toifl, Christian Menolfi, Matthias Brändli
A 0.3PJ/Bit 112GB/S PAM4 1+0.5D TX-DFE Precoder and 8-Tap FFE in 14NM CMOS. VLSI Circuits 2018: 53-54 - [c31]Pier Andrea Francese
A 50GB/S 1.6PJ/B RX Data-Path with Quarter-Rate 3-Tap Speculative DFE. VLSI Circuits 2018: 267-268 - [c30]Lukas Kull, Danny Luu, Christian Menolfi, Thomas Morf, Pier Andrea Francese
A 10-Bit 20-40 GS/S ADC with 37 dB SNDR at 40 GHz Input Using First Order Sampling Bandwidth Calibration. VLSI Circuits 2018: 275-276 - 2017
- [j14]Ilter Özkaya
A 64-Gb/s 1.4-pJ/b NRZ Optical Receiver Data-Path in 14-nm CMOS FinFET. IEEE J. Solid State Circuits 52(12): 3458-3473 (2017) - [c29]Marcel A. Kossel, Christian Menolfi, Pier Andrea Francese
DDR4 transmitter with AC-boost equalization and wide-band voltage regulators for thin-oxide protection in 14-nm SOI CMOS technology. ESSCIRC 2017: 115-118 - [c28]Danny Luu, Lukas Kull, Thomas Toifl, Christian Menolfi, Matthias Braendli
Background calibration using noisy reference ADC for a 12 b 600 MS/s 2 × TI SAR ADC in 14nm CMOS FinFET. ESSCIRC 2017: 183-186 - [c27]Lukas Kull, Danny Luu, Christian Menolfi, Matthias Braendli
28.5 A 10b 1.5GS/s pipelined-SAR ADC with background second-stage common-mode regulation and offset calibration in 14nm CMOS FinFET. ISSCC 2017: 474-475 - [c26]Alessandro Cevrero, Ilter Özkaya, Pier Andrea Francese
29.1 A 64Gb/s 1.4pJ/b NRZ optical-receiver data-path in 14nm CMOS FinFET. ISSCC 2017: 482-483 - 2016
- [j13]Lukas Kull, Jan Plíva, Thomas Toifl, Martin L. Schmatz, Pier Andrea Francese
Implementation of Low-Power 6-8 b 30-90 GS/s Time-Interleaved ADCs With Optimized Input Bandwidth in 32 nm CMOS. IEEE J. Solid State Circuits 51(3): 636-648 (2016) - [c25]Hazar Yueksel, Matthias Braendli
A 4.1 pJ/b 25.6 Gb/s 4-PAM reduced-state sliding-block Viterbi detector in 14 nm CMOS. ESSCIRC 2016: 309-312 - [c24]Thomas Toifl, Matthias Braendli
Design considerations for 50G+ backplane links. ESSCIRC 2016: 477-482 - [c23]Pier Andrea Francese
23.6 A 30Gb/s 0.8pJ/b 14nm FinFET receiver data-path. ISSCC 2016: 408-409 - 2015
- [c22]Hazar Yueksel, Lukas Kull, Andreas Burg
A 3.6pJ/b 56Gb/s 4-PAM receiver with 6-Bit TI-SAR ADC and quarter-rate speculative 2-tap DFE in 32 nm CMOS. ESSCIRC 2015: 148-151 - [c21]Toke Meyer Andersen, Florian Krismer, Johann Walter Kolar, Thomas Toifl, Christian Menolfi, Lukas Kull, Thomas Morf, Marcel A. Kossel, Matthias Braendli, Pier Andrea Francese
20.3 A feedforward controlled on-chip switched-capacitor voltage regulator delivering 10W in 32nm SOI CMOS. ISSCC 2015: 1-3 - [c20]Pier Andrea Francese
10.6 continuous-time linear equalization with programmable active-peaking transistor arrays in a 14nm FinFET 2mW/Gb/s 16Gb/s 2-Tap speculative DFE receiver. ISSCC 2015: 1-3 - [c19]Alessandro Cevrero, Cosimo Aprile, Pier Andrea Francese
A 5.9mW/Gb/s 7Gb/s/pin 8-lane single-ended RX with crosstalk cancellation scheme using a XCTLE and 56-tap XDFE in 32nm SOI CMOS. VLSIC 2015: 228- - 2014
- [j12]Pier Andrea Francese
A 16 Gb/s 3.7 mW/Gb/s 8-Tap DFE Receiver and Baud-Rate CDR With 31 kppm Tracking Bandwidth. IEEE J. Solid State Circuits 49(11): 2490-2502 (2014) - [c18]Lukas Kull, Jan Plíva, Thomas Toifl, Martin L. Schmatz, Pier Andrea Francese
A 110 mW 6 bit 36 GS/s interleaved SAR ADC for 100 GBE occupying 0.048 mm2 in 32 nm SOI CMOS. A-SSCC 2014: 89-92 - [c17]Marcel A. Kossel, Christian Menolfi, Thomas Toifl, Pier Andrea Francese
A DDR3/4 memory link TX supporting 24-40 Ω, 0.8-1.6 V, 0.8-5.0 Gb/s with slew rate control and thin oxide output stages in 22-nm CMOS SOI. ESSCIRC 2014: 135-138 - [c16]Pier Andrea Francese
A 16 Gb/s receiver with DC wander compensated rail-to-rail AC coupling and passive linear-equalizer in 22 nm CMOS. ESSCIRC 2014: 435-438 - [c15]Thomas Toifl, Peter Buchmann, Troy J. Beukema, Michael P. Beakes, Matthias Braendli
A 3.5pJ/bit 8-tap-feed-forward 8-tap-decision feedback digital equalizer for 16Gb/s I/Os. ESSCIRC 2014: 455-458 - [c14]Toke Meyer Andersen, Florian Krismer, Johann W. Kolar, Thomas Toifl, Christian Menolfi, Lukas Kull, Thomas Morf, Marcel A. Kossel, Matthias Braendli
4.7 A sub-ns response on-chip switched-capacitor DC-DC voltage regulator delivering 3.7W/mm2 at 90% efficiency using deep-trench capacitors in 32nm SOI CMOS. ISSCC 2014: 90-91 - [c13]Lukas Kull, Thomas Toifl, Martin L. Schmatz, Pier Andrea Francese
22.1 A 90GS/s 8b 667mW 64× interleaved SAR ADC in 32nm digital SOI CMOS. ISSCC 2014: 378-379 - 2013
- [j11]Lukas Kull, Thomas Toifl, Martin L. Schmatz, Pier Andrea Francese
A 3.1 mW 8b 1.2 GS/s Single-Channel Asynchronous SAR ADC With Alternate Comparators for Enhanced Speed in 32 nm Digital SOI CMOS. IEEE J. Solid State Circuits 48(12): 3049-3058 (2013) - [j10]Marcel A. Kossel, Thomas Toifl, Pier Andrea Francese
A 10 Gb/s 8-Tap 6b 2-PAM/4-PAM Tomlinson-Harashima Precoding Transmitter for Future Memory-Link Applications in 22-nm SOI CMOS. IEEE J. Solid State Circuits 48(12): 3268-3284 (2013) - [c12]Marcel A. Kossel, Christian Menolfi, Thomas Toifl, Pier Andrea Francese
A 5.7mW/Gb/s 24-to-240Ω 1.6Gb/s thin-oxide DDR transmitter with 1.9-to-7.6V/ns clock-feathering slew-rate control in 22nm CMOS. ISSCC 2013: 310-311 - [c11]Marcel A. Kossel, Thomas Toifl, Pier Andrea Francese
An 8Gb/s 1.5mW/Gb/s 8-tap 6b NRZ/PAM-4 Tomlinson-Harashima precoding transmitter for future memory-link applications in 22nm CMOS. ISSCC 2013: 408-409 - [c10]Lukas Kull, Thomas Toifl, Martin L. Schmatz, Pier Andrea Francese
A 3.1mW 8b 1.2GS/s single-channel asynchronous SAR ADC with alternate comparators for enhanced speed in 32nm digital SOI CMOS. ISSCC 2013: 468-469 - 2012
- [j9]Thomas Toifl, Christian Menolfi, Michael Ruegg, Robert Reutemann, Daniel Dreps, Troy J. Beukema, Andrea Prati, Daniele Gardellini, Marcel A. Kossel, Peter Buchmann, Matthias Braendli
A 2.6 mW/Gbps 12.5 Gbps RX With 8-Tap Switched-Capacitor DFE in 32 nm CMOS. IEEE J. Solid State Circuits 47(4): 897-910 (2012) - [j8]John F. Bulzacchelli, Christian Menolfi, Troy J. Beukema, Daniel W. Storaska, Juergen Hertle, David Hanson, Ping-Hsuan Hsieh
A 28-Gb/s 4-Tap FFE/15-Tap DFE Serial Link Transceiver in 32-nm SOI CMOS Technology. IEEE J. Solid State Circuits 47(12): 3232-3248 (2012) - [c9]Christian Menolfi, Juergen Hertle, Thomas Toifl, Thomas Morf, Daniele Gardellini, Matthias Braendli
A 28Gb/s source-series terminated TX in 32nm CMOS SOI. ISSCC 2012: 334-336 - [c8]Thomas Toifl, Michael Ruegg, Rajesh Inti, Christian Menolfi, Matthias Braendli
A 3.1mW/Gbps 30Gbps quarter-rate triple-speculation 15-tap SC-DFE RX data path in 32nm CMOS. VLSIC 2012: 102-103 - 2011
- [c7]Rajesh Inti, Amr Elshazly, Brian Young, Wenjing Yin, Marcel A. Kossel, Thomas Toifl, Pavan Kumar Hanumolu:
A highly digital 0.5-to-4Gb/s 1.9mW/Gb/s serial-link transceiver using current-recycling in 90nm CMOS. ISSCC 2011: 152-154 - [c6]Christian Menolfi, Thomas Toifl, Michael Ruegg, Matthias Braendli
A 14Gb/s high-swing thin-oxide device SST TX in 45nm CMOS SOI. ISSCC 2011: 156-158
2000 – 2009
- 2009
- [j7]Marcel A. Kossel, Thomas Morf, Jonas R. M. Weiss, Peter Buchmann, Christian Menolfi, Thomas Toifl, Martin L. Schmatz:
LC PLL With 1.2-Octave Locking Range Based on Mutual-Inductance Switching in 45-nm SOI CMOS. IEEE J. Solid State Circuits 44(2): 436-449 (2009) - [j6]Thomas Toifl, Christian Menolfi, Peter Buchmann, Marcel A. Kossel, Thomas Morf, Martin L. Schmatz:
A 1.25-5 GHz Clock Generator With High-Bandwidth Supply-Rejection Using a Regulated-Replica Regulator in 45-nm CMOS. IEEE J. Solid State Circuits 44(11): 2901-2910 (2009) - [c5]George von Büren, David Barras, Heinz Jäckel, Alex Huber, Christian Kromer, Marcel A. Kossel:
Design and phase noise analysis of a multiphase 6 to 11 GHz PLL. ESSCIRC 2009: 384-387 - 2008
- [j5]Marcel A. Kossel, Christian Menolfi, Jonas R. M. Weiss, Peter Buchmann, George von Büren, Lucio Rodoni, Thomas Morf, Thomas Toifl, Martin L. Schmatz:
A T-Coil-Enhanced 8.5 Gb/s High-Swing SST Transmitter in 65 nm Bulk CMOS With ≪ -16 dB Return Loss Over 10 GHz Bandwidth. IEEE J. Solid State Circuits 43(12): 2905-2920 (2008) - [c4]Marcel A. Kossel, Christian Menolfi, Jonas R. M. Weiss, Peter Buchmann, George von Büren, Lucio Rodoni, Thomas Morf, Thomas Toifl, Martin L. Schmatz:
A T-Coil-Enhanced 8.5Gb/s High-Swing source-Series-Terminated Transmitter in 65nm Bulk CMOS. ISSCC 2008: 110-111 - 2007
- [c3]Thomas Toifl, Christian Menolfi, Peter Buchmann, Christoph Hagleitner, Marcel A. Kossel, Thomas Morf, Jonas R. M. Weiss, Martin L. Schmatz:
A 72mW 0.03mm2 Inductorless 40Gb/s CDR in 65nm SOI CMOS. ISSCC 2007: 226-598 - [c2]Christian Menolfi, Thomas Toifl, Peter Buchmann, Marcel A. Kossel, Thomas Morf, Jonas R. M. Weiss, Martin L. Schmatz:
A 16Gb/s Source-Series Terminated Transmitter in 65nm CMOS SOI. ISSCC 2007: 446-614 - 2006
- [j4]Thomas Toifl, Christian Menolfi, Michael Ruegg, Robert Reutemann, Peter Buchmann, Marcel A. Kossel, Thomas Morf, Jonas R. M. Weiss, Martin L. Schmatz:
A 22-gb/s PAM-4 receiver in 90-nm CMOS SOI technology. IEEE J. Solid State Circuits 41(4): 954-965 (2006) - [c1]Jonas R. M. Weiss, Marcel A. Kossel, Christian Menolfi, Thomas Morf, Martin L. Schmatz, Thomas Toifl, Heinz Jäckel:
A DC-to-44-GHz 19dB Gain Amplifier in 90nm CMOS Using Capacitive Bandwidth Enhancement. ISSCC 2006: 2082-2091 - 2005
- [j3]Thomas Toifl, Christian Menolfi, Peter Buchmann, Marcel A. Kossel, Thomas Morf, Robert Reutemann, Michael Ruegg, Martin L. Schmatz, Jonas R. M. Weiss:
A 0.94-ps-RMS-jitter 0.016-mm2 2.5-GHz multiphase generator PLL with 360° digitally programmable phase shift for 10-Gb/s serial links. IEEE J. Solid State Circuits 40(12): 2700-2712 (2005) - 2004
- [j2]Marcel A. Kossel, Martin L. Schmatz:
Jitter Measurements of High-Speed Serial Links. IEEE Des. Test Comput. 21(6): 536-543 (2004) - [j1]Marcel A. Kossel, Pascal Leuchtmann, Jürg Rüfenacht:
Traceable correction method for complex reflection coefficient using calculable air line impedance standards. IEEE Trans. Instrum. Meas. 53(2): 398-405 (2004)
Coauthor Index
Matthias Braendli
aka: Matthias Brändli
aka: Matthias Brändli
[j25] [j24] [j23] [c49] [c48] [j22] [j21] [c47] [c46] [c45] [c44] [i1] [c41] [j20] [c39] [c38] [c37] [j19] [j18] [j17] [j16] [j15] [c36] [c35] [c34] [c33] [c32] [c31] [c30] [j14] [c29] [c28] [c27] [c26] [j13] [c25] [c24] [c23] [c22] [c21] [c20] [c19] [j12] [c18] [c17] [c16] [c15] [c14] [c13] [j11] [j10] [c12] [c11] [c10] [j9] [j8] [c9] [c8] [c6]
[j25] [j24] [j23] [c49] [c48] [j22] [j21] [c47] [c46] [c45] [c44] [i1] [c43] [c42] [c41] [j20] [c40] [c39] [c38] [c37] [j19] [j18] [j17] [j16] [j15] [c36] [c35] [c34] [c33] [c32] [c31] [c30] [j14] [c29] [c28] [c27] [c26] [j13] [c25] [c24] [c23] [c22] [c21] [c20] [c19] [j12] [c18] [c17] [c16] [c15] [c14] [c13] [j11] [j10] [c12] [c11] [c10] [j9] [c8]
[c46] [j20] [c39] [c38] [c37] [j19] [j18] [j17] [j16] [j15] [c36] [c35] [c34] [c33] [c32] [c31] [c30] [j14] [c29] [c28] [c27] [c26] [j13] [c25] [c24] [c23] [c22] [c21] [c20] [c19] [j12] [c18] [c17] [c16] [c15] [c14] [c13] [j11] [j10] [c12] [c11] [c10] [j9] [j8] [c9] [c8] [c6] [j7] [j6] [j5] [c4] [c3] [c2] [j4] [c1] [j3]
[j25] [j24] [j23] [c49] [c48] [j22] [c47] [c46] [c45] [c44] [i1] [c43] [c42] [c41] [j20] [c40] [c39] [c38] [c37] [j19] [j18] [j17] [j16] [j15] [c36] [c35] [c34] [c33] [c32] [c31] [c30] [j14] [c29] [c28] [c27] [c26] [j13] [c25] [c24] [c23] [c22] [c21] [c20] [c19] [j12] [c18] [c17] [c16] [c15] [c14] [c13] [j11] [j10] [c12] [c11] [c10] [j9] [j8] [c9] [c8] [c6] [j7] [j6] [j5] [c4] [c3] [c2] [j4] [c1] [j3]
Ilter Özkaya
aka: Ilter Oezkaya
aka: Ilter Oezkaya
[j20] [c39] [c38] [c37] [j19] [j18] [j17] [j16] [j15] [c36] [c35] [c34] [c33] [c32] [c31] [c30] [j14] [c29] [c28] [c27] [c26] [j13] [c25] [c24] [c23] [c22] [c21] [c20] [c19] [j12] [c18] [c17] [c16] [c15] [c14] [c13] [j11] [j10] [c12] [c11] [c10] [j9] [j8] [c9] [c8] [c7] [c6] [j7] [j6] [j5] [c4] [c3] [c2] [j4] [c1] [j3]
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