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Jean-Olivier Plouchart
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2020 – today
- 2024
- [j17]Wooram Lee
, Caglar Ozdag
A 24 to 30-GHz Phased Array Transceiver Front End With 2.8 to 3.1-dB RX NF and 22 to 24% TX Peak Efficiency. IEEE J. Solid State Circuits 59(9): 2788-2804 (2024) - 2023
- [c29]Rajiv V. Joshi, Jean-Olivier Plouchart, George Zettles, Scott Willenborg, Sudipto Chakraborty, Blake R. Johnson, Andrew Wack, Brian Allison, John Timmerwilke, Kevin Tien, Mark Yeck, Dereje Yilma, Alberto Valdes-Garcia, Daniel J. Friedman:
Cryogenic CMOS: design considerations for future quantum computing systems. CICC 2023: 1-8 - 2022
- [j16]Bodhisatwa Sadhu
A 24-30-GHz 256-Element Dual-Polarized 5G Phased Array Using Fast On-Chip Beam Calculators and Magnetoelectric Dipole Antennas. IEEE J. Solid State Circuits 57(12): 3599-3616 (2022) - [c28]Bodhisatwa Sadhu, Arun Paidimarri
A 24-to-30GHz 256-Element Dual-Polarized 5G Phased Array with Fast Beam-Switching Support for >30, 000 Beams. ISSCC 2022: 436-438 - 2020
- [j15]Bodhisatwa Sadhu
A 250-mW 60-GHz CMOS Transceiver SoC Integrated With a Four-Element AiP Providing Broad Angular Link Coverage. IEEE J. Solid State Circuits 55(6): 1516-1529 (2020)
2010 – 2019
- 2018
- [j14]Wooram Lee
Fully Integrated 94-GHz Dual-Polarized TX and RX Phased Array Chipset in SiGe BiCMOS Operating up to 105 °C. IEEE J. Solid State Circuits 53(9): 2512-2531 (2018) - [c27]Alberto Valdes-Garcia, Bodhisatwa Sadhu, Xiaoxiong Gu, Jean-Olivier Plouchart, Mark Yeck, Daniel J. Friedman:
Scaling Millimeter-Wave Phased Arrays: Challenges and Solutions. BCICTS 2018: 80-84 - 2017
- [c26]Jen-Chieh Hsueh, Vanessa H.-C. Chen, Jean-Olivier Plouchart:
An ultra-high bandwidth sub-ranging ADC with programmable dynamic range in 32nm CMOS SOI. MWSCAS 2017: 448-451 - 2015
- [c25]Fa Wang, Manzil Zaheer, Xin Li, Jean-Olivier Plouchart, Alberto Valdes-Garcia:
Co-Learning Bayesian Model Fusion: Efficient Performance Modeling of Analog and Mixed-Signal Circuits Using Side Information. ICCAD 2015: 575-582 - 2014
- [j13]Jean-Olivier Plouchart, Fa Wang, Xin Li, Benjamin D. Parker, Mihai A. T. Sanduleanu
Adaptive Circuit Design Methodology and Test Applied to Millimeter-Wave Circuits. IEEE Des. Test 31(6): 8-18 (2014) - [j12]Shupeng Sun, Fa Wang, Soner Yaldiz, Xin Li, Lawrence T. Pileggi, Arun Natarajan, Mark A. Ferriss, Jean-Olivier Plouchart, Bodhisatwa Sadhu
Indirect Performance Sensing for On-Chip Self-Healing of Analog and RF Circuits. IEEE Trans. Circuits Syst. I Regul. Pap. 61-I(8): 2243-2252 (2014) - 2013
- [j11]Mark A. Ferriss, Jean-Olivier Plouchart, Arun Natarajan, Alexander V. Rylyakov, Benjamin D. Parker, José A. Tierno, Aydin Babakhani, Soner Yaldiz, Alberto Valdes-Garcia, Bodhisatwa Sadhu
An Integral Path Self-Calibration Scheme for a Dual-Loop PLL. IEEE J. Solid State Circuits 48(4): 996-1008 (2013) - [j10]Bodhisatwa Sadhu
A linearized, low-phase-noise VCO-based 25-GHz PLL with autonomic biasing. IEEE J. Solid State Circuits 48(5): 1138-1150 (2013) - [j9]Bodhisatwa Sadhu
Correction to "A Linearized, Low Phase Noise VCO Based 25 GHz PLL With Autonomic Biasing". IEEE J. Solid State Circuits 48(6): 1539 (2013) - [j8]Jean-Olivier Plouchart, Mark A. Ferriss, Arun Natarajan, Alberto Valdes-Garcia, Bodhisatwa Sadhu
A 23.5 GHz PLL With an Adaptively Biased VCO in 32 nm SOI-CMOS. IEEE Trans. Circuits Syst. I Regul. Pap. 60-I(8): 2009-2017 (2013) - [c24]Shupeng Sun, Fa Wang, Soner Yaldiz, Xin Li, Lawrence T. Pileggi, Arun Natarajan, Mark A. Ferriss, Jean-Olivier Plouchart, Bodhisatwa Sadhu
Indirect performance sensing for on-chip analog self-healing via Bayesian model fusion. CICC 2013: 1-4 - 2012
- [c23]Jean-Olivier Plouchart, Mark A. Ferriss, Arun Natarajan, Alberto Valdes-Garcia, Bodhisatwa Sadhu
A 23.5GHz PLL with an adaptively biased VCO in 32nm SOI-CMOS. CICC 2012: 1-4 - [c22]Jean-Olivier Plouchart, Mihai A. T. Sanduleanu
A 3.2GS/s 4.55b ENOB two-step subranging ADC in 45nm SOI CMOS. CICC 2012: 1-4 - [c21]Mark A. Ferriss, Jean-Olivier Plouchart, Arun Natarajan, Alexander V. Rylyakov, Benjamin D. Parker, Aydin Babakhani, Soner Yaldiz, Bodhisatwa Sadhu
An integral path self-calibration scheme for a 20.1-26.7GHz dual-loop PLL in 32nm SOI CMOS. VLSIC 2012: 176-177 - 2011
- [j7]Gokce Keskin, Jonathan E. Proesel, Jean-Olivier Plouchart, Lawrence T. Pileggi:
Exploiting Combinatorial Redundancy for Offset Calibration in Flash ADCs. IEEE J. Solid State Circuits 46(8): 1904-1918 (2011) - [c20]Mihai A. T. Sanduleanu
A 4GS/s, 8.45 ENOB and 5.7fJ/conversion, digital assisted, sampling system in 45nm CMOS SOI. CICC 2011: 1-4 - 2010
- [c19]Jonathan E. Proesel, Gokce Keskin, Jean-Olivier Plouchart, Lawrence T. Pileggi:
An 8-bit 1.5GS/s flash ADC using post-manufacturing statistical selection. CICC 2010: 1-4
2000 – 2009
- 2009
- [c18]Alexander V. Rylyakov, José A. Tierno, Herschel A. Ainspan, Jean-Olivier Plouchart, John F. Bulzacchelli, Zeynep Toprak Deniz, Daniel J. Friedman:
Bang-bang digital PLLs at 11 and 20GHz with sub-200fs integrated jitter for high-speed serial communication applications. ISSCC 2009: 94-95 - [c17]Daeik D. Kim, Jonghae Kim, Choongyeun Cho, Jean-Olivier Plouchart, Mahender Kumar, Woo-Hyeong Lee, Ken Rim:
An array of 4 complementary LC-VCOs with 51.4% W-Band coverage in 32nm SOI CMOS. ISSCC 2009: 278-279 - 2008
- [c16]Daeik D. Kim, Choongyeun Cho, Jonghae Kim, Jean-Olivier Plouchart:
Wideband mmWave CML static divider in 65nm SOI CMOS technology. CICC 2008: 627-634 - [c15]Alexander V. Rylyakov, José A. Tierno, Didem Zeliha Turker, Jean-Olivier Plouchart, Herschel A. Ainspan, Daniel J. Friedman:
A Modular All-Digital PLL Architecture Enabling Both 1-to-2GHz and 24-to-32GHz Operation in 65nm CMOS. ISSCC 2008: 516-517 - 2007
- [c14]Choongyeun Cho, Daeik D. Kim, Jonghae Kim, Jean-Olivier Plouchart, Robert Trzcinski:
Statistical Framework for Technology-Model-Product Co-Design and Convergence. DAC 2007: 503-508 - [c13]Choongyeun Cho, Daeik D. Kim, Jonghae Kim, Jean-Olivier Plouchart, Daihyun Lim, Sangyeun Cho, Robert Trzcinski:
A Data-Driven Statistical Approach to Analyzing Process Variation in 65nm SOI Technology. ISQED 2007: 699-702 - [c12]Daeik D. Kim, Jonghae Kim, Jean-Olivier Plouchart, Choongyeun Cho, Weipeng Li, Daihyun Lim, Robert Trzcinski, Mahender Kumar, Christine Norris, David Ahlgren:
A 70GHz Manufacturable Complementary LC-VCO with 6.14GHz Tuning Range in 65nm SOI CMOS. ISSCC 2007: 540-620 - [c11]Daihyun Lim, Jonghae Kim, Jean-Olivier Plouchart, Choongyeun Cho, Daeik D. Kim, Robert Trzcinski, Duane S. Boning:
Performance Variability of a 90GHz Static CML Frequency Divider in 65nm SOI CMOS. ISSCC 2007: 542-621 - 2006
- [c10]Daeik D. Kim, Choongyeun Cho, Jonghae Kim, Jean-Olivier Plouchart, Robert Trzcinski, David Ahlgren:
CMOS Mixed-Signal Circuit Process Variation Sensitivity Characterization for Yield Improvement. CICC 2006: 365-368 - [c9]Jean-Olivier Plouchart, Jonghae Kim, Victor Karam, Robert Trzcinski, Jeff Gross:
Performance Variations of a 66GHz Static CML Divider in 90nm CMOS. ISSCC 2006: 2142-2151 - 2004
- [j6]Neric H. W. Fong, Jonghae Kim, Jean-Olivier Plouchart, Noah Zamdmer, Duixian Liu, Lawrence F. Wagner, Calvin Plett, Garry Tarr:
A low-voltage 40-GHz complementary VCO with 15% frequency tuning range in SOI CMOS technology. IEEE J. Solid State Circuits 39(5): 841-846 (2004) - [j5]Jean-Olivier Plouchart, Jonghae Kim, Noah Zamdmer, Liang-Hung Lu, Melanie Sherony, Yue Tan, Robert A. Groves, Robert Trzcinski, Mohamed Talbi
A 4-91-GHz traveling-wave amplifier in a standard 0.12-μm SOI CMOS microprocessor technology. IEEE J. Solid State Circuits 39(9): 1455-1461 (2004) - [c8]Jonghae Kim, Jean-Olivier Plouchart, Noah Zamdmer:
Design and manufacturability aspect of SOI CMOS RFICs. CICC 2004: 541-548 - 2003
- [j4]Jean-Olivier Plouchart, Noah Zamdmer, Jonghae Kim, Melanie Sherony, Yue Tan, Asit Ray, Mohamed Talbi
Application of an SOI 0.12-µm CMOS technology to SoCs with low-power and high-frequency circuits. IBM J. Res. Dev. 47(5-6): 611-630 (2003) - [j3]Yu Cao, Robert A. Groves, Xuejue Huang, Noah Zamdmer, Jean-Olivier Plouchart, Richard A. Wachnik, Tsu-Jae King, Chenming Hu:
Frequency-independent equivalent-circuit model for on-chip spiral inductors. IEEE J. Solid State Circuits 38(3): 419-426 (2003) - [j2]Neric H. W. Fong, Jean-Olivier Plouchart, Noah Zamdmer, Duixian Liu, Lawrence F. Wagner, Calvin Plett, N. Garry Tarr:
Design of wide-band CMOS VCO for multiband wireless LAN applications. IEEE J. Solid State Circuits 38(8): 1333-1342 (2003) - [c7]Jean-Olivier Plouchart, Jonghae Kim, Noah Zamdmer, Liang-Hung Lu, Melanie Sherony, Yue Tan, Robert A. Groves, Robert Trzcinski, Mohamed Talbi, Asit Ray, Lawrence F. Wagner:
A 4-91 GHz distributed amplifier in a standard 0.12 μm SOI CMOS microprocessor technology. CICC 2003: 159-162 - [c6]Jean-Olivier Plouchart, Jonghae Kim, Noah Zamdmer, Melanie Sherony, Yue Tan, Meeyoung Yoon, Mohamed Talbi
A 31 GHz CML ring VCO with 5.4 ps delay in a 0.12-μm SOI CMOS technology. ESSCIRC 2003: 357-360 - [c5]Jonghae Kim, Jean-Olivier Plouchart, Noah Zamdmer, Melanie Sherony, Yue Tan, Meeyoung Yoon, Robert Trzcinski, Mohamed Talbi, John Safran, Asit Ray, Lawrence F. Wagner:
A power-optimized widely-tunable 5-GHz monolithic VCO in a digital SOI CMOS technology on high resistivity substrate. ISLPED 2003: 434-439 - [c4]Jean-Olivier Plouchart, Jonghae Kim, Hector Recoules, Noah Zamdmer, Yue Tan, Melanie Sherony, Asit Ray, Lawrence F. Wagner:
A 0.123 mW 7.25 GHz static frequency divider by 8 in a 120-nm SOI technology. ISLPED 2003: 440-442 - 2002
- [c3]Yu Cao, Robert A. Groves, Noah Zamdmer, Jean-Olivier Plouchart, Richard A. Wachnik, Xuejue Huang, Tsu-Jae King, Chenming Hu:
Frequency-independent equivalent circuit model for on-chip spiral inductors. CICC 2002: 217-220 - [c2]Neric H. W. Fong, Jean-Olivier Plouchart, Noah Zamdmer, Duixian Liu, Lawrence F. Wagner, Calvin Plett, Gerry Tarr:
A low-voltage multi-GHz VCO with 58% tuning range in SOI CMOS. CICC 2002: 423-426 - 2000
- [j1]Mehmet Soyuer, Herschel A. Ainspan, Mounir Meghelli, Jean-Olivier Plouchart:
Low-power multi-GHz and multi-Gb/s SiGe BiCMOS circuits. Proc. IEEE 88(10): 1572-1582 (2000)
1990 – 1999
- 1999
- [c1]Jean-Olivier Plouchart, Herschel A. Ainspan, Mehmet Soyuer:
A 5.2 GHz 3.3 V I/Q SiGe RF transceiver. CICC 1999: 217-220
Coauthor Index
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