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"A 47% access time reduction with a worst-case timing-generation scheme ..."

Atsushi Kawasumi et al. (2012)

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DOI: 10.1109/VLSIC.2012.6243809

access: closed

type: Conference or Workshop Paper

metadata version: 2017-05-21

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  - conf/vlsic/KawasumiTHKTNSY12
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Atsushi Kawasumi, Yasuhisa Takeyama, Osamu Hirabayashi, Keiichi Kushida, Fumihiko Tachibana, Yusuke Niki, Shinichi Sasaki, Tomoaki Yabe:
A 47% access time reduction with a worst-case timing-generation scheme utilizing a statistical method for ultra low voltage SRAMs. VLSIC 2012: 100-101

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