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Koichi Takeda 0001
Person information
- affiliation: Renesas Electronics, LSI Research Laboratory, Kawasaki, Japan
- affiliation (1993 - 2009): NEC Corporation, Kanagawa, Japan
Other persons with the same name
- Koichi Takeda — disambiguation page
- Koichi Takeda 0002 (aka: Kohichi Takeda) — IBM Research, Tokyo, Japan
- Koichi Takeda 0003 — Nagoya University, Graduate School of Informatics, Japan
- Koichi Takeda 0004 — University of Tohoku, Department of Electrical and Communication Engineering, Sendai, Japan
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2010 – 2019
- 2012
- [c3]Takashi Tokairin, Koichi Nose, Koichi Takeda, Koichiro Noguchi, Tadashi Maeda, Kazuyoshi Kawai, Masayuki Mizuno:
A 280nW, 100kHz, 1-cycle start-up time, on-chip CMOS relaxation oscillator employing a feedforward period control scheme. VLSIC 2012: 16-17 - 2011
- [j8]Koichi Takeda, Toshio Saito, Shinobu Asayama, Yoshiharu Aimoto, Hiroyuki Kobatake, Shinya Ito, Toshifumi Takahashi, Masahiro Nomura, Kiyoshi Takeuchi, Yoshihiro Hayashi
:
Multi-Step Word-Line Control Technology in Hierarchical Cell Architecture for Scaled-Down High-Density SRAMs. IEEE J. Solid State Circuits 46(4): 806-814 (2011)
2000 – 2009
- 2006
- [j7]Masahiro Nomura, Taku Ohsawa, Koichi Takeda, Yoetsu Nakazawa, Yoshinori Hirota, Yasuhiko Hagihara, Naoki Nishi:
An Automatic Bi-Directional Bus Repeater Control Scheme Using Dynamic Collaborative Driving Techniques. IEICE Trans. Electron. 89-C(3): 334-341 (2006) - [j6]Koichi Takeda, Yasuhiko Hagihara, Yoshiharu Aimoto, Masahiro Nomura, Yoetsu Nakazawa, Toshio Ishii, Hiroyuki Kobatake:
A read-static-noise-margin-free SRAM cell for low-VDD and high-speed applications. IEEE J. Solid State Circuits 41(1): 113-121 (2006) - [j5]Masahiro Nomura, Yoshifumi Ikenaga, Koichi Takeda, Yoetsu Nakazawa, Yoshiharu Aimoto, Yasuhiko Hagihara:
Delay and power monitoring schemes for minimizing power consumption by means of supply and threshold voltage control in active and standby modes. IEEE J. Solid State Circuits 41(4): 805-814 (2006) - [c2]Koichi Takeda, Hidetoshi Ikeda, Yasuhiko Hagihara, Masahiro Nomura, Hiroyuki Kobatake:
Redefinition of Write Margin for Next-Generation SRAM and Write-Margin Monitoring Circuit. ISSCC 2006: 2602-2611 - 2001
- [j4]Kenji Noda, Koichi Takeda, Koujirou Matsui, Shinya Ito, Sadaaki Masuoka, Hideaki Kawamoto, Nobuyuki Ikezawa, Yoshiharu Aimoto, Noritsugu Nakamura, Takahiro Iwasaki, Hideo Toyoshima, Tadahiko Horiuchi:
An ultrahigh-density high-speed loadless four-transistor SRAM macro with twisted bitline architecture and triple-well shield. IEEE J. Solid State Circuits 36(3): 510-515 (2001) - 2000
- [j3]Koichi Takeda, Yoshiharu Aimoto, Noritsugu Nakamura, Hideo Toyoshima, Takahiro Iwasaki, Kenji Noda, Koujirou Matsui, Shinya Itoh, Sadaaki Masuoka, Tadahiko Horiuchi, Atsushi Nakagawa, Kenju Shimogawa, Hiroyuki Takahashi:
A 16-Mb 400-MHz loadless CMOS four-transistor SRAM macro. IEEE J. Solid State Circuits 35(11): 1631-1640 (2000) - [c1]Kenji Noda, Koujirou Matsui, Shinya Ito, Sadaaki Masuoka, Hiroyuki Kawamoto, Nobuyuki Ikezawa, Koichi Takeda, Yoshiharu Aimoto, Naoto Nakamura, Hideo Toyoshima, Takahiro Iwasaki, Tadahiko Horiuchi:
An ultra-high-density high-speed loadless four-transistor SRAM macro with a dual-layered twisted bit-line and a triple-well shield. CICC 2000: 283-286
1990 – 1999
- 1997
- [j2]Kazuyuki Nakamura, Koichi Takeda, Hideo Toyoshima, Kenji Noda, Hiroaki Ohkubo, Tetsuya Uchida, Toshiyuki Shimizu, Toshiro Itani, Ken Tokashiki, Koji Kishimoto:
A 500-MHz 4-Mb CMOS pipeline-burst cache SRAM with point-to-point noise reduction coding I/O. IEEE J. Solid State Circuits 32(11): 1758-1765 (1997) - 1996
- [j1]Hideo Toyoshima, Shigeru Kuhara, Koichi Takeda, Kazuyuki Nakamura, Hiloshi Okamura, Masahide Takada, Hisamitsu Suzuki, Hiroshi Yoshida, Tohru Yamazaki:
A 6-ns, 1.5-V, 4-Mb BiCMOS SRAM. IEEE J. Solid State Circuits 31(11): 1610-1617 (1996)
Coauthor Index
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