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Takashi Ohsawa
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2020 – today
- 2024
- [j14]Yihan Zhu, Takashi Ohsawa:
Area-Efficient Binarized Neural Network Inference Accelerator Based on Time-Multiplexed XNOR Multiplier Using Loadless 4T SRAM. IEICE Trans. Electron. 107(12): 545-556 (2024) - 2023
- [j13]Yaxin Mei, Takashi Ohsawa:
A Fully Analog Deep Neural Network Inference Accelerator with Pipeline Registers Based on Master-Slave Switched Capacitors. IEICE Trans. Electron. 106(9): 477-485 (2023) - 2022
- [j12]Zian Chen, Takashi Ohsawa:
A Low-Cost Training Method of ReRAM Inference Accelerator Chips for Binarized Neural Networks to Recover Accuracy Degradation due to Statistical Variabilities. IEICE Trans. Electron. 105-C(8): 375-384 (2022) - 2021
- [j11]Haoyan Liu, Takashi Ohsawa:
Compact Model of Magnetic Tunnel Junctions for SPICE Simulation Based on Switching Probability. IEICE Trans. Electron. 104-C(3): 121-127 (2021) - 2020
- [j10]Ziyue Zhang, Takashi Ohsawa:
Array Design of High-Density Emerging Memories Making Clamped Bit-Line Sense Amplifier Compatible with Dummy Cell Average Read Scheme. IEICE Trans. Electron. 103-C(8): 372-380 (2020) - [j9]Yue Guan, Takashi Ohsawa:
Co-Design of Binary Processing in Memory ReRAM Array and DNN Model Optimization Algorithm. IEICE Trans. Electron. 103-C(11): 685-692 (2020)
2010 – 2019
- 2019
- [c4]Haoyan Liu, Takashi Ohsawa
:
User- Friendly Compact Model of Magnetic Tunnel Junctions for Circuit Simulation Based on Switching Probability. VLSI-DAT 2019: 1-4 - 2018
- [j8]Takashi Ohsawa
A New Read Scheme for High-Density Emerging Memories. IEICE Trans. Electron. 101-C(6): 423-429 (2018) - 2013
- [j7]Takashi Ohsawa
A 1 Mb Nonvolatile Embedded Memory Using 4T2MTJ Cell With 32 b Fine-Grained Power Gating Scheme. IEEE J. Solid State Circuits 48(6): 1511-1520 (2013) - 2012
- [j6]Shuta Togashi, Takashi Ohsawa
Low Power Nonvolatile Counter Unit with Fine-Grained Power Gating. IEICE Trans. Electron. 95-C(5): 854-859 (2012) - [c3]Noboru Sakimura, Ryusuke Nebashi, Yukihide Tsuji
High-speed simulator including accurate MTJ models for spintronics integrated circuit design. ISCAS 2012: 1971-1974 - [c2]Takashi Ohsawa
1Mb 4T-2MTJ nonvolatile STT-RAM for embedded memories using 32b fine-grained power gating technique with 1.0ns/200ps wake-up/power-off times. VLSIC 2012: 46-47 - 2011
- [j5]Takashi Ohsawa
Generation of Accurate Reference Current for Data Sensing in High-Density Memories by Averaging Multiple Pairs of Dummy Cells. IEEE J. Solid State Circuits 46(9): 2148-2157 (2011)
2000 – 2009
- 2006
- [j4]Takashi Ohsawa
Design of a 128-mb SOI DRAM using the floating body cell (FBC). IEEE J. Solid State Circuits 41(1): 135-145 (2006) - 2005
- [c1]Kosuke Hatsuda, Katsuyuki Fujita, Takashi Ohsawa
A 333MHz random cycle DRAM using the floating body cell. CICC 2005: 259-262 - 2002
- [j3]Takashi Ohsawa
Memory design using a one-transistor gain cell on SOI. IEEE J. Solid State Circuits 37(11): 1510-1522 (2002)
1980 – 1989
- 1989
- [j2]Tohru Furuyama, Takashi Ohsawa, Yousei Nagahama, Hiroto Tanaka, Yohji Watanabe, Tohru Kimura, Kazuyoshi Muraoka, Kenji Natori:
An experimental 2-bit/cell storage DRAM for macrocell or memory-on-logic application. IEEE J. Solid State Circuits 24(2): 388-393 (1989) - [j1]Yohji Watanabe, Takashi Ohsawa, Kiyofumi Sakurai, Tohru Furuyama:
A new CR-delay circuit technology for high-density and high-speed DRAMs. IEEE J. Solid State Circuits 24(4): 905-910 (1989)
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