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WO2019090875A1 - Goa电路 - Google Patents

Goa电路 Download PDF

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Publication number
WO2019090875A1
WO2019090875A1 PCT/CN2017/114622 CN2017114622W WO2019090875A1 WO 2019090875 A1 WO2019090875 A1 WO 2019090875A1 CN 2017114622 W CN2017114622 W CN 2017114622W WO 2019090875 A1 WO2019090875 A1 WO 2019090875A1
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WO
WIPO (PCT)
Prior art keywords
node
thin film
film transistor
electrically connected
frequency clock
Prior art date
Application number
PCT/CN2017/114622
Other languages
English (en)
French (fr)
Inventor
石龙强
Original Assignee
深圳市华星光电半导体显示技术有限公司
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Filing date
Publication date
Application filed by 深圳市华星光电半导体显示技术有限公司 filed Critical 深圳市华星光电半导体显示技术有限公司
Priority to US15/743,901 priority Critical patent/US10714041B2/en
Publication of WO2019090875A1 publication Critical patent/WO2019090875A1/zh

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Classifications

    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
    • G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
    • G09G3/3611—Control of matrices with row and column drivers
    • G09G3/3674—Details of drivers for scan electrodes
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
    • G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
    • G09G3/3611—Control of matrices with row and column drivers
    • G09G3/3674—Details of drivers for scan electrodes
    • G09G3/3677—Details of drivers for scan electrodes suitable for active matrices only
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
    • G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
    • G09G3/3611—Control of matrices with row and column drivers
    • G09G3/3696—Generation of voltages supplied to electrode drivers
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/02—Addressing, scanning or driving the display screen or processing steps related thereto
    • G09G2310/0264—Details of driving circuits
    • G09G2310/0286—Details of a shift registers arranged for use in a driving circuit
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/08—Details of timing specific for flat panels, other than clock recovery

Definitions

  • the present invention relates to the field of display technologies, and in particular, to a GOA circuit.
  • LCD Liquid crystal display
  • PDAs personal digital assistants
  • digital cameras computer screens or laptop screens, etc.
  • the active matrix liquid crystal display comprises a plurality of pixels, each of which is electrically connected to a thin film transistor (TFT), a thin film transistor.
  • TFT thin film transistor
  • a gate is connected to the horizontal scan line
  • a source is connected to the vertical data line
  • a drain is connected to the pixel electrode.
  • the Gate Driver on Array (GOA) technology utilizes an existing Array process of a thin film transistor liquid crystal display to fabricate a gate row scan driving circuit on a TFT array substrate to realize progressive scan of the gate. Drive mode.
  • GOA technology can reduce the bonding process of external integrated circuits (ICs), increase the productivity and reduce the cost of products, and make LCD panels more suitable for narrow-frame or borderless display products.
  • a metal oxide semiconductor such as Indium Gallium Zinc Oxide (IGZO) has high mobility and good device stability, and a GOA circuit is fabricated using a metal oxide semiconductor thin film transistor, which can reduce the complexity of the GOA circuit.
  • the size and number of thin film transistors and the number of power supplies used to stabilize the performance of thin film transistors are simplified, simplifying the structure of the GOA circuit and achieving a narrow bezel display while reducing power consumption.
  • the threshold voltage of the thin film transistor is likely to be negative, which causes the failure of the GOA circuit, especially in the case of a GOA circuit using a metal oxide semiconductor thin film transistor. .
  • the present invention provides a GOA circuit comprising: cascaded multi-level GOA units, each stage GOA unit includes: a pull-up control module, a pull-up module, a downlink module, a pull-down module, and a bootstrap Module and pull-down maintenance module;
  • n be a positive integer, in the nth level GOA unit:
  • the pull-up control module is electrically connected to the first node of the n+4th GOA unit and receives the level-transmitted signal and the high-frequency clock signal of the n-4th-level GOA unit for use according to the n-4th-level GOA unit
  • the level transfer signal raises the potential of the first node, and under the control of the first node of the n+4th GOA unit, pulls down the potential of the second node by using the high frequency clock signal;
  • the pull-up module is electrically connected to the first node and receives a high-frequency clock signal for outputting a scan signal by using a high-frequency clock signal under the control of the first node;
  • the downlink module is electrically connected to the first node and receives a high frequency clock signal, and is used to output a level transmission signal by using a high frequency clock signal under the control of the first node;
  • the pull-down module is electrically connected to the second node and receives the scan signal of the n+4th GOA unit, and is used to pull down the first node by using the potential of the second node under the control of the scan signal of the n+4th GOA unit.
  • the bootstrap module is electrically connected to the first node and connected to the scan signal for raising the potential of the first node and maintaining the raised potential during the scan signal output;
  • the pull-down maintaining module is electrically connected to the first node, the third node, the fourth node, the first DC low potential and the second DC low potential, and receives the first low frequency clock signal, the second low frequency clock signal, the scan signal, and a level-transmitting signal for pulling down the potentials of the third node and the fourth node to the second DC low potential when the potential of the first node is raised, and using the first low-frequency clock signal and the first after the first node potential is pulled down
  • the two low frequency clock signals alternately raise the potentials of the third node and the fourth node, respectively, to maintain the potentials of the first node, the level transfer signal, and the scan signal at a first direct current low potential.
  • the pull-up control module includes: a first thin film transistor, a second thin film transistor, and a third thin film transistor;
  • the gate and the source of the first thin film transistor are both connected to the level-transmitting signal of the n-4th stage GOA unit, and the drain is electrically connected to the second node;
  • the gate of the second thin film transistor is connected to the level-transmitting signal of the n-4th stage GOA unit, the source is electrically connected to the second node, and the drain is electrically connected to the first node;
  • the gate of the third thin film transistor is electrically connected to the first node of the n+4th stage GOA unit, the source is electrically connected to the second node, and the drain is connected to the high frequency clock signal.
  • the pull-up module includes: a fourth thin film transistor, the gate of the fourth thin film transistor is electrically connected to the first node, the source is connected to the high frequency clock signal, and the drain is outputting the scan signal.
  • the downlink module includes: a fifth thin film transistor, a gate of the fifth thin film transistor is electrically connected to the first node, a source is connected to the high frequency clock signal, and a drain output stage transmits a signal.
  • the pull-down module includes: a sixth thin film transistor, a gate of the sixth thin film transistor is connected to a scan signal of the n+4th GOA unit, a source is electrically connected to the second node, and a drain is electrically connected to the first node .
  • the bootstrap module includes: a bootstrap capacitor, the first end of the bootstrap capacitor is electrically connected to the first node, and the second end is connected to the scan signal.
  • the pull-down maintaining module includes: a first pull-down maintaining circuit and a second pull-down maintaining circuit;
  • the first pull-down maintaining circuit is electrically connected to the first node, the third node, the first DC low potential and the second DC low potential, and receives the first low frequency clock signal, the scan signal and the level transmission signal, for When the potential of the first node is raised, the potential of the third node is pulled down to the second DC low potential, and after the potential of the first node is pulled down, the potential of the third node is periodically raised by the first low frequency clock signal to The potentials of the first node, the level transmission signal and the scan signal are maintained at a first direct current low potential;
  • the second pull-down maintaining circuit is electrically connected to the first node, the fourth node, the first DC low potential and the second DC low potential, and receives the second low frequency clock signal, the scan signal and the level transmission signal, for When the potential of one node is raised, the potential of the fourth node is pulled down to the second DC low potential, and after the potential of the first node is pulled down, the potential of the fourth node is periodically raised by the second low frequency clock signal to The potential of the one node, the level transfer signal and the scan signal is maintained at the first DC low potential.
  • the first pull-down maintaining circuit includes: a seventh thin film transistor, an eighth thin film transistor, a ninth thin film transistor, a tenth thin film transistor, an eleventh thin film transistor, a twelfth thin film transistor, and a thirteenth thin film transistor;
  • the gate of the seventh thin film transistor is electrically connected to the third node, the drain is connected to the scan signal, and the source is connected to the first DC low potential;
  • the gate of the eighth thin film transistor is electrically connected to the third node, the drain is connected to the level transmitting signal, and the source is connected to the first direct current low potential;
  • the gate of the ninth thin film transistor is electrically connected to the third node, the drain is electrically connected to the first node, and the source is connected to the first DC low potential;
  • the gate and the source of the tenth thin film transistor are both connected to the first high frequency clock signal, and the drain is electrically connected to the gate of the eleventh thin film transistor;
  • the source of the eleventh thin film transistor is connected to the first high frequency clock signal, and the drain is electrically connected Third node;
  • the gate of the twelfth thin film transistor is electrically connected to the first node, the source is electrically connected to the gate of the eleventh thin film transistor, and the drain is connected to the second direct current low potential;
  • the gate of the thirteenth thin film transistor is electrically connected to the first node, the source is electrically connected to the third node, and the drain is connected to the second DC low potential;
  • the second pull-down maintaining circuit includes: a fourteenth thin film transistor, a fifteenth thin film transistor, a sixteenth thin film transistor, a seventeenth thin film transistor, an eighteenth thin film transistor, a nineteenth thin film transistor, and a twentieth film Transistor
  • the gate of the fourteenth thin film transistor is electrically connected to the fourth node, the drain is electrically connected to the first node, and the source is connected to the first DC low potential;
  • the gate of the fifteenth thin film transistor is electrically connected to the fourth node, the drain is connected to the level transmitting signal, and the source is connected to the first direct current low potential;
  • the gate of the sixteenth thin film transistor is electrically connected to the fourth node, the drain is connected to the scan signal, and the source is connected to the first DC low potential;
  • the gate and the source of the seventeenth thin film transistor are both connected to the second high frequency clock signal, and the drain is electrically connected to the gate of the eighteenth thin film transistor;
  • the source of the eighteenth thin film transistor is connected to the second high frequency clock signal, and the drain is electrically connected to the fourth node;
  • the gate of the nineteenth thin film transistor is electrically connected to the first node, the source is electrically connected to the gate of the eighteenth thin film transistor, and the drain is connected to the second direct current low potential;
  • the gate of the twentieth thin film transistor is electrically connected to the first node, the source is electrically connected to the four nodes, and the drain is connected to the second DC low potential.
  • the high frequency clock signal accessed in the nth stage GOA unit is a first high frequency clock signal, a second high frequency clock signal, a third high frequency clock signal, a fourth high frequency clock signal, and a fifth high frequency clock signal. And one of the sixth high frequency clock signal, the seventh high frequency clock signal, and the eighth high frequency clock signal, the phase of the high frequency clock signal connected to the nth stage GOA unit and the n+4th GOA The phase of the high frequency clock signal connected in the unit is opposite;
  • the first DC low potential is greater than the second DC low potential; the phase of the first low frequency clock signal is opposite to the phase of the second low frequency clock signal.
  • the invention also provides a GOA circuit, comprising: a cascaded multi-level GOA unit, each stage GOA unit comprises: a pull-up control module, a pull-up module, a downlink module, a pull-down module, a bootstrap module and a pull-down maintenance module ;
  • n be a positive integer, in the nth level GOA unit:
  • the pull-up control module is electrically connected to the first node of the n+4th GOA unit and receives the first
  • the level-transmitting signal and the high-frequency clock signal of the n-4 level GOA unit are used to raise the potential of the first node according to the level-transmitted signal of the n-4th-level GOA unit, and are at the first node of the n+4th GOA unit Controlling, using the high frequency clock signal to pull down the potential of the second node;
  • the pull-up module is electrically connected to the first node and receives a high-frequency clock signal for outputting a scan signal by using a high-frequency clock signal under the control of the first node;
  • the downlink module is electrically connected to the first node and receives a high frequency clock signal, and is used to output a level transmission signal by using a high frequency clock signal under the control of the first node;
  • the pull-down module is electrically connected to the second node and receives the scan signal of the n+4th GOA unit for using the second node under the control of the scan signal or the second start signal of the n+4th GOA unit The potential of the first node is pulled down;
  • the bootstrap module is electrically connected to the first node and connected to the scan signal for raising the potential of the first node and maintaining the raised potential during the scan signal output;
  • the pull-down maintaining module is electrically connected to the first node, the third node, the fourth node, the first DC low potential and the second DC low potential, and receives the first low frequency clock signal, the second low frequency clock signal, the scan signal, and a level-transmitting signal for pulling down the potentials of the third node and the fourth node to the second DC low potential when the potential of the first node is raised, and using the first low-frequency clock signal and the first after the first node potential is pulled down
  • the two low frequency clock signals alternately raise the potentials of the third node and the fourth node respectively to maintain the potentials of the first node, the level transmission signal and the scan signal at a first direct current low potential;
  • the pull-up control module includes: a first thin film transistor, a second thin film transistor, and a third thin film transistor;
  • the gate and the source of the first thin film transistor are both connected to the level-transmitting signal of the n-4th stage GOA unit, and the drain is electrically connected to the second node;
  • the gate of the second thin film transistor is connected to the level-transmitting signal of the n-4th stage GOA unit, the source is electrically connected to the second node, and the drain is electrically connected to the first node;
  • the gate of the third thin film transistor is electrically connected to the first node of the n+4th stage GOA unit, the source is electrically connected to the second node, and the drain is connected to the high frequency clock signal;
  • the pull-up module includes: a fourth thin film transistor, a gate of the fourth thin film transistor is electrically connected to the first node, a source is connected to the high-frequency clock signal, and a drain outputs a scan signal;
  • the downlink module includes: a fifth thin film transistor, a gate of the fifth thin film transistor is electrically connected to the first node, a source is connected to the high frequency clock signal, and a drain output stage transmits a signal;
  • the pull-down module includes: a sixth thin film transistor, the gate of the sixth thin film transistor is connected to the scan signal of the n+4th GOA unit, the source is electrically connected to the second node, and the drain is electrically connected.
  • a sixth thin film transistor the gate of the sixth thin film transistor is connected to the scan signal of the n+4th GOA unit, the source is electrically connected to the second node, and the drain is electrically connected.
  • the bootstrap module includes: a bootstrap capacitor, the first end of the bootstrap capacitor is electrically connected to the first node, and the second end is connected to the scan signal.
  • the present invention provides a GOA circuit in which an n-th stage GOA unit raises a potential of a second node during a scan signal output by using a high potential of a high-frequency clock signal, so that a potential of the second node is greater than
  • the potential of the level-transmitting signal of the n-4th stage GOA unit, so that the pull-up control module is kept off during the scan signal output, can improve the stability of the GOA circuit and prevent the GOA circuit from failing.
  • FIG. 1 is a circuit diagram of a GOA circuit of the present invention
  • FIG. 2 is a timing chart showing the operation of the GOA circuit of the present invention.
  • the present invention provides a GOA circuit, including: a cascaded multi-level GOA unit, each level of the GOA unit includes: a pull-up control module 100, a pull-up module 200, a downlink module 300, and a pull-down module 400.
  • n be a positive integer.
  • the pull-up control module 100 is electrically connected to the first node Q(n+4) of the n+4th GOA unit and receives the n-4th GOA.
  • the stage pass signal ST(n-4) and the high frequency clock signal CK are used to raise the first node Q according to the level pass signal ST(n-4) of the n-4th stage GOA unit or the first start signal STV1 ( The potential of n), and under the control of the first node Q(n+4) or the second enable signal STV2 of the n+4th GOA unit, the potential of the second node W(n) is pulled down by the high frequency clock signal CK ;
  • the pull-up module 200 is electrically connected to the first node Q(n) and receives the high-frequency clock signal CK for outputting the scan signal G by using the high-frequency clock signal CK under the control of the first node Q(n) ( n);
  • the downlink module 300 is electrically connected to the first node Q(n) and receives the high frequency clock signal CK for outputting the level transmission signal ST by using the high frequency clock signal CK under the control of the first node Q(n). (n);
  • the pull-down module 400 is electrically connected to the second node W(n) and receives the scan signal G(n+4) of the n+4th GOA unit for the scan signal G of the n+4th GOA unit ( n+4) or Under the control of the second start signal STV2, the potential of the first node Q(n) is pulled down by the potential of the second node W(n);
  • the bootstrap module 500 is electrically connected to the first node Q(n) and connected to the scan signal G(n) for raising the potential of the first node Q(n) during the output of the scan signal G(n) And maintain the potential after lifting;
  • the pull-down maintaining module 600 is electrically connected to and receives from the first node Q(n), the third node P(n), the fourth node K(n), the first DC low potential Vss1, and the second DC low potential Vss2.
  • the first low frequency clock signal LC1, the second low frequency clock signal LC2, the scan signal G(n) and the level transmission signal ST(n) are used for the third node P(n) when the potential of the first node Q(n) is raised.
  • the potential of the fourth node P(n) is pulled down to the second DC low potential Vss2, and after the potential of the first node Q(n) is pulled down, the first low frequency clock signal LC1 and the second low frequency clock signal LC2 are respectively used to alternate Raising the potentials of the third node P(n) and the fourth node K(n) to maintain the potentials of the first node Q(n), the level signal ST(n), and the scan signal G(n) A DC low potential Vss1.
  • the pull-down maintaining module 600 includes: a first pull-down maintaining circuit 601 and a second pull-down maintaining circuit 602; the first pull-down maintaining circuit 601 and the first node Q(n), the third node P(n).
  • the first DC low potential Vss1 and the second DC low potential Vss2 are electrically connected and receive the first low frequency clock signal LC1, the scan signal G(n) and the level transmission signal ST(n) for use at the first node Q. (n)
  • the potential of the third node P(n) is pulled down to the second DC low potential Vss2, and after the potential of the first node Q(n) is pulled down, the first low frequency clock signal LC1 is periodically raised.
  • a potential of the third node P(n) to maintain the potential of the first node Q(n), the level transfer signal ST(n), and the scan signal G(n) at a first DC low potential Vss1;
  • the second pull-down maintaining circuit 602 is electrically connected to the first node Q(n), the fourth node K(n), the first DC low potential Vss1, and the second DC low potential Vss2 and receives the second low frequency clock signal LC2.
  • a scan signal G(n) and a level transfer signal ST(n) for pulling down the potential of the fourth node K(n) to the second DC low potential Vss2 when the potential of the first node Q(n) is raised, and After the potential of the first node Q(n) is pulled down, the potential of the fourth node K(n) is periodically raised by the second low frequency clock signal LC2 to convert the first node Q(n) and the level signal ST ( The potential of n) and the scanning signal G(n) is maintained at the first DC low potential Vss1.
  • the pull-up control module 100 includes: a first thin film transistor T1, a second thin film transistor T2, and a third thin film transistor T3;
  • the gate and source of the first thin film transistor T1 are both connected to the pass signal ST(n-4) of the n-4th stage GOA unit, and the drain is electrically connected to the second node W(n);
  • the gate of the second thin film transistor T2 is connected to the pass signal ST(n-4) of the n-4th stage GOA unit, the source is electrically connected to the second node W(n), and the drain is electrically connected to the first Node Q(n);
  • the gate of the third thin film transistor T3 is electrically connected to the first node Q(n+4) of the n+4th stage GOA unit, the source is electrically connected to the second node W(n), and the drain is connected to the high frequency.
  • Clock signal CK is electrically connected to the first node Q(n+4) of the n+4th stage GOA unit, the source is electrically connected to the second node W(n), and the drain is connected to the high frequency.
  • the pull-up module 200 includes: a fourth thin film transistor T4, the gate of the fourth thin film transistor T4 is electrically connected to the first node Q(n), the source is connected to the high-frequency clock signal CK, and the drain outputs a scan signal. G(n).
  • the downlink module 300 includes a fifth thin film transistor T5.
  • the gate of the fifth thin film transistor T5 is electrically connected to the first node Q(n), the source is connected to the high frequency clock signal CK, and the drain output is transmitted.
  • the pull-down module 400 includes: a sixth thin film transistor T6, the gate of the sixth thin film transistor T6 is connected to the scan signal G(n+4) of the n+4th GOA unit, and the source is electrically connected to the second node. W(n), the drain is electrically connected to the first node Q(n).
  • the bootstrap module 500 includes a bootstrap capacitor Cb.
  • the first end of the bootstrap capacitor Cb is electrically connected to the first node Q(n), and the second end is connected to the scan signal G(n).
  • the first pull-down maintaining circuit 601 includes: a seventh thin film transistor T7, an eighth thin film transistor T8, a ninth thin film transistor T9, a tenth thin film transistor T10, an eleventh thin film transistor T11, a twelfth thin film transistor T12, and The thirteenth thin film transistor T13;
  • the gate of the seventh thin film transistor T7 is electrically connected to the third node P(n), the drain is connected to the scan signal G(n), and the source is connected to the first DC low potential Vss1;
  • the gate of the eighth thin film transistor T8 is electrically connected to the third node P(n), the drain is connected to the pass signal ST(n), and the source is connected to the first DC low potential Vss1;
  • the gate of the ninth thin film transistor T9 is electrically connected to the third node P(n), the drain is electrically connected to the first node Q(n), and the source is connected to the first DC low potential Vss1;
  • the gate and the source of the tenth thin film transistor T10 are both connected to the first high frequency clock signal LC1, and the drain is electrically connected to the gate of the eleventh thin film transistor T11;
  • the source of the eleventh thin film transistor T11 is connected to the first high frequency clock signal LC1, and the drain is electrically connected to the third node P(n);
  • the gate of the twelfth thin film transistor T12 is electrically connected to the first node Q(n), the source is electrically connected to the gate of the eleventh thin film transistor T11, and the drain is connected to the second DC low potential Vss2;
  • the gate of the thirteenth thin film transistor T13 is electrically connected to the first node Q(n), the source is electrically connected to the third node P(n), and the drain is connected to the second DC low potential Vss2.
  • the second pull-down maintaining circuit 602 includes: a fourteenth thin film transistor T14, a fifteenth thin film transistor T15, a sixteenth thin film transistor T16, a seventeenth thin film transistor T17, an eighteenth thin film transistor T18, and a nineteenth thin film transistor. T19, and twentieth thin film transistor T20;
  • the gate of the fourteenth thin film transistor T14 is electrically connected to the fourth node K(n), and the drain is electrically Connecting the first node Q(n), the source is connected to the first DC low potential Vss1;
  • the gate of the fifteenth thin film transistor T15 is electrically connected to the fourth node K(n), the drain is connected to the pass signal ST(n), and the source is connected to the first DC low potential Vss1;
  • the gate of the sixteenth thin film transistor T16 is electrically connected to the fourth node K(n), the drain is connected to the scan signal G(n), and the source is connected to the first DC low potential Vss1;
  • the gate and the source of the seventeenth thin film transistor T17 are both connected to the second high frequency clock signal LC2, and the drain is electrically connected to the gate of the eighteenth thin film transistor T18;
  • the eighteenth thin film transistor T18 has a source connected to the second high frequency clock signal LC2, and a drain electrically connected to the fourth node K(n);
  • the gate of the nineteenth thin film transistor T19 is electrically connected to the first node Q(n), the source is electrically connected to the gate of the eighteenth thin film transistor T18, and the drain is connected to the second DC low potential Vss2;
  • the gate of the twentieth thin film transistor T20 is electrically connected to the first node Q(n), the source is electrically connected to the four nodes K(n), and the drain is connected to the second DC low potential Vss2.
  • all the thin film transistors described in the GOA circuit of the present invention are metal oxide semiconductor thin film transistors, such as IGZO thin film transistors, and the GOA circuit of the present invention can effectively overcome the leakage problem of the IGZO thin film transistor and ensure the normal operation of the GOA circuit. Work to take full advantage of IGZO thin film transistors.
  • the high frequency clock signal CK accessed in the nth stage GOA unit is the first high frequency clock signal CK1 and the second high frequency clock signal CK2.
  • the third high frequency clock signal CK3, the fourth high frequency clock signal CK4, the fifth high frequency clock signal CK5, the sixth high frequency clock signal CK6, the seventh high frequency clock signal CK7, and the eighth high frequency clock signal CK8 One, the phase of the high frequency clock signal CK accessed in the nth stage GOA unit is opposite to the phase of the high frequency clock signal CK accessed in the n+4th stage GOA unit.
  • the first high frequency clock signal CK1, the second high frequency clock signal CK2, the third high frequency clock signal CK3, the fourth high frequency clock signal CK4, and the fifth high frequency clock signal CK5 The sixth high frequency clock signal CK6, the seventh high frequency clock signal CK7, and the eighth high frequency clock signal CK8 are sequentially phase shifted, and the first high frequency clock signal CK1, the second high frequency clock signal CK2, and the third highest
  • the periods of the frequency clock signal CK3, the fourth high frequency clock signal CK4, the fifth high frequency clock signal CK5, the sixth high frequency clock signal CK6, the seventh high frequency clock signal CK7, and the eighth high frequency clock signal CK8 are the same, accounting for The space ratio is 0.5, and the waveforms of the adjacent two high frequency clock signals are different by one eighth period.
  • the rising edge of the first high frequency clock signal CK1 is different from the rising edge of the second high frequency clock signal CK2 by eight points. A cycle.
  • the first high frequency clock signal CK1, the second high frequency clock signal CK2, the third high frequency clock signal CK3, the fourth high frequency clock signal CK4, the fifth high frequency clock signal CK5, the first The periods of the six high frequency clock signal CK6, the seventh high frequency clock signal CK7, and the eighth high frequency clock signal CK8 are both 30 ⁇ s, and the first to eighth stage GOA units sequentially access the first high frequency clock signal CK1.
  • the eighth high frequency clock signal CK8, the ninth stage GOA unit to the sixteenth stage GOA unit also sequentially access the first high frequency clock signal CK1, the second high frequency clock signal CK2, the third high frequency clock signal CK3, and the fourth The high frequency clock signal CK4, the fifth high frequency clock signal CK5, the sixth high frequency clock signal CK6, the seventh high frequency clock signal CK7, and the eighth high frequency clock signal CK8 are sequentially analogized to the last stage GOA unit.
  • the first DC low potential Vss1 is greater than the second DC low potential Vss2; the phase of the first low frequency clock signal LC1 is opposite to the phase of the second low frequency clock signal LC2.
  • the periods of the first low frequency clock signal LC1 and the second low frequency clock signal LC2 are both 200 frame durations.
  • the nth stage GOA unit is connected to the first high frequency clock signal CK(1), and the n+4th GOA unit is connected to the fifth high frequency clock signal CK. (5)
  • the specific working process of the GOA circuit is as follows:
  • the high potential of the transmission signal ST(n-4) is written to the first node Q(n) such that the first node Q(n) is raised to a high potential, and the fifth and fourth thin film transistors T5, T4 are turned on, the first high
  • the frequency clock signal CK(1) outputs a low potential
  • the nineteenth, twentieth, thirteenth, twelfth thin film transistors T19, T20, T13, T12 are turned on, and the third and fourth nodes P(n), K(n) are pulled down to the second DC low potential Vss2, the seventh, eighth, ninth, fourteenth, fifteenth, and sixteenth thin film transistors T7, T8, T9, T14, T15, T16 are turned off, and the seventh, eighth, ninth,
  • the gate-source voltages of the fourteenth, fifteenth, and sixteenth thin film transistors T7, T8, T9, T14, T15, and T16 are equal to the second DC low potential Vss2 minus the first DC low potential Vss1 due to the first straight
  • the low flow potential Vss1 is greater than the second direct current low potential Vss2, so the gate sources of the seventh, eighth, ninth, fourteenth, fifteenth, and sixteenth thin film transistors T7, T8, T9, T14, T15, and T16
  • the pole voltage is negative and the shutdown is good;
  • the scan signal G(n+4) of the n+4th GOA unit and the first node Q(n+4) are both low, and the third thin film transistor T3 and the sixth thin film transistor T6 are both turned off.
  • the graded signal ST(n-4) of the n-4th GOA unit is low, the first and second thin film crystals
  • the body tubes T1 and T2 are turned off, the first high frequency clock signal CK(1) outputs a high potential, and the fourth and fifth thin film transistors T4 and T5 are turned on to output a high level scanning signal G(n) and a level transmission signal ST, respectively.
  • the bootstrap capacitor Cb causes the first node Q(n) to rise to a higher level, while the potential of the first node Q(n+4) of the n+4th GOA unit rises to a high potential, and the third thin film transistor T3 Turning on, the high potential of the first high frequency clock signal CK(1) is written into the second node W(n) such that the gate and source voltages of the first thin film transistor T1 and the second thin film transistor T2 are negative, and are turned off. well.
  • Phase 3 the first node pull-down phase: the scan signal G(n+4) of the n+4th GOA unit becomes high, the sixth thin film transistor T6 is turned on, and the first high frequency clock signal CK(1) is output Low level to the second node W(n), the first node Q(n) is pulled down to a low potential;
  • Stage 4 low potential sustaining phase: the first node Q(n) is low, and the twelfth, thirteenth, nineteenth, and twentieth thin film transistors T12, T13, T19, T20 are turned off,
  • the first low frequency clock signal LC1 or the second low frequency clock signal LC2 provides a high level such that the third node P(n) or the fourth node K(n) is at a high level, the seventh, eighth, and ninth
  • the thin film transistors T7, T8, T9 are turned on or the fourteenth, fifteenth, and sixteenth thin film transistors T14, T15, and T16 are turned on, and the first node Q(n), the level signal ST(n), and the scan signal are pulled down.
  • the present invention replaces the level-transmitted signal ST of the n-4th-level GOA unit with the first enable signal in the first to fourth-stage GOA units of the GOA circuit ( N-4) inputting the pull-up control unit 100 to achieve normal operation of the circuit, and replacing the n+4th GOA unit with the second start signal in the fourth to last stage GOA unit of the GOA circuit
  • a node Q(n+4) is input to the pull-up control unit 100, and the high frequency clock signal CK is controlled to be written to the second node W(n).
  • the pulse periods of the first enable signal and the second enable signal are both equal to one frame duration, and the pulse width is equal to 30 ⁇ s.
  • the GOA circuit of the present invention can still work normally after the threshold voltage of the thin film transistor is shifted to the negative direction by 5V, which effectively improves the working stability of the GOA circuit.
  • the present invention provides a GOA circuit in which the n-th stage GOA unit raises the potential of the second node during the output of the scan signal by using the high potential of the high-frequency clock signal, so that the potential of the second node is greater than
  • the potential of the level-transmitting signal of the n-4 level GOA unit, so that the pull-up control module is kept off during the scan signal output, can improve the stability of the GOA circuit and prevent the GOA circuit from failing.

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Abstract

一种GOA电路，该GOA电路利用高频时钟信号（CK）的高电位在扫描信号(G（n+4）)输出期间抬升第二节点（W（n））的电位，使得第二节点（W（n））的电位大于第n-4级GOA单元的级传信号（ST(n-4)）的电位，从而在扫描信号(G（n+4）)输出期间保持上拉控制模块（100）处于关闭状态，能够提升GOA电路的稳定性，防止GOA电路失效。

Description

GOA电路 技术领域
本发明涉及显示技术领域，尤其涉及一种GOA电路。
背景技术
液晶显示器(Liquid Crystal Display，LCD)具有机身薄、省电、无辐射等众多优点，得到了广泛的应用。如：液晶电视、移动电话、个人数字助理(PDA)、数字相机、计算机屏幕或笔记本电脑屏幕等，在平板显示领域中占主导地位。
主动矩阵式液晶显示器(Active Matrix Liquid Crystal Display，AMLCD)是目前最常用的显示装置，所述主动矩阵式液晶显示器包含多个像素，每个像素电性连接一个薄膜晶体管(TFT)，薄膜晶体管的栅极(Gate)连接至水平扫描线，源极(Source)连接至垂直方向的数据线，漏极(Drain)则连接至像素电极。在水平扫描线上施加足够的电压，会使得电性连接至该条水平扫描线上的所有TFT打开，从而数据线上的信号电压能够写入像素，控制不同液晶的透光度进而达到控制色彩与亮度的效果。
阵列基板行驱动(Gate Driver on Array，GOA)技术是利用现有的薄膜晶体管液晶显示器的阵列(Array)制程将栅极行扫描驱动电路制作在TFT阵列基板上，实现对栅极逐行扫描的驱动方式。GOA技术能减少外接集成电路板(Integrated Circuit，IC)的焊接(bonding)工序，有机会提升产能并降低产品成本，而且可以使液晶显示面板更适合制作窄边框或无边框的显示产品。
诸如铟镓锌氧化物(Indium Gallium Zinc Oxide，IGZO)的金属氧化物半导体，具有高迁移率和良好的器件稳定性，采用金属氧化物半导体薄膜晶体管制作GOA电路，可减少GOA电路的复杂程度，减小薄膜晶体管的尺寸和数量、以及用来稳定薄膜晶体管的性能的电源数量，从而简化GOA电路结构，实现窄边框显示器同时降低功耗。
然而，在GOA电路的工作过程中，容易出现薄膜晶体管的阈值电压为负值，导致GOA电路的失效的情况发生，尤其是在采用金属氧化物半导体薄膜晶体管制作GOA电路中，这种情况更加严重。
发明内容
本发明的目的在于提供一种GOA电路，能够提升GOA电路的稳定性，防止GOA电路失效。
为实现上述目的，本发明提供了一种GOA电路，包括：级联的多级GOA单元，每一级GOA单元均包括：上拉控制模块、上拉模块、下传模块、下拉模块、自举模块及下拉维持模块；
设n为正整数，在第n级GOA单元中：
所述上拉控制模块与第n+4级GOA单元的第一节点电性连接并接收第n-4级GOA单元的级传信号和高频时钟信号，用于根据第n-4级GOA单元的级传信号抬升第一节点的电位，并在第n+4级GOA单元的第一节点的控制下，利用高频时钟信号下拉第二节点的电位；
所述上拉模块与第一节点电性连接并接收高频时钟信号，用于在第一节点的控制下，利用高频时钟信号输出扫描信号；
所述下传模块与第一节点电性连接并接收高频时钟信号，用于在第一节点的控制下，利用高频时钟信号输出级传信号；
所述下拉模块与第二节点电性连接并接收第n+4级GOA单元的扫描信号，用于在第n+4级GOA单元的扫描信号控制下，利用第二节点的电位下拉第一节点的电位；
所述自举模块与第一节点电性连接并连接扫描信号，用于在扫描信号输出期间使得所述第一节点的电位抬升并保持抬升后的电位；
所述下拉维持模块与第一节点、第三节点、第四节点、第一直流低电位和第二直流低电位电性连接并接收第一低频时钟信号、第二低频时钟信号、扫描信号及级传信号，用于在第一节点电位抬升时，将第三节点和第四节点的电位下拉至第二直流低电位，以及在第一节点电位被下拉后，利用第一低频时钟信号和第二低频时钟信号分别交替抬升第三节点和第四节点的电位，以将所述第一节点、级传信号和扫描信号的电位维持在第一直流低电位。
所述上拉控制模块包括：第一薄膜晶体管、第二薄膜晶体管、及第三薄膜晶体管；
所述第一薄膜晶体管的栅极和源极均接入第n-4级GOA单元的级传信号，漏极电性连接第二节点；
所述第二薄膜晶体管的栅极接入第n-4级GOA单元的级传信号，源极电性连接第二节点，漏极电性连接第一节点；
所述第三薄膜晶体管的栅极电性连接第n+4级GOA单元的第一节点，源极电性连接第二节点，漏极接入高频时钟信号。
所述上拉模块包括：第四薄膜晶体管，所述第四薄膜晶体管的栅极电性连接第一节点，源极接入高频时钟信号，漏极输出扫描信号。
所述下传模块包括：第五薄膜晶体管，所述第五薄膜晶体管的栅极电性连接第一节点，源极接入高频时钟信号，漏极输出级传信号。
所述下拉模块包括：第六薄膜晶体管，所述第六薄膜晶体管的栅极接入第n+4级GOA单元的扫描信号，源极电性连接第二节点，漏极电性连接第一节点。
所述自举模块包括：自举电容，所述自举电容的第一端电性连接第一节点，第二端接入扫描信号。
所述下拉维持模块包括：第一下拉维持电路和第二下拉维持电路；
所述第一下拉维持电路与第一节点、第三节点、第一直流低电位和第二直流低电位电性连接并接收第一低频时钟信号、扫描信号及级传信号，用于在第一节点电位抬升时，将第三节点的电位下拉至第二直流低电位，以及在第一节点电位被下拉后，利用第一低频时钟信号周期性抬升第三节点的电位，以将所述第一节点、级传信号和扫描信号的电位维持在第一直流低电位；
所述第二下拉维持电路与第一节点、第四节点、第一直流低电位和第二直流低电位电性连接并接收第二低频时钟信号、扫描信号及级传信号，用于在第一节点电位抬升时，将第四节点的电位下拉至第二直流低电位，以及在第一节点电位被下拉后，利用第二低频时钟信号周期性抬升第四节点的电位，以将所述第一节点、级传信号和扫描信号的电位维持在第一直流低电位。
所述第一下拉维持电路包括：第七薄膜晶体管、第八薄膜晶体管、第九薄膜晶体管、第十薄膜晶体管、第十一薄膜晶体管、第十二薄膜晶体管、及第十三薄膜晶体管；
所述第七薄膜晶体管的栅极电性连接第三节点，漏极接入扫描信号，源极接入第一直流低电位；
所述第八薄膜晶体管的栅极电性连接第三节点，漏极接入级传信号，源极接入第一直流低电位；
所述第九薄膜晶体管的栅极电性连接第三节点，漏极电性连接第一节点，源极接入第一直流低电位；
所述第十薄膜晶体管的栅极和源极均接入第一高频时钟信号，漏极电性连接第十一薄膜晶体管的栅极；
所述第十一薄膜晶体管的源极接入第一高频时钟信号，漏极电性连接 第三节点；
所述第十二薄膜晶体管的栅极电性连接第一节点，源极电性连接第十一薄膜晶体管的栅极，漏极接入第二直流低电位；
所述第十三薄膜晶体管的栅极电性连接第一节点，源极电性连接第三节点，漏极接入第二直流低电位；
所述第二下拉维持电路包括：第十四薄膜晶体管、第十五薄膜晶体管、第十六薄膜晶体管、第十七薄膜晶体管、第十八薄膜晶体管、第十九薄膜晶体管、及第二十薄膜晶体管；
所述第十四薄膜晶体管的栅极电性连接第四节点，漏极电性连接第一节点，源极接入第一直流低电位；
所述第十五薄膜晶体管的栅极电性连接第四节点，漏极接入级传信号，源极接入第一直流低电位；
所述第十六薄膜晶体管的栅极电性连接第四节点，漏极接入扫描信号，源极接入第一直流低电位；
所述第十七薄膜晶体管的栅极和源极均接入第二高频时钟信号，漏极电性连接第十八薄膜晶体管的栅极；
所述第十八薄膜晶体管的源极接入第二高频时钟信号，漏极电性连接第四节点；
所述第十九薄膜晶体管的栅极电性连接第一节点，源极电性连接第十八薄膜晶体管的栅极，漏极接入第二直流低电位；
所述第二十薄膜晶体管的栅极电性连接第一节点，源极电性连接四节点，漏极接入第二直流低电位。
所述第n级GOA单元中接入的高频时钟信号为第一高频时钟信号、第二高频时钟信号、第三高频时钟信号、第四高频时钟信号、第五高频时钟信号、第六高频时钟信号、第七高频时钟信号、及第八高频时钟信号中的一个，所述第n级GOA单元中接入的高频时钟信号的相位与第n+4级GOA单元中接入的高频时钟信号的相位相反；
所述第一直流低电位大于第二直流低电位；所述第一低频时钟信号的相位与第二低频时钟信号的相位相反。
本发明还提供一种GOA电路，包括：级联的多级GOA单元，每一级GOA单元均包括：上拉控制模块、上拉模块、下传模块、下拉模块、自举模块及下拉维持模块；
设n为正整数，在第n级GOA单元中：
所述上拉控制模块与第n+4级GOA单元的第一节点电性连接并接收第 n-4级GOA单元的级传信号和高频时钟信号，用于根据第n-4级GOA单元的级传信号抬升第一节点的电位，并在第n+4级GOA单元的第一节点的控制下，利用高频时钟信号下拉第二节点的电位；
所述上拉模块与第一节点电性连接并接收高频时钟信号，用于在第一节点的控制下，利用高频时钟信号输出扫描信号；
所述下传模块与第一节点电性连接并接收高频时钟信号，用于在第一节点的控制下，利用高频时钟信号输出级传信号；
所述下拉模块与第二节点电性连接并接收第n+4级GOA单元的扫描信号，用于在第n+4级GOA单元的扫描信号或第二启动信号的控制下，利用第二节点的电位下拉第一节点的电位；
所述自举模块与第一节点电性连接并连接扫描信号，用于在扫描信号输出期间使得所述第一节点的电位抬升并保持抬升后的电位；
所述下拉维持模块与第一节点、第三节点、第四节点、第一直流低电位和第二直流低电位电性连接并接收第一低频时钟信号、第二低频时钟信号、扫描信号及级传信号，用于在第一节点电位抬升时，将第三节点和第四节点的电位下拉至第二直流低电位，以及在第一节点电位被下拉后，利用第一低频时钟信号和第二低频时钟信号分别交替抬升第三节点和第四节点的电位，以将所述第一节点、级传信号和扫描信号的电位维持在第一直流低电位；
其中，所述上拉控制模块包括：第一薄膜晶体管、第二薄膜晶体管、及第三薄膜晶体管；
所述第一薄膜晶体管的栅极和源极均接入第n-4级GOA单元的级传信号，漏极电性连接第二节点；
所述第二薄膜晶体管的栅极接入第n-4级GOA单元的级传信号，源极电性连接第二节点，漏极电性连接第一节点；
所述第三薄膜晶体管的栅极电性连接第n+4级GOA单元的第一节点，源极电性连接第二节点，漏极接入高频时钟信号；
其中，所述上拉模块包括：第四薄膜晶体管，所述第四薄膜晶体管的栅极电性连接第一节点，源极接入高频时钟信号，漏极输出扫描信号；
其中，所述下传模块包括：第五薄膜晶体管，所述第五薄膜晶体管的栅极电性连接第一节点，源极接入高频时钟信号，漏极输出级传信号；
其中，所述下拉模块包括：第六薄膜晶体管，所述第六薄膜晶体管的栅极接入第n+4级GOA单元的扫描信号，源极电性连接第二节点，漏极电性连接第一节点；
其中，所述自举模块包括：自举电容，所述自举电容的第一端电性连接第一节点，第二端接入扫描信号。
本发明的有益效果：本发明提供一种GOA电路，该GOA电路中第n级GOA单元利用高频时钟信号的高电位在扫描信号输出期间抬升第二节点的电位，使得第二节点的电位大于第n-4级GOA单元的级传信号的电位，从而在扫描信号输出期间保持上拉控制模块处于关闭状态，能够提升GOA电路的稳定性，防止GOA电路失效。
附图说明
为了能更进一步了解本发明的特征以及技术内容，请参阅以下有关本发明的详细说明与附图，然而附图仅提供参考与说明用，并非用来对本发明加以限制。
附图中，
图1为本发明的GOA电路的电路图；
图2为本发明的GOA电路的工作时序图。
具体实施方式
为更进一步阐述本发明所采取的技术手段及其效果，以下结合本发明的优选实施例及其附图进行详细描述。
请参阅图1，本发明提供一种GOA电路，包括：级联的多级GOA单元，每一级GOA单元均包括：上拉控制模块100、上拉模块200、下传模块300、下拉模块400、自举模块500及下拉维持模块600；
设n为正整数，在第n级GOA单元中：所述上拉控制模块100与第n+4级GOA单元的第一节点Q(n+4)电性连接并接收第n-4级GOA单元的级传信号ST(n-4)和高频时钟信号CK，用于根据第n-4级GOA单元的级传信号ST(n-4)或第一启动信号STV1抬升第一节点Q(n)的电位，并在第n+4级GOA单元的第一节点Q(n+4)或第二启动信号STV2的控制下，利用高频时钟信号CK下拉第二节点W(n)的电位；
所述上拉模块200与第一节点Q(n)电性连接并接收高频时钟信号CK，用于在第一节点Q(n)的控制下，利用高频时钟信号CK输出扫描信号G(n)；
所述下传模块300与第一节点Q(n)电性连接并接收高频时钟信号CK，用于在第一节点Q(n)的控制下，利用高频时钟信号CK输出级传信号ST(n)；
所述下拉模块400与第二节点W(n)电性连接并接收第n+4级GOA单元的扫描信号G(n+4)，用于在第n+4级GOA单元的扫描信号G(n+4)或第 二启动信号STV2的控制下，利用第二节点W(n)的电位下拉第一节点Q(n)的电位；
所述自举模块500与第一节点Q(n)电性连接并连接扫描信号G(n)，用于在扫描信号G(n)输出期间使得所述第一节点Q(n)的电位抬升并保持抬升后的电位；
所述下拉维持模块600与第一节点Q(n)、第三节点P(n)、第四节点K(n)、第一直流低电位Vss1和第二直流低电位Vss2电性连接并接收第一低频时钟信号LC1、第二低频时钟信号LC2、扫描信号G(n)及级传信号ST(n)，用于在第一节点Q(n)电位抬升时，将第三节点P(n)和第四节点P(n)的电位下拉至第二直流低电位Vss2，以及在第一节点Q(n)电位被下拉后，利用第一低频时钟信号LC1和第二低频时钟信号LC2分别交替抬升第三节点P(n)和第四节点K(n)的电位，以将所述第一节点Q(n)、级传信号ST(n)和扫描信号G(n)的电位维持在第一直流低电位Vss1。
具体地，所述下拉维持模块600包括：第一下拉维持电路601和第二下拉维持电路602；所述第一下拉维持电路601与第一节点Q(n)、第三节点P(n)、第一直流低电位Vss1和第二直流低电位Vss2电性连接并接收第一低频时钟信号LC1、扫描信号G(n)及级传信号ST(n)，用于在第一节点Q(n)电位抬升时，将第三节点P(n)的电位下拉至第二直流低电位Vss2，以及在第一节点Q(n)电位被下拉后，利用第一低频时钟信号LC1周期性抬升第三节点P(n)的电位，以将所述第一节点Q(n)、级传信号ST(n)和扫描信号G(n)的电位维持在第一直流低电位Vss1；
所述第二下拉维持电路602与第一节点Q(n)、第四节点K(n)、第一直流低电位Vss1和第二直流低电位Vss2电性连接并接收第二低频时钟信号LC2、扫描信号G(n)及级传信号ST(n)，用于在第一节点Q(n)电位抬升时，将第四节点K(n)的电位下拉至第二直流低电位Vss2，以及在第一节点Q(n)电位被下拉后，利用第二低频时钟信号LC2周期性抬升第四节点K(n)的电位，以将所述第一节点Q(n)、级传信号ST(n)和扫描信号G(n)的电位维持在第一直流低电位Vss1。
具体地，如图1所示，在本发明的优选实施例中，所述上拉控制模块100包括：第一薄膜晶体管T1、第二薄膜晶体管T2、及第三薄膜晶体管T3；
所述第一薄膜晶体管T1的栅极和源极均接入第n-4级GOA单元的级传信号ST(n-4)，漏极电性连接第二节点W(n)；
所述第二薄膜晶体管T2的栅极接入第n-4级GOA单元的级传信号ST(n-4)，源极电性连接第二节点W(n)，漏极电性连接第一节点Q(n)；
所述第三薄膜晶体管T3的栅极电性连接第n+4级GOA单元的第一节点Q(n+4)，源极电性连接第二节点W(n)，漏极接入高频时钟信号CK。
所述上拉模块200包括：第四薄膜晶体管T4，所述第四薄膜晶体管T4的栅极电性连接第一节点Q(n)，源极接入高频时钟信号CK，漏极输出扫描信号G(n)。
所述下传模块300包括：第五薄膜晶体管T5，所述第五薄膜晶体管T5的栅极电性连接第一节点Q(n)，源极接入高频时钟信号CK，漏极输出级传信号ST(n)。
所述下拉模块400包括：第六薄膜晶体管T6，所述第六薄膜晶体管T6的栅极接入第n+4级GOA单元的扫描信号G(n+4)，源极电性连接第二节点W(n)，漏极电性连接第一节点Q(n)。
所述自举模块500包括：自举电容Cb，所述自举电容Cb的第一端电性连接第一节点Q(n)，第二端接入扫描信号G(n)。
所述第一下拉维持电路601包括：第七薄膜晶体管T7、第八薄膜晶体管T8、第九薄膜晶体管T9、第十薄膜晶体管T10、第十一薄膜晶体管T11、第十二薄膜晶体管T12、及第十三薄膜晶体管T13；
所述第七薄膜晶体管T7的栅极电性连接第三节点P(n)，漏极接入扫描信号G(n)，源极接入第一直流低电位Vss1；
所述第八薄膜晶体管T8的栅极电性连接第三节点P(n)，漏极接入级传信号ST(n)，源极接入第一直流低电位Vss1；
所述第九薄膜晶体管T9的栅极电性连接第三节点P(n)，漏极电性连接第一节点Q(n)，源极接入第一直流低电位Vss1；
所述第十薄膜晶体管T10的栅极和源极均接入第一高频时钟信号LC1，漏极电性连接第十一薄膜晶体管T11的栅极；
所述第十一薄膜晶体管T11的源极接入第一高频时钟信号LC1，漏极电性连接第三节点P(n)；
所述第十二薄膜晶体管T12的栅极电性连接第一节点Q(n)，源极电性连接第十一薄膜晶体管T11的栅极，漏极接入第二直流低电位Vss2；
所述第十三薄膜晶体管T13的栅极电性连接第一节点Q(n)，源极电性连接第三节点P(n)，漏极接入第二直流低电位Vss2。
所述第二下拉维持电路602包括：第十四薄膜晶体管T14、第十五薄膜晶体管T15、第十六薄膜晶体管T16、第十七薄膜晶体管T17、第十八薄膜晶体管T18、第十九薄膜晶体管T19、及第二十薄膜晶体管T20；
所述第十四薄膜晶体管T14的栅极电性连接第四节点K(n)，漏极电性 连接第一节点Q(n)，源极接入第一直流低电位Vss1；
所述第十五薄膜晶体管T15的栅极电性连接第四节点K(n)，漏极接入级传信号ST(n)，源极接入第一直流低电位Vss1；
所述第十六薄膜晶体管T16的栅极电性连接第四节点K(n)，漏极接入扫描信号G(n)，源极接入第一直流低电位Vss1；
所述第十七薄膜晶体管T17的栅极和源极均接入第二高频时钟信号LC2，漏极电性连接第十八薄膜晶体管T18的栅极；
所述第十八薄膜晶体管T18的源极接入第二高频时钟信号LC2，漏极电性连接第四节点K(n)；
所述第十九薄膜晶体管T19的栅极电性连接第一节点Q(n)，源极电性连接第十八薄膜晶体管T18的栅极，漏极接入第二直流低电位Vss2；
所述第二十薄膜晶体管T20的栅极电性连接第一节点Q(n)，源极电性连接四节点K(n)，漏极接入第二直流低电位Vss2。
优选地，本发明的GOA电路中所述的所有薄膜晶体管均为金属氧化物半导体薄膜晶体管，如：IGZO薄膜晶体管，通过本发明的GOA电路能够有效克服IGZO薄膜晶体管的漏电问题，保证GOA电路正常工作，充分发挥IGZO薄膜晶体管的优势。
具体地，如图2所示，在本发明的优选实施例，所述第n级GOA单元中接入的高频时钟信号CK为第一高频时钟信号CK1、第二高频时钟信号CK2、第三高频时钟信号CK3、第四高频时钟信号CK4、第五高频时钟信号CK5、第六高频时钟信号CK6、第七高频时钟信号CK7、及第八高频时钟信号CK8中的一个，所述第n级GOA单元中接入的高频时钟信号CK的相位与第n+4级GOA单元中接入的高频时钟信号CK的相位相反。
进一步地，如图2所示，所述第一高频时钟信号CK1、第二高频时钟信号CK2、第三高频时钟信号CK3、第四高频时钟信号CK4、第五高频时钟信号CK5、第六高频时钟信号CK6、第七高频时钟信号CK7、及第八高频时钟信号CK8依次相移，所述第一高频时钟信号CK1、第二高频时钟信号CK2、第三高频时钟信号CK3、第四高频时钟信号CK4、第五高频时钟信号CK5、第六高频时钟信号CK6、第七高频时钟信号CK7、及第八高频时钟信号CK8的周期相同，占空比为0.5，相邻的两个高频时钟信号的波形相差八分之一个周期，例如第一高频时钟信号CK1的上升沿与第二高频时钟信号CK2的上升沿相差八分之一个周期。
优选地，所述第一高频时钟信号CK1、第二高频时钟信号CK2、第三高频时钟信号CK3、第四高频时钟信号CK4、第五高频时钟信号CK5、第 六高频时钟信号CK6、第七高频时钟信号CK7、及第八高频时钟信号CK8的周期均为30μs，所述第一级至第八级GOA单元依次接入第一高频时钟信号CK1、第二高频时钟信号CK2、第三高频时钟信号CK3、第四高频时钟信号CK4、第五高频时钟信号CK5、第六高频时钟信号CK6、第七高频时钟信号CK7、及第八高频时钟信号CK8，第九级GOA单元至第十六级GOA单元也依次接入第一高频时钟信号CK1、第二高频时钟信号CK2、第三高频时钟信号CK3、第四高频时钟信号CK4、第五高频时钟信号CK5、第六高频时钟信号CK6、第七高频时钟信号CK7、及第八高频时钟信号CK8，依次类推至最后一级GOA单元。
进一步地，如图2所示，所述第一直流低电位Vss1大于第二直流低电位Vss2；所述第一低频时钟信号LC1的相位与第二低频时钟信号LC2的相位相反。
优选地，所述第一低频时钟信号LC1与第二低频时钟信号LC2的周期均为200帧时长。
需要说明的是，本发明的优选实施例的GOA电路，设第n级GOA单元接入第一高频时钟信号CK(1)，第n+4级GOA单元接入第五高频时钟信号CK(5)，此时该GOA电路具体工作过程如下：
阶段1，预充电：第n-4级GOA单元的级传信号ST(n-4)为高电位，所述第一和第二薄膜晶体管T1和T2打开，第n-4级GOA单元的级传信号ST(n-4)的高电位写入第一节点Q(n)，使得第一节点Q(n)抬升至高电位，所述第五和第四薄膜晶体管T5、T4打开，第一高频时钟信号CK(1)输出低电位；
第十九、第二十、第十三、第十二薄膜晶体管T19、T20、T13、T12打开，第三和第四节点P(n)、K(n)被拉低至第二直流低电位Vss2，所述第七、第八、第九、第十四、第十五、及第十六薄膜晶体管T7、T8、T9、T14、T15、T16关闭，且第七、第八、第九、第十四、第十五、及第十六薄膜晶体管T7、T8、T9、T14、T15、T16的栅源极电压等于第二直流低电位Vss2减第一直流低电位Vss1，由于第一直流低电位Vss1大于第二直流低电位Vss2，因此第七、第八、第九、第十四、第十五、及第十六薄膜晶体管T7、T8、T9、T14、T15、T16的栅源极电压为负值，关闭的很好；
第n+4级GOA单元的扫描信号G(n+4)和第一节点Q(n+4)均为低电位，所述第三薄膜晶体管T3和第六薄膜晶体管T6均关闭。
阶段2、扫描信号输出阶段；
第n-4级GOA单元的级传信号ST(n-4)为低电位，第一和第二薄膜晶 体管T1、T2关闭，第一高频时钟信号CK(1)输出高电位，第四和第五薄膜晶体管T4、T5打开，分别输出高电平的扫描信号G(n)和级传信号ST(n)，自举电容Cb使得第一节点Q(n)抬升至更高，同时第n+4级GOA单元的第一节点Q(n+4)的电位抬升至高电位，第三薄膜晶体管T3打开，所述第一高频时钟信号CK(1)的高电位写入第二节点W(n)，使得第一薄膜晶体管T1和第二薄膜晶体管T2的栅源极电压为负值，关闭的很好。
阶段3、第一节点下拉阶段：第n+4级GOA单元的扫描信号G(n+4)变为高电位，所述第六薄膜晶体管T6打开，第一高频时钟信号CK(1)输出低电平至第二节点W(n)，所述第一节点Q(n)被下拉至低电位；
阶段4、低电位维持阶段：第一节点Q(n)为低电位，所述第十二、第十三、第十九、及第二十薄膜晶体管T12、T13、T19、T20关闭，所述第一低频时钟信号LC1或第二低频时钟信号LC2提供高电平，使得第三节点P(n)或第四节点K(n)为高电平，所述第七、第八、及第九薄膜晶体管T7、T8、T9打开或者第十四、第十五、及第十六薄膜晶体管T14、T15、T16打开，下拉第一节点Q(n)、级传信号ST(n)、及扫描信号G(n)至第一直流低电位Vss1，并持续保持。
值得一提的是，为了实现电路的正常启动，本发明在GOA电路的第一至第四级GOA单元中，采用第一启动信号替代所述第n-4级GOA单元的级传信号ST(n-4)输入所述上拉控制单元100，实现电路的正常工作，在GOA电路的倒数第四级至最后一级GOA单元中，采用第二启动信号替代第n+4级GOA单元的第一节点Q(n+4)输入到所述上拉控制单元100，控制所述高频时钟信号CK写入到所述第二节点W(n)。优选地，所述第一启动信号和第二启动信号的脉冲周期均等于一帧时长，脉冲宽度等于30μs。
经过仿真测试，本发明的GOA电路，在薄膜晶体管的阈值电压向负方向偏移5V之后仍可正常工作，有效提升了GOA电路的工作稳定性。
综上所述，本发明提供一种GOA电路，该GOA电路中第n级GOA单元利用高频时钟信号的高电位在扫描信号输出期间抬升第二节点的电位，使得第二节点的电位大于第n-4级GOA单元的级传信号的电位，从而在扫描信号输出期间保持上拉控制模块处于关闭状态，能够提升GOA电路的稳定性，防止GOA电路失效。
以上所述，对于本领域的普通技术人员来说，可以根据本发明的技术方案和技术构思作出其他各种相应的改变和变形，而所有这些改变和变形都应属于本发明权利要求的保护范围。

Claims (15)

  1. 一种GOA电路，包括：级联的多级GOA单元，每一级GOA单元均包括：上拉控制模块、上拉模块、下传模块、下拉模块、自举模块及下拉维持模块；
    设n为正整数，在第n级GOA单元中：
    所述上拉控制模块与第n+4级GOA单元的第一节点电性连接并接收第n-4级GOA单元的级传信号和高频时钟信号，用于根据第n-4级GOA单元的级传信号抬升第一节点的电位，并在第n+4级GOA单元的第一节点的控制下，利用高频时钟信号下拉第二节点的电位；
    所述上拉模块与第一节点电性连接并接收高频时钟信号，用于在第一节点的控制下，利用高频时钟信号输出扫描信号；
    所述下传模块与第一节点电性连接并接收高频时钟信号，用于在第一节点的控制下，利用高频时钟信号输出级传信号；
    所述下拉模块与第二节点电性连接并接收第n+4级GOA单元的扫描信号，用于在第n+4级GOA单元的扫描信号或第二启动信号的控制下，利用第二节点的电位下拉第一节点的电位；
    所述自举模块与第一节点电性连接并连接扫描信号，用于在扫描信号输出期间使得所述第一节点的电位抬升并保持抬升后的电位；
    所述下拉维持模块与第一节点、第三节点、第四节点、第一直流低电位和第二直流低电位电性连接并接收第一低频时钟信号、第二低频时钟信号、扫描信号及级传信号，用于在第一节点电位抬升时，将第三节点和第四节点的电位下拉至第二直流低电位，以及在第一节点电位被下拉后，利用第一低频时钟信号和第二低频时钟信号分别交替抬升第三节点和第四节点的电位，以将所述第一节点、级传信号和扫描信号的电位维持在第一直流低电位。
  2. 如权利要求1所述的GOA电路，其中，所述上拉控制模块包括：第一薄膜晶体管、第二薄膜晶体管、及第三薄膜晶体管；
    所述第一薄膜晶体管的栅极和源极均接入第n-4级GOA单元的级传信号，漏极电性连接第二节点；
    所述第二薄膜晶体管的栅极接入第n-4级GOA单元的级传信号，源极电性连接第二节点，漏极电性连接第一节点；
    所述第三薄膜晶体管的栅极电性连接第n+4级GOA单元的第一节点， 源极电性连接第二节点，漏极接入高频时钟信号。
  3. 如权利要求1所述的GOA电路，其中，所述上拉模块包括：第四薄膜晶体管，所述第四薄膜晶体管的栅极电性连接第一节点，源极接入高频时钟信号，漏极输出扫描信号。
  4. 如权利要求1所述的GOA电路，其中，所述下传模块包括：第五薄膜晶体管，所述第五薄膜晶体管的栅极电性连接第一节点，源极接入高频时钟信号，漏极输出级传信号。
  5. 如权利要求1所述的GOA电路，其中，所述下拉模块包括：第六薄膜晶体管，所述第六薄膜晶体管的栅极接入第n+4级GOA单元的扫描信号，源极电性连接第二节点，漏极电性连接第一节点。
  6. 如权利要求1所述的GOA电路，其中，所述自举模块包括：自举电容，所述自举电容的第一端电性连接第一节点，第二端接入扫描信号。
  7. 如权利要求1所述的GOA电路，其中，所述下拉维持模块包括：第一下拉维持电路和第二下拉维持电路；
    所述第一下拉维持电路与第一节点、第三节点、第一直流低电位和第二直流低电位电性连接并接收第一低频时钟信号、扫描信号及级传信号，用于在第一节点电位抬升时，将第三节点的电位下拉至第二直流低电位，以及在第一节点电位被下拉后，利用第一低频时钟信号周期性抬升第三节点的电位，以将所述第一节点、级传信号和扫描信号的电位维持在第一直流低电位；
    所述第二下拉维持电路与第一节点、第四节点、第一直流低电位和第二直流低电位电性连接并接收第二低频时钟信号、扫描信号及级传信号，用于在第一节点电位抬升时，将第四节点的电位下拉至第二直流低电位，以及在第一节点电位被下拉后，利用第二低频时钟信号周期性抬升第四节点的电位，以将所述第一节点、级传信号和扫描信号的电位维持在第一直流低电位。
  8. 如权利要求7所述的GOA电路，其中，所述第一下拉维持电路包括：第七薄膜晶体管、第八薄膜晶体管、第九薄膜晶体管、第十薄膜晶体管、第十一薄膜晶体管、第十二薄膜晶体管、及第十三薄膜晶体管；
    所述第七薄膜晶体管的栅极电性连接第三节点，漏极接入扫描信号，源极接入第一直流低电位；
    所述第八薄膜晶体管的栅极电性连接第三节点，漏极接入级传信号，源极接入第一直流低电位；
    所述第九薄膜晶体管的栅极电性连接第三节点，漏极电性连接第一节 点，源极接入第一直流低电位；
    所述第十薄膜晶体管的栅极和源极均接入第一高频时钟信号，漏极电性连接第十一薄膜晶体管的栅极；
    所述第十一薄膜晶体管的源极接入第一高频时钟信号，漏极电性连接第三节点；
    所述第十二薄膜晶体管的栅极电性连接第一节点，源极电性连接第十一薄膜晶体管的栅极，漏极接入第二直流低电位；
    所述第十三薄膜晶体管的栅极电性连接第一节点，源极电性连接第三节点，漏极接入第二直流低电位；
    所述第二下拉维持电路包括：第十四薄膜晶体管、第十五薄膜晶体管、第十六薄膜晶体管、第十七薄膜晶体管、第十八薄膜晶体管、第十九薄膜晶体管、及第二十薄膜晶体管；
    所述第十四薄膜晶体管的栅极电性连接第四节点，漏极电性连接第一节点，源极接入第一直流低电位；
    所述第十五薄膜晶体管的栅极电性连接第四节点，漏极接入级传信号，源极接入第一直流低电位；
    所述第十六薄膜晶体管的栅极电性连接第四节点，漏极接入扫描信号，源极接入第一直流低电位；
    所述第十七薄膜晶体管的栅极和源极均接入第二高频时钟信号，漏极电性连接第十八薄膜晶体管的栅极；
    所述第十八薄膜晶体管的源极接入第二高频时钟信号，漏极电性连接第四节点；
    所述第十九薄膜晶体管的栅极电性连接第一节点，源极电性连接第十八薄膜晶体管的栅极，漏极接入第二直流低电位；
    所述第二十薄膜晶体管的栅极电性连接第一节点，源极电性连接四节点，漏极接入第二直流低电位。
  9. 如权利要求1所述的GOA电路，其中，所述第n级GOA单元中接入的高频时钟信号为第一高频时钟信号、第二高频时钟信号、第三高频时钟信号、第四高频时钟信号、第五高频时钟信号、第六高频时钟信号、第七高频时钟信号、及第八高频时钟信号中的一个，所述第n级GOA单元中接入的高频时钟信号的相位与第n+4级GOA单元中接入的高频时钟信号的相位相反。
  10. 如权利要求1所述的GOA电路，其中，所述第一直流低电位大于第二直流低电位；所述第一低频时钟信号的相位与第二低频时钟信号的相 位相反。
  11. 一种GOA电路，包括：级联的多级GOA单元，每一级GOA单元均包括：上拉控制模块、上拉模块、下传模块、下拉模块、自举模块及下拉维持模块；
    设n为正整数，在第n级GOA单元中：
    所述上拉控制模块与第n+4级GOA单元的第一节点电性连接并接收第n-4级GOA单元的级传信号和高频时钟信号，用于根据第n-4级GOA单元的级传信号抬升第一节点的电位，并在第n+4级GOA单元的第一节点的控制下，利用高频时钟信号下拉第二节点的电位；
    所述上拉模块与第一节点电性连接并接收高频时钟信号，用于在第一节点的控制下，利用高频时钟信号输出扫描信号；
    所述下传模块与第一节点电性连接并接收高频时钟信号，用于在第一节点的控制下，利用高频时钟信号输出级传信号；
    所述下拉模块与第二节点电性连接并接收第n+4级GOA单元的扫描信号，用于在第n+4级GOA单元的扫描信号或第二启动信号的控制下，利用第二节点的电位下拉第一节点的电位；
    所述自举模块与第一节点电性连接并连接扫描信号，用于在扫描信号输出期间使得所述第一节点的电位抬升并保持抬升后的电位；
    所述下拉维持模块与第一节点、第三节点、第四节点、第一直流低电位和第二直流低电位电性连接并接收第一低频时钟信号、第二低频时钟信号、扫描信号及级传信号，用于在第一节点电位抬升时，将第三节点和第四节点的电位下拉至第二直流低电位，以及在第一节点电位被下拉后，利用第一低频时钟信号和第二低频时钟信号分别交替抬升第三节点和第四节点的电位，以将所述第一节点、级传信号和扫描信号的电位维持在第一直流低电位；
    其中，所述上拉控制模块包括：第一薄膜晶体管、第二薄膜晶体管、及第三薄膜晶体管；
    所述第一薄膜晶体管的栅极和源极均接入第n-4级GOA单元的级传信号，漏极电性连接第二节点；
    所述第二薄膜晶体管的栅极接入第n-4级GOA单元的级传信号，源极电性连接第二节点，漏极电性连接第一节点；
    所述第三薄膜晶体管的栅极电性连接第n+4级GOA单元的第一节点，源极电性连接第二节点，漏极接入高频时钟信号；
    其中，所述上拉模块包括：第四薄膜晶体管，所述第四薄膜晶体管的 栅极电性连接第一节点，源极接入高频时钟信号，漏极输出扫描信号；
    其中，所述下传模块包括：第五薄膜晶体管，所述第五薄膜晶体管的栅极电性连接第一节点，源极接入高频时钟信号，漏极输出级传信号；
    其中，所述下拉模块包括：第六薄膜晶体管，所述第六薄膜晶体管的栅极接入第n+4级GOA单元的扫描信号，源极电性连接第二节点，漏极电性连接第一节点；
    其中，所述自举模块包括：自举电容，所述自举电容的第一端电性连接第一节点，第二端接入扫描信号。
  12. 如权利要求11所述的GOA电路，其中，所述下拉维持模块包括：第一下拉维持电路和第二下拉维持电路；
    所述第一下拉维持电路与第一节点、第三节点、第一直流低电位和第二直流低电位电性连接并接收第一低频时钟信号、扫描信号及级传信号，用于在第一节点电位抬升时，将第三节点的电位下拉至第二直流低电位，以及在第一节点电位被下拉后，利用第一低频时钟信号周期性抬升第三节点的电位，以将所述第一节点、级传信号和扫描信号的电位维持在第一直流低电位；
    所述第二下拉维持电路与第一节点、第四节点、第一直流低电位和第二直流低电位电性连接并接收第二低频时钟信号、扫描信号及级传信号，用于在第一节点电位抬升时，将第四节点的电位下拉至第二直流低电位，以及在第一节点电位被下拉后，利用第二低频时钟信号周期性抬升第四节点的电位，以将所述第一节点、级传信号和扫描信号的电位维持在第一直流低电位。
  13. 如权利要求12所述的GOA电路，其中，所述第一下拉维持电路包括：第七薄膜晶体管、第八薄膜晶体管、第九薄膜晶体管、第十薄膜晶体管、第十一薄膜晶体管、第十二薄膜晶体管、及第十三薄膜晶体管；
    所述第七薄膜晶体管的栅极电性连接第三节点，漏极接入扫描信号，源极接入第一直流低电位；
    所述第八薄膜晶体管的栅极电性连接第三节点，漏极接入级传信号，源极接入第一直流低电位；
    所述第九薄膜晶体管的栅极电性连接第三节点，漏极电性连接第一节点，源极接入第一直流低电位；
    所述第十薄膜晶体管的栅极和源极均接入第一高频时钟信号，漏极电性连接第十一薄膜晶体管的栅极；
    所述第十一薄膜晶体管的源极接入第一高频时钟信号，漏极电性连接 第三节点；
    所述第十二薄膜晶体管的栅极电性连接第一节点，源极电性连接第十一薄膜晶体管的栅极，漏极接入第二直流低电位；
    所述第十三薄膜晶体管的栅极电性连接第一节点，源极电性连接第三节点，漏极接入第二直流低电位；
    所述第二下拉维持电路包括：第十四薄膜晶体管、第十五薄膜晶体管、第十六薄膜晶体管、第十七薄膜晶体管、第十八薄膜晶体管、第十九薄膜晶体管、及第二十薄膜晶体管；
    所述第十四薄膜晶体管的栅极电性连接第四节点，漏极电性连接第一节点，源极接入第一直流低电位；
    所述第十五薄膜晶体管的栅极电性连接第四节点，漏极接入级传信号，源极接入第一直流低电位；
    所述第十六薄膜晶体管的栅极电性连接第四节点，漏极接入扫描信号，源极接入第一直流低电位；
    所述第十七薄膜晶体管的栅极和源极均接入第二高频时钟信号，漏极电性连接第十八薄膜晶体管的栅极；
    所述第十八薄膜晶体管的源极接入第二高频时钟信号，漏极电性连接第四节点；
    所述第十九薄膜晶体管的栅极电性连接第一节点，源极电性连接第十八薄膜晶体管的栅极，漏极接入第二直流低电位；
    所述第二十薄膜晶体管的栅极电性连接第一节点，源极电性连接四节点，漏极接入第二直流低电位。
  14. 如权利要求11所述的GOA电路，其中，所述第n级GOA单元中接入的高频时钟信号为第一高频时钟信号、第二高频时钟信号、第三高频时钟信号、第四高频时钟信号、第五高频时钟信号、第六高频时钟信号、第七高频时钟信号、及第八高频时钟信号中的一个，所述第n级GOA单元中接入的高频时钟信号的相位与第n+4级GOA单元中接入的高频时钟信号的相位相反。
  15. 如权利要求11所述的GOA电路，其中，所述第一直流低电位大于第二直流低电位；所述第一低频时钟信号的相位与第二低频时钟信号的相位相反。
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