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WO2020019426A1 - 包括goa电路的液晶面板及其驱动方法 - Google Patents

包括goa电路的液晶面板及其驱动方法 Download PDF

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Publication number
WO2020019426A1
WO2020019426A1 PCT/CN2018/105166 CN2018105166W WO2020019426A1 WO 2020019426 A1 WO2020019426 A1 WO 2020019426A1 CN 2018105166 W CN2018105166 W CN 2018105166W WO 2020019426 A1 WO2020019426 A1 WO 2020019426A1
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WIPO (PCT)
Prior art keywords
circuit unit
clock signal
pull
period
thin film
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PCT/CN2018/105166
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English (en)
French (fr)
Inventor
陈帅
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深圳市华星光电技术有限公司
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Priority to US16/322,044 priority Critical patent/US10825412B2/en
Publication of WO2020019426A1 publication Critical patent/WO2020019426A1/zh

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    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
    • G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
    • G09G3/3611—Control of matrices with row and column drivers
    • G09G3/3674—Details of drivers for scan electrodes
    • G09G3/3677—Details of drivers for scan electrodes suitable for active matrices only

Definitions

  • the present invention relates to the field of display technology, and more particularly, to a liquid crystal panel including a GOA (Gate Driver On Array) circuit and a driving method thereof.
  • GOA Gate Driver On Array
  • Liquid crystal displays have the advantages of low radiation, small size, and low energy consumption. They have been widely used in notebook computers, personal digital assistants, PDAs, flat-screen televisions, or mobile phones.
  • the traditional liquid crystal display method uses an external driving chip to drive the chip on the panel to display the image.
  • it has gradually developed to directly drive the circuit structure on the display panel, for example, using GOA technology. .
  • the GOA technology integrates a TFT LCD (Thin Film Transistor Liquid Crystal Display) gate drive circuit on a glass substrate to form a scan drive for a liquid crystal panel.
  • TFT LCD Thin Film Transistor Liquid Crystal Display
  • COF Chip, Flex / Film
  • GOA technology can greatly save manufacturing costs, and eliminates the Bonding process of the gate-side COF, which is also extremely beneficial to the improvement of production capacity. Therefore, GOA is a key technology for the development of LCD panels in the future.
  • the existing GOA circuit usually includes a plurality of single-stage GOA circuit units cascaded, and each single-stage GOA circuit unit corresponds to a scan driving line of a corresponding stage.
  • the single-stage GOA circuit unit includes: a pull-up control circuit unit 1, a pull-up circuit unit 2, a download circuit unit 3, a pull-down circuit unit 4, a pull-down sustain circuit unit 5, and a bootstrap capacitor 6.
  • the pull-up control circuit unit 1 mainly implements pre-charging for the pre-charging node Q (N), which is usually input to the down-going signal ST (N-1) and the scan driving signal G ( N-1); the pull-up circuit unit 2 is mainly used to increase the potential of the scan driving signal G (N); the signal transmission unit 3 includes a thin film transistor, which mainly controls the next by outputting the downstream signal ST (N) of this stage
  • the pull-up control circuit unit in the first-level GOA circuit unit is turned on and off; the pull-down circuit unit 4 is mainly used to pull down the potential of the pre-charge node Q (N) and the scan drive signal G (N) to a low power supply voltage VSS; pull-down maintenance
  • the circuit unit 5 may include an inverter and a plurality of thin film transistors, which are mainly used to maintain the potentials of the precharge node Q (N) and the scan driving signal G (N) at a low power supply voltage VSS; the bootstrap capacitor 6 mainly In order to
  • the inverter of the pull-down sustaining circuit unit 5 can use a Darlington inverter.
  • the specific circuit structure is shown in Figure 2.
  • the Darlington inverter can include four thin film transistors and can have input terminals Input and output terminals. Output. If the control signal LC is set to always be a high-potential signal and the low power supply voltage VSS is set to always be a low-potential signal, when a high-potential signal is input at the input terminal Input, a low-potential signal is output at the output terminal; When a low potential signal is output, the output terminal Output outputs a high potential signal.
  • the pull-down sustaining circuit unit 5 includes a Darlington inverter
  • a single-stage GOA circuit unit is shown in FIG. 3.
  • two pull-down sustaining circuit units 5-1 and 5-2 are alternately operated according to the waveforms shown in FIG. 5 to prevent the thin film transistors T32, T42, T33, and T43 from being subjected to positive bias stress for a long time (Positive Bias Stress, PBS), and the threshold voltage Vth of the thin film transistor drifts forward, which causes the device to fail.
  • PBS Positive Bias Stress
  • a liquid crystal panel using GOA technology usually includes the following signal traces: a common electrode signal Acom on an array substrate, and a color pattern substrate.
  • the space occupied by the GOA circuit is also getting larger and larger, which is extremely disadvantageous for the design of a narrow-frame LCD panel. Therefore, how to reduce the number of signal lines and how to efficiently use the signal lines are extremely important for the future development of liquid crystal panels.
  • An exemplary embodiment of the present invention is to provide a liquid crystal panel including a GOA circuit and a driving method thereof.
  • the GOA circuit is input with a set of newly designed clock signals.
  • the set of clock signals can meet the signal requirements of the pull-up circuit unit, and can also replace the control signals in the pull-down maintenance circuit unit, thereby efficiently using the clock signal line and effectively saving.
  • the space occupied by the wiring in the display panel provides a new possibility for the design of future GOA circuits.
  • An aspect of the present invention provides a liquid crystal panel including a GOA circuit, the GOA circuit comprising a plurality of cascaded single-stage GOA circuit units, wherein each single-stage GOA circuit unit includes a pull-up control circuit unit, a pull-up circuit Unit, pull-down circuit unit, bootstrap capacitor, download circuit unit, first pull-down sustain circuit unit, and second pull-down sustain circuit unit, wherein in each single-stage GOA circuit unit, the The first control terminal is configured to receive a first clock signal, the second control terminal of the second pull-down sustain circuit unit is configured to receive a second clock signal, and the pull-down circuit unit is configured to receive a scan drive from the next two levels of GOA circuit units.
  • the pull-up circuit units in the two adjacent GOA circuit units are configured to alternately receive the first clock signal and the second clock signal, wherein the first clock signal and the second clock signal have a period of the same length Where the second clock signal is delayed relative to the first clock signal, so that the second clock signal is within each high potential period of the first clock signal
  • the first period and the third period have a high potential
  • the second period between the first period and the third period has a low potential.
  • the first pull-down sustaining circuit unit may include a first inverter having a first input terminal, a first output terminal, and a first control terminal.
  • the first input terminal is connected to a precharge node, and the first The output terminal is connected to the gates of the sixth thin film transistor and the seventh thin film transistor;
  • the gate of the sixth thin film transistor is connected to the gate of the seventh thin film transistor, the drain is connected to the low power voltage line, and the source is connected to Scan driving lines of this stage; and a seventh thin film transistor whose gate is connected to the gate of the sixth thin film transistor, whose drain is connected to the low power supply voltage line, and whose source is connected to the precharge node.
  • the second pull-down sustaining circuit unit may include a second inverter having a second input terminal, a second output terminal, and a second control terminal, the second input terminal is connected to the precharge node, and the second output Terminals are connected to the gates of the eighth thin film transistor and the ninth thin film transistor; the gate of the eighth thin film transistor is connected to the gate of the ninth thin film transistor, the drain is connected to the low power supply voltage line, and the source is connected to the And a ninth thin film transistor whose gate is connected to the gate of the eighth thin film transistor, whose drain is connected to the low power supply voltage line, and whose source is connected to the precharge node.
  • the pull-down circuit unit may include a fourth thin film transistor whose gate is docked with the gate of the fifth thin film transistor and is configured to receive a scan driving signal from the lower two-stage GOA circuit unit, and a drain thereof is connected To the low power supply voltage line, the source of which is connected to the scanning drive line of this stage; the fifth thin film transistor whose gate is docked with the gate of the fourth thin film transistor and is configured to receive the scan drive from the next two levels of GOA circuit units The signal has its drain connected to the low supply voltage line and its source connected to the precharge node.
  • the pull-up circuit unit may include a second thin film transistor, a drain of which is connected to the pass-through circuit unit and configured to receive the first clock signal or the second clock signal, and a gate of which is connected to the precharge node. , Its source is connected to the scan drive line of this stage to output the scan drive signal.
  • the downstream circuit unit may include a third thin film transistor whose drain is connected to the pull-up circuit unit and is configured to receive the first clock signal or the second clock signal, and a gate thereof is connected to the precharge node. , Its source is connected to the stage signal line to output stage signal.
  • Another aspect of the present invention provides a method for driving a liquid crystal panel including a GOA circuit, the GOA circuit including a plurality of cascaded single-stage GOA circuit units, wherein each single-stage GOA circuit unit includes a pull-up control circuit unit , A pull-up circuit unit, a pull-down circuit unit, a bootstrap capacitor, a download circuit unit, a first pull-down sustain circuit unit, and a second pull-down sustain circuit unit, the method includes: The control terminal inputs the first clock signal, and inputs the second clock signal to the second control terminal of the second pull-down maintaining circuit unit, and alternately inputs the first clock signal and the pull-up circuit unit in the GOA circuit unit of the adjacent two stages.
  • the second clock signal during the scan output period, the pull-up circuit unit outputs the first clock signal or the second clock signal to the scan drive line of the current stage to output the scan drive signal; during the reset period, input from the next two to the pull-down circuit unit Level driving signal of the GOA circuit unit to reset the potentials of the pre-charge node and the scanning driving signal;
  • the pull-maintenance circuit unit and the second pull-down sustain circuit unit work alternately to maintain the low potential of the scan drive signal and the precharge node, wherein the first clock signal and the second clock signal have a period of the same length, where the second clock signal is opposite
  • the first clock signal is delayed so that the second clock signal has a high potential in the first period and the third period in each high potential period of the first clock signal, and the second period between the first period and the third period is high.
  • the period has a low potential.
  • the first period may be an initial period of the first clock signal and an end period of a previous high-potential period of the second clock signal
  • the second period may be an intermediate period of the first clock signal and the second clock signal
  • the third period may be an end period of the first clock signal and an initial period of a subsequent high potential period of the second clock signal.
  • the duty ratio of each of the first clock signal and the second clock signal may be 60/40.
  • the first period and the third period may each account for 10% of each period.
  • FIG. 1 is a schematic diagram of a single-stage GOA circuit unit in the prior art
  • FIG. 2 is a circuit diagram of a Darlington inverter included in the pull-down sustaining circuit unit of FIG. 1;
  • FIG. 3 is a schematic diagram of a single-stage GOA circuit unit in the prior art
  • FIG. 5 is a waveform diagram of control signals of two pull-down sustaining circuit units in FIG. 3;
  • FIG. 6 is a schematic diagram of a single-stage GOA circuit unit according to an exemplary embodiment of the present invention.
  • FIG. 7 is a waveform diagram of a clock signal according to an exemplary embodiment of the present invention.
  • FIG. 8 is a signal waveform diagram of the single-stage GOA circuit unit of FIG. 6.
  • a GOA circuit may include a plurality of thin film transistors.
  • FIG. 4 is an equivalent circuit diagram of a thin film transistor.
  • the three electrodes of the thin film transistor are called a gate, a source, and a drain, respectively.
  • the voltages applied to the electrodes can be labeled as Vg, Vs, and Vd, respectively.
  • the lower voltage end is usually referred to as the source and the other higher voltage end is referred to as the drain. pole.
  • Vgs Vg-Vs.
  • Vgs>0 the thin-film transistor is in the on-state and the current flows from the drain Drain to the source Source.
  • Vgs 0, the thin-film transistor is micro-conductive In the on state, current flows from the drain Drain to the source Source; when Vgs ⁇ 0, the device is in the off state.
  • one end with a lower voltage may be referred to as a drain Drain, and the other end with a higher voltage may be referred to as a source. That is, when the thin film transistor is in an on state, the current From source to drain Drain.
  • FIG. 5 is a waveform diagram of the control signals LC1 and LC2 of the two pull-down sustaining circuit units 5-1 and 5-2 in FIG. 3. The principle of the alternate operation of the two pull-down sustaining circuit units 5-1 and 5-2 will be described below with reference to FIGS. 3 and 5.
  • the precharge node Q (N) is always at a low potential, that is, a thin film transistor T52, T54, T62 and T64 are all off.
  • the pull-down sustaining circuit unit 5-1 When the first control signal LC1 is at a high potential and the second control signal LC2 is at a low potential, the pull-down sustaining circuit unit 5-1 is in an operating state, and the thin film transistors T51 and T53 are turned on. At this time, the first node A is at a high potential, and the thin film transistors T32 and T42 are subjected to a positive bias stress PBS, that is, the thin film transistors T32 and T42 are turned on, so that the low power supply voltage VSS is transmitted to the The charging node Q (N) and the scanning drive line of the current stage maintain the low potentials of the pre-charging node Q (N) and the scanning drive signal G (N).
  • NBS Negative Bias Stress
  • the pull-down sustaining circuit unit 5-2 is in an operating state, and the thin film transistors T61 and T63 are turned on.
  • the second node B is at a high potential, and the thin film transistors T33 and T43 are subjected to a positive bias stress PBS.
  • the thin film transistors T33 and T43 are turned on, so that the low power supply voltage VSS is transmitted to the precharge node through the thin film transistors T43 and T33, respectively.
  • Q (N) and the current scan drive line to maintain the low potential of the precharge node Q (N) and the scan drive signal G (N).
  • the pull-down sustaining circuit units 5-1 and 5-2 work alternately to maintain the low potential of the precharge node Q (N) and the scan driving signal G (N).
  • the thin film transistors T32 and T42 are based on the first node
  • the potential change of A is affected by both PBS and NBS.
  • the thin film transistors T33 and T43 are affected by both PBS and NBS according to the potential change of the second node B, so that the device fails due to charge trapping. Can be relieved to a certain extent.
  • FIG. 6 is a schematic diagram of a single-stage GOA circuit unit according to an exemplary embodiment of the present invention.
  • FIG. 7 is a waveform diagram of a clock signal according to an exemplary embodiment of the present invention.
  • a GOA circuit of a liquid crystal panel including a GOA circuit includes a plurality of single-stage GOA circuit units cascaded, wherein each single-stage GOA circuit unit includes: a pull-up control The circuit unit 100, the pull-up circuit unit 200, the download circuit unit 300, the pull-down circuit unit 400, the bootstrap capacitor Cbt, the first pull-down sustain circuit unit 501, and the second pull-down sustain circuit unit 502.
  • a first control terminal of the first pull-down sustain circuit unit 501 is input with a first clock signal CK
  • a second control terminal of the second pull-down sustain circuit unit 502 is input with a first
  • the two clock signals XCK, the pull-down circuit unit 400 is input with the scan driving signals of the next two stages of the GOA circuit unit, and the first clock signal CK and the second clock signal XCK are alternately input to the pull-up circuit unit in the adjacent stage GOA circuit unit 200 and download circuit unit 300.
  • the first clock signal CK and the second clock signal XCK have a period of the same length, and the second clock signal XCK is delayed relative to the first clock signal CK, so that the second clock signal XCK is at each of the first clock signals CK.
  • the first period t1 'and the third period t3' in the high potential period have a high potential, and the second period t2 'between the first period t1' and the third period t3 'has a low potential.
  • each single-level GOA circuit unit of the liquid crystal panel may be driven by a first clock signal CK and a second clock signal XCK, that is, the first clock signal CK and the second clock signal XCK may be maintained instead of being pulled down.
  • the control signals LC1 and LC2 in the circuit unit can also meet the signal requirements of the pull-up circuit unit, which can reduce the number of signal lines and efficiently use the signal lines, thereby saving the space occupied by the wiring in the display panel.
  • N is a natural number greater than or equal to 1.
  • the other GOA circuit units have similar structures.
  • the thin film transistor included in the GOA circuit may be a high potential conducting thin film transistor, such as a high potential conducting amorphous silicon (a-Si) thin film transistor or an NMOS transistor.
  • a-Si high potential conducting amorphous silicon
  • the inventive concept is not limited to this.
  • the thin film transistor included in the GOA circuit may also be a thin film transistor that is turned on at a low potential, such as a PMOS thin film transistor.
  • a-Si amorphous silicon
  • the pull-up control circuit unit 100 may include: a first thin film transistor T11, a gate of which is input to a stage signal ST (N-1) of the previous stage GOA circuit unit, and a drain of which is The scan driving signal G (N-1) of the upper GOA circuit unit is input, and its source is connected to the precharge node Q (N).
  • the pull-up circuit unit 200 may include: a second thin film transistor T21, whose drain is input with the first clock signal CK or the second clock signal XCK, whose gate is connected to the precharge node Q (N), and whose source is connected to the The stage scans the drive lines to output a scan drive signal G (N).
  • the pull-up circuit unit 200 is mainly used to increase the potential of the scan driving signal G (N).
  • the downstream circuit unit 300 may include a third thin film transistor T22, the drain of which is input with the first clock signal CK or the second clock signal XCK (that is, the clock signal input with the drain of the second thin film transistor T22 of the current stage). Same), its gate is connected to the pre-charge node Q (N), and its source is connected to the stage transmission signal line of this stage to output the stage transmission signal ST (N).
  • the first clock signal CK and the second clock signal XCK are alternately input to the GOA circuit unit of the adjacent stage, that is, the first clock signal CK and the second clock signal
  • the clock signal XCK is alternately input to the pull-up circuit unit 200 and the download circuit unit 300 in the GOA circuit unit of the adjacent stage.
  • the pull-up circuit unit 200 and the download circuit unit 300 of the N-th stage GOA circuit unit are input with the first clock signal CK
  • the (N + 1) -th stage GOA circuit The pull-up circuit unit 200 and the download circuit unit 300 in the unit are input with the second clock signal XCK
  • the pull-up circuit unit 200 and the download circuit unit 300 in the (N + 2) th stage GOA circuit unit are input with the first clock
  • the signal CK, the pull-up circuit unit 200 and the download circuit unit 300 in the (N + 3) th stage GOA circuit unit are input with the second clock signal XCK, and so on.
  • the present inventive concept is not limited to this.
  • the pull-up circuit unit 200 and the download circuit unit 300 in the N-th GOA circuit unit may be input with the second clock signal XCK, the (N + 1
  • the pull-up circuit unit 200 and the downlink circuit unit 300 of the GOA circuit unit may be input with the first clock signal CK, and so on.
  • the pull-up circuit unit 200 and the downlink circuit unit 300 in the odd-numbered GOA circuit unit may be input with the first clock signal CK, and the pull-up circuit unit 200 and the downlink circuit in the even-numbered GOA circuit unit.
  • the unit 300 may be input with the second clock signal XCK, and vice versa.
  • the bootstrap capacitor Cbt takes advantage of the fact that the voltage across the capacitor cannot be abruptly changed. When a certain voltage is maintained across the capacitor, the voltage at the negative terminal of the capacitor is increased. The voltage at the positive terminal remains the same as the original voltage difference at the negative terminal. Lifted up. As shown in FIG. 6, one end of the bootstrap capacitor Cbt can be connected to the pre-charge node Q (N), and the other end can be connected to the scanning driving line of this stage.
  • the bootstrap capacitor Cbt is mainly used to maintain and increase the potential of the precharge node Q (N).
  • the pull-down circuit unit 400 may include a fourth thin film transistor T31 and a fifth thin-film transistor T41 whose gates are docked with each other, and a scan drive signal G (N + 1) -level GOA circuit unit is input to the pull-down circuit unit shown in FIG. 3 ( N + 1) Different, the gates of the fourth thin film transistor T31 and the fifth thin film transistor T41 can be input to the scan driving signal G (N + 2) of the next two stages (ie, the (N + 2) th stage) GOA circuit unit .
  • the drain of the fourth thin film transistor T31 may be connected to a low power supply voltage line, and the source thereof may be connected to a scan driving line of this stage.
  • the drain of the fifth thin film transistor T41 may be connected to a low power supply voltage line, and the source thereof may be connected to a precharge node Q (N).
  • the pull-down circuit unit 400 is mainly used to pull down the potentials of the precharge node Q (N) and the scan driving signal G (N) to a low power supply voltage VSS.
  • the inverter included in the pull-down sustaining circuit unit may be a Darlington inverter, which may have a structure as shown in FIG. 2, but the inventive concept is not limited thereto.
  • a Darlington inverter will be described as an example in the following description.
  • the first pull-down maintaining circuit unit 501 may include a first inverter having a first input terminal Input, a first output terminal Output (corresponding to the first node A), and a first control terminal, where the first The input terminal Input can be connected to the precharge node Q (N), and the first output terminal Output can be connected to the gates of the sixth thin film transistor T32 and the seventh thin film transistor T42; the sixth thin film transistor T32 can be connected to the gate
  • the gate of the seventh thin film transistor T42 can have its drain connected to the low power supply voltage line VSS, and its source can be connected to the scanning drive line of this stage; the gate of the seventh thin film transistor T42 can be connected to the sixth thin film transistor T32
  • the gate and the drain thereof can be connected to the low power voltage line VSS, and the source can be connected to the precharge node Q (N).
  • the second pull-down maintaining circuit unit 502 may include a second inverter having a second input terminal Input, a second output terminal Output (corresponding to the first node B), and a second control terminal, wherein the second input terminal Input can be connected to the pre-charge node, and the second output terminal Output can be connected to the gate of the eighth thin film transistor T33 and the ninth thin film transistor; the gate of the eighth thin film transistor T33 can be connected to the gate of the ninth thin film transistor T43.
  • Its drain can be connected to the low power voltage line VSS, and its source can be connected to the scanning drive line of this stage; its ninth thin film transistor T43, its gate can be connected to the gate of the eighth thin film transistor T33, and its drain
  • the pole can be connected to the low power supply voltage line VSS, and its source can be connected to the precharge node Q (N).
  • the second pull-down sustaining circuit unit 502 may have a circuit structure substantially the same as that of the first pull-down sustaining circuit unit 501.
  • the pull-down sustaining circuit units 501 and 502 are mainly used to maintain the potentials of the precharge node Q (N) and the scan driving signal G (N) at a low power supply voltage VSS.
  • FIG. 7 is a waveform diagram of a clock signal according to an exemplary embodiment of the present invention.
  • the first clock signal CK and the second clock signal XCK have a period of the same length. Taking one period as an example, one period of each of the first clock signal CK and the second clock signal XCK may include a first period t1 ', a second period t2', a third period t3 ', and a fourth period t4'.
  • the first clock signal CK and the second clock signal XCK may be square-wave pulse signals, and each period thereof may be composed of a high-potential period and a low-potential period.
  • the second clock signal XCK is delayed relative to the first clock signal CK, so that the second clock signal XCK is in the first period t1 ′ and the first period in each high potential period of the first clock signal CK.
  • the three periods t3 ' have a high potential, and the second period t2' between the first period t1 'and the third period t3' has a low potential.
  • the first period t1 ′ may be an initial period of the first clock signal CK and an end of a previous high potential period of the second clock signal XCK.
  • the second period t2 ′ may be an intermediate period of the first clock signal CK and a low-potential period of the second clock signal XCK
  • the third period t3 ′ may be an end period of the first clock signal CK and a period of the second clock signal XCK The initial period of the next high potential period.
  • the high potential time of the first clock signal CK and the second clock signal XCK may occupy 60% of one cycle, and the low potential time may occupy 40% of one cycle. That is, the duty ratio of each of the first clock signal CK and the second clock signal XCK may be 60/40.
  • the first period t1 'and the third period t3' may be spaced apart from each other, and each may account for 10% of each period.
  • the second period t2 'and the fourth period t4' may each occupy 40% of one period.
  • the first clock signal CK and the second clock signal XCK may be completely inverted during the second period t2 'and the fourth period t4'.
  • the duty cycle (ie, the ratio of the high potential time to the low potential time) of the high and low potentials of the first clock signal CK and the second clock signal XCK may be other ratios, For example, 50/50, 70/30, 80/20, etc .; the first period t1 'and the third period t3' each occupy a cycle time may also be other proportions, such as 5%, 20%, and so on.
  • the precharge node Q (N) when the precharge node Q (N) is at a high potential (not shown), according to the principle of the Darlington inverter, the first output terminal of the first inverter (that is, the first node A ) And the second output terminal of the second inverter (that is, the second node B) are both at a low potential, and the thin film transistors T32, T42, T33, and T43 are all turned off. At this time, the pull-down maintenance circuit units 501 and 502 do not work. . However, during the low-potential maintenance stage, the pre-charge node Q (N) is at a low potential, and the thin film transistors T52, T54, T62, and T64 are all turned off. At this time, the pull-down sustaining circuit units 501 and 502 alternately work to maintain the scan driving signal G ( N) low potential. The principle of alternate operation will be described below with reference to FIGS. 6 and 7.
  • the first clock signal CK is at a high potential
  • the second clock signal XCK is also at a high potential.
  • the first node A that is the first output terminal of the first inverter and the second node B that is the second output terminal of the second inverter are both at a high potential, and the thin film transistors T32, T42, T33, and T43 are all turned on.
  • the first pull-down sustaining circuit unit 501 and the second pull-down sustaining circuit unit 502 are both in an operating state, and the low power supply voltage VSS can be transmitted to the pre-charge node Q (N) and the scanning drive line of this stage to maintain the pre-charge node Q, respectively. (N) and the low potential of the scan drive signal G (N).
  • the first clock signal CK is still at a high potential, and the second clock signal XCK is transitioned to a low potential.
  • the first node A as the first output terminal of the first inverter may be at a high potential
  • the thin film transistors T32 and T42 are turned on
  • the first pull-down sustaining circuit unit 501 may be in an operating state
  • the low power supply voltage VSS may be respectively It is transmitted to the precharge node Q (N) and the scanning drive line of this stage to maintain the low potential of the precharge node Q (N) and the scan drive signal G (N).
  • the second node B which is the second output terminal of the second inverter, is at a low potential at this time, the thin film transistors T33 and T43 are turned off, and the second pull-down sustaining circuit unit 502 does not operate.
  • the first clock signal CK is still high and the second clock signal XCK is changed to high.
  • the first node A that is the first output terminal of the first inverter and the second node B that is the second output terminal of the second inverter are both at a high potential, and the thin film transistors T32, T42, T33, and T43 are all turned on.
  • the first pull-down sustaining circuit unit 501 and the second pull-down sustaining circuit unit 502 are both in an operating state, and the low power supply voltage VSS can be transmitted to the pre-charge node Q (N) and the scanning drive line of this level to maintain the pre-charge node Q (N) and the low potential of the scan drive signal G (N).
  • the first clock signal CK transitions to a low potential, and the second clock signal XCK remains at a high potential.
  • the first node A serving as the first output terminal of the first inverter may be at a low potential, the thin film transistors T32 and T42 are turned off, and the first pull-down sustaining circuit unit 501 is not operated;
  • the second node B of the two output terminals is now at a high potential, the thin film transistors T33 and T43 are turned on, and the second pull-down sustaining circuit unit 502 is in an operating state.
  • the low power supply voltage VSS can be transmitted to the precharge node Q (N) and the The scanning drive lines are staged to maintain the low potential of the precharge node Q (N) and the scan drive signal G (N).
  • the fully inverted control signals LC1 and LC2 shown in FIG. 5 are usually used.
  • the control signals LC1 and LC2 belong to High-frequency AC signals will experience signal delays under the action of resistors and capacitors, that is, the signal will have a certain degree of gradual change, which may cause the scanning drive signal G (N) to be intermittent or the potential to be unstable.
  • the clock signals CK and XCK are set to have the same period of time (ie, the first period t1 ′ and the third period t3 ′), for example, referring to FIG.
  • the first pull-down maintaining unit 501 starts to enter the working state;
  • the second pull-down maintenance unit 502 starts to enter the working state, thereby ensuring that the pull-down maintenance units 501 and 502 normally work alternately, and stably maintains the precharge node Q (N) and the scan driving signal G ( N) without a discontinuity or potential instability in the scan driving signal G (N).
  • the pull-down circuit unit 400 of the single-stage GOA circuit unit of FIG. 6 is input to the next two-stage GOA circuit unit.
  • the scanning driving signal G (N + 2) makes it possible to better maintain the stability of the scanning driving signal G (N). This case will be described below with reference to FIGS. 6 and 8.
  • FIG. 8 is a signal waveform diagram of the single-stage GOA circuit unit of FIG. 6.
  • FIG. 8 shows the clock signals CK and XCK shown in FIG. 7, the scan output signal G (N) of the Nth stage GOA circuit unit, and the scan output signal G (N + 1) of the N + 1th stage GOA circuit unit. And the scan output signal G (N + 2) of the N + 2 stage GOA circuit unit.
  • the second clock is input to the pull-up circuit unit 200 in the (N + 1) -th GOA circuit unit.
  • Signal XCK and input the first clock signal CK to the pull-up circuit unit 200 in the (N + 2) th stage GOA circuit unit, and so on.
  • the scan output signal G (N) of the Nth stage GOA circuit unit corresponds to the first clock signal CK
  • the scan output signal G (N + 2) of the N + 2 stage GOA circuit unit corresponds to the first clock signal CK.
  • the scan driving signal G (N + 1) of the next-level GOA circuit unit is usually input to the pull-down circuit unit 400, but this driving method will cause the scan output signal G (N) is unstable. Specifically, during the scan output period t1-t3, the precharge node Q (N) is at a high potential (not shown), the second thin film transistor T21 is turned on, and the scan output signal G (N) of the N-th GOA circuit unit is turned on.
  • the fourth thin film transistor T31 is turned on, so that the low power supply voltage VSS pulls the scan output signal G (N) of the N-th GOA circuit unit to a low potential via the fourth thin film transistor T31. It can be seen that during the period of t3, the second thin film transistor T21 and the fourth thin film transistor T31 are both turned on.
  • the scan driving line of the N-th GOA circuit unit is simultaneously input with the high-level first clock signal CK and low
  • the potential of the low power supply voltage VSS, the simultaneous competition of the high potential and the low potential causes the scan output signal G (N) to be unstable.
  • the pull-down circuit unit 400 is input from the next two stages (ie, the (N + 2) th stage) GOA circuit Scanning drive signal G (N + 2) of the unit.
  • This driving method can effectively avoid the above-mentioned "simultaneous competition between high and low potentials". Specifically, during the scan output period t1-t4, the precharge node Q (N) is at a high potential (not shown), the second thin film transistor T21 is turned on, and the scan output signal G (N) of the N-th GOA circuit unit is turned on.
  • the scan output signal G (N + 2) of the N + 2 stage GOA circuit unit is high potential, and its transmission
  • the fourth thin film transistor T31 is turned on, so that the low power supply voltage VSS pulls the scan output signal G (N) of the N-th GOA circuit unit low through the fourth thin film transistor T31.
  • the low power supply voltage VSS pulls the scan output signal G (N) of the N-th GOA circuit unit low through the fourth thin film transistor T31.
  • the scan output period t1-t4 and the reset period t5-t6 are not overlapped, and a situation in which a high potential and a low potential are simultaneously input to the scan driving line of the N-th GOA circuit unit will not occur.
  • the pull-down sustaining circuit units 501 and 502 alternately operate to maintain the precharge node Q (N) and the scan driving signal G ( N) The low potential will not be described repeatedly.
  • a method of driving a liquid crystal panel including a GOA circuit is provided.
  • a GOA circuit of a liquid crystal panel including a GOA circuit includes a plurality of single-stage GOA circuit units cascaded, wherein each single-stage GOA circuit unit may include a pull-up control circuit unit 100.
  • the method includes: inputting a first clock signal CK to a first control terminal of the first pull-down sustaining circuit unit 501, and inputting a first control signal to the second control terminal of the second pull-down sustaining circuit unit 502.
  • the pull-up circuit unit 200 outputs the first clock signal CK or the second clock signal XCK to the scanning driving line of this stage to output the scanning driving signal G (N); during the reset period (for example, the period t5-t6), it pulls down
  • the circuit unit 400 inputs the scan driving signal G (N + 2) from the next two stages of the GOA circuit unit to reset the potentials of the pre-charge node Q (N) and the scan driving signal G (N); , During a period after period t6), the first pull-down sustaining circuit unit 501 and the second pull-down sustaining circuit unit 502 work alternately to maintain the low potentials of the scan driving signal G (N) and the precharge node Q (N).
  • each single-stage GOA circuit of a liquid crystal panel including a GOA circuit according to an exemplary embodiment of the present invention is input with a new set of clock signals CK and XCK, and the set of clock signals can both satisfy the pull-up circuit unit It can also replace the control signal in the pull-down maintenance circuit unit, thereby efficiently using the clock signal line and effectively saving the space occupied by the wiring in the display panel.
  • the exemplary embodiment of the present invention includes a GOA circuit
  • the LCD panel also improves the input control signal of the pull-down circuit unit 400, further improving the stability of the scan output signal, and providing a new possibility for the design of the future GOA circuit.
  • the liquid crystal panel according to the exemplary embodiment of the present invention may further include various elements common in the art such as a polarizer, a filter, a liquid crystal layer, and a backlight module, which are not described in detail here.

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Abstract

一种包括GOA电路的液晶面板及其驱动方法。GOA电路包括级联的多个单级GOA电路单元，每个单级GOA电路单元包括第一下拉维持电路单元（501）和第二下拉维持电路单元（502）。第一下拉维持电路单元（501）的第一控制端被输入第一时钟信号（CK），第二下拉维持电路单元（502）的第二控制端被输入第二时钟信号（XCK），下拉电路单元（400）被输入下两级GOA电路单元的扫描驱动信号（G（N+2））。第一时钟信号（CK）和第二时钟信号（XCK）交替地输入到相邻级的GOA电路单元中的上拉电路单元（200）和下传电路单元（300）。第一时钟信号（CK）与第二时钟信号（XCK）具有相同长度的周期。第二时钟信号（XCK）相对于第一时钟信号（CK）延迟，使得第二时钟信号（XCK）在第一时钟信号（CK）的每个高电位周期内的第一时段（t1'，t1）和第三时段（t3'，t3）具有高电位，并且在第一时段（t1'，t1）与第三时段（t3'，t3）之间的第二时段（t2'，t2）具有低电位。

Description

包括GOA电路的液晶面板及其驱动方法 技术领域
本发明涉及显示技术领域，更具体地讲，涉及一种包括GOA(Gate Driver OnArray，阵列基板行驱动)电路的液晶面板及其驱动方法。
背景技术
液晶显示器具有低辐射、体积小及低耗能等优点，已经被广泛地应用于笔记本电脑、个人数字助理PDA、平面电视或移动电话等产品上。传统液晶显示器的方式是利用外部驱动芯片来驱动面板上的芯片以显示图像，但为了减少元件数目并降低制造成本，近年来逐渐发展成将驱动电路结构直接制作于显示面板上，例如采用GOA技术。
GOA技术是将TFT LCD(Thin Film Transistor Liquid Crystal Display，薄膜晶体管液晶显示器)的栅极驱动电路集成在玻璃基板上，形成对液晶面板的扫描驱动。GOA技术相比传统的利用COF(Chip On Flex/Film，覆晶薄膜)的驱动技术可以大幅度节约制造成本，而且省去了Gate侧COF的Bonding制程，对产能提升也是极为有利的。因此，GOA是未来液晶面板发展的重点技术。
现有的GOA电路通常包括级联的多个单级GOA电路单元，每个单级GOA电路单元均与相应级的扫描驱动线对应。例如，如图1所示，单级GOA电路单元包括：上拉控制电路单元①、上拉电路单元②、下传电路单元③、下拉电路单元④、下拉维持电路单元⑤以及自举电容⑥。参照图1，上拉控制电路单元①主要为预充电节点Q(N)实现预充电，通常被输入上一级GOA电路单元传递过来的下传信号ST(N-1)和扫描驱动信号G(N-1)；上拉电路单元②主要为提高扫描驱动信号G(N)的电位；信号下传单元③包括薄膜晶体管，其主要通过输出本级的下传信号ST(N)来控制下一级GOA电路单元中的上拉控制电路单元的打开和关闭；下拉电路单元④主要用于拉低预充电节点Q(N)和扫描驱动信号G(N)的电位至低电源电压VSS；下拉维持电路单元⑤可以包括反相器和多个薄膜晶体管，其主要用于将预充电节点Q(N)、扫描驱动信号G(N)的电位 维持在低电源电压VSS不变；自举电容⑥主要为提供并维持预充电节点Q(N)电位，这样有利于上拉电路单元②输出扫描驱动信号G(N)。
下拉维持电路单元⑤的反相器可以采用达灵顿反相器，其具体的电路结构如图2所示，达灵顿反相器可以包括四个薄膜晶体管并且可以具有输入端Input和输出端Output。如果将控制信号LC设置成始终为高电位信号并且将低电源电压VSS设置成始终为低电位信号，则当输入端Input输入高电位信号时，输出端Output输出低电位信号；当输入端Input输入低电位信号时，输出端Output输出高电位信号。
以向GOA电路输入2个时钟信号CK和XCK为例，当下拉维持电路单元⑤包括达灵顿反相器时，单级GOA电路单元如图3所示。通常情况下会设置两个下拉维持电路单元⑤-1和⑤-2根据图5所示的波形交替工作，防止薄膜晶体管T32、T42、T33、T43长时间受到正偏压应力(Positive Bias Stress，PBS)而使薄膜晶体管的阈值电压Vth正向漂移严重导致器件失效。
然而，在现有技术中，仍然以向GOA电路输入2个时钟信号CK和XCK为例，采用GOA技术的液晶面板通常包含如下信号的走线：阵列基板上的共电极信号Acom、彩模基板上的共电极信号CFcom、控制信号LC1和LC2、启动信号STV、低电源电压VSS、时钟信号CK和XCK。随着越来越多的功能结构被增加到电路中，GOA电路所占的空间也越来越大，这对于窄边框液晶面板的设计是极为不利的。因此，如何减少信号线的数目、如何高效利用信号线对于未来液晶面板的发展是极为重要的。
发明内容
本发明的示例性实施例在于提供一种包括GOA电路的液晶面板及其驱动方法。该GOA电路被输入一组新设计的时钟信号，该组时钟信号可以满足上拉电路单元的信号要求，也可以替代下拉维持电路单元中的控制信号，从而高效利用了时钟信号线且有效节省了显示面板中布线所占的空间，为未来GOA电路的设计提供了一种新的可能。
本发明的一方面提供一种包括GOA电路的液晶面板，所述GOA电路包括级联的多个单级GOA电路单元，其中，每个单级GOA电路单元包括上拉控制电路单元、上拉电路单元、下拉电路单元、自举电容、下传电路单元、第 一下拉维持电路单元以及第二下拉维持电路单元，其中，在每个单级GOA电路单元中，第一下拉维持电路单元的第一控制端被构造为接收第一时钟信号，第二下拉维持电路单元的第二控制端被构造为接收第二时钟信号，下拉电路单元被构造为接收来自下两级GOA电路单元的扫描驱动信号，其中，相邻两级的GOA电路单元中的上拉电路单元被构造为交替地接收第一时钟信号和第二时钟信号，其中，第一时钟信号与第二时钟信号具有相同长度的周期，其中，第二时钟信号相对于第一时钟信号延迟，使得第二时钟信号在第一时钟信号的每个高电位周期内的第一时段和第三时段具有高电位，并且在第一时段与第三时段之间的第二时段具有低电位。
根据示例性实施例，第一下拉维持电路单元可以包括：第一反相器，具有第一输入端、第一输出端和第一控制端，第一输入端连接到预充电节点，第一输出端连接到第六薄膜晶体管和第七薄膜晶体管的栅极；第六薄膜晶体管，其栅极连接到第七薄膜晶体管的栅极，其漏极连接到低电源电压线，其源极连接到本级的扫描驱动线；以及第七薄膜晶体管，其栅极连接到第六薄膜晶体管的栅极，其漏极连接到低电源电压线，其源极连接到预充电节点。
根据示例性实施例，第二下拉维持电路单元可以包括：第二反相器，具有第二输入端、第二输出端和第二控制端，第二输入端连接到预充电节点，第二输出端连接到第八薄膜晶体管和第九薄膜晶体管的栅极；第八薄膜晶体管，其栅极连接到第九薄膜晶体管的栅极，其漏极连接到低电源电压线，其源极连接到本级的扫描驱动线；以及第九薄膜晶体管，其栅极连接到第八薄膜晶体管的栅极，其漏极连接到低电源电压线，其源极连接到预充电节点。
根据示例性实施例，下拉电路单元可以包括：第四薄膜晶体管，其栅极与第五薄膜晶体管的栅极对接并且被构造为接收来自下两级GOA电路单元的扫描驱动信号，其漏极连接到低电源电压线，其源极连接到本级的扫描驱动线；第五薄膜晶体管，其栅极与第四薄膜晶体管的栅极对接并且被构造为接收来自下两级GOA电路单元的扫描驱动信号，其漏极连接到低电源电压线，其源极连接到预充电节点。
根据示例性实施例，上拉电路单元可以包括：第二薄膜晶体管，其漏极连接到下传电路单元并且被构造为接收第一时钟信号或第二时钟信号，其栅极连接到预充电节点，其源极连接到本级的扫描驱动线以输出扫描驱动信号。
根据示例性实施例，下传电路单元可以包括：第三薄膜晶体管，其漏极连接到上拉电路单元并且被构造为接收第一时钟信号或第二时钟信号，其栅极连接到预充电节点，其源极连接到本级的级传信号线以输出级传信号。
本发明的另一方面提供一种驱动包括GOA电路的液晶面板的方法，所述GOA电路包括级联的多个单级GOA电路单元，其中，每个单级GOA电路单元包括上拉控制电路单元、上拉电路单元、下拉电路单元、自举电容、下传电路单元、第一下拉维持电路单元以及第二下拉维持电路单元，所述方法包括：向第一下拉维持电路单元的第一控制端输入第一时钟信号，并且向第二下拉维持电路单元的第二控制端输入第二时钟信号，向相邻两级的GOA电路单元中的上拉电路单元交替地输入第一时钟信号和第二时钟信号；在扫描输出时段，上拉电路单元将第一时钟信号或第二时钟信号输出到本级的扫描驱动线以输出扫描驱动信号；在复位时段，向下拉电路单元输入来自下两级GOA电路单元的扫描驱动信号以对预充电节点和扫描驱动信号的电位进行复位；在低电位维持阶段，第一下拉维持电路单元和第二下拉维持电路单元交替工作以维持扫描驱动信号和预充电节点的低电位，其中，第一时钟信号与第二时钟信号具有相同长度的周期，其中，第二时钟信号相对于第一时钟信号延迟，使得第二时钟信号在第一时钟信号的每个高电位周期内的第一时段和第三时段具有高电位，并且在第一时段与第三时段之间的第二时段具有低电位。
根据示例性实施例，第一时段可以为第一时钟信号的初始时段和第二时钟信号的前一高电位周期的结束时段，第二时段可以为第一时钟信号的中间时段和第二时钟信号的低电位时段，第三时段可以为第一时钟信号的结束时段和第二时钟信号的后一高电位周期的初始时段。
根据示例性实施例，第一时钟信号和第二时钟信号中的每个的占空比可以为60/40。
根据示例性实施例，第一时段和第三时段可以各自占每个周期的10％。
附图说明
通过下面结合附图进行的对实施例的描述，本发明的上述和/或其它目的和优点将会变得更加清楚，其中：
图1是现有技术中单级GOA电路单元的示意图；
图2是图1的下拉维持电路单元中包括的达灵顿反相器的电路图；
图3是现有技术的单级GOA电路单元的示意图；
图4是薄膜晶体管的等效电路图；
图5是图3中的两个下拉维持电路单元的控制信号的波形图；
图6是根据本发明的示例性实施例的单级GOA电路单元的示意图；
图7是根据本发明的示例性实施例的时钟信号的波形图；
图8是图6的单级GOA电路单元的信号波形图。
具体实施方式
现在将参照附图更详细地描述本公开的一个或更多个示例性实施例。可以使用相同的附图标记来表示相同或相应的组件并且省略重复的解释。
在此使用的术语仅出于描述特定的示例实施例的目的，而并不意图限制发明构思。如在这里使用的，除非上下文另外清楚地指出，否则单数形式的“一个(种/者)”和“该(所述)”也意图包括复数形式。也将理解，当术语“包含”和“包括”在本说明书中使用时，说明存在所述的特征、整体、步骤、操作、构件、元件和/或它们的组，但是不排除存在或者附加一个或更多个其他特征、整体、步骤、操作、构件、元件和/或它们的组。
为了便于之后的理解，首先对基本元件进行说明。根据本发明的示例实施例的GOA电路可包括多个薄膜晶体管。图4是薄膜晶体管的等效电路图，薄膜晶体管的三个电极分别称为栅极Gate、源极Source和漏极Drain，相应地，加载在各个电极上的电压可以分别标记为Vg、Vs和Vd。在这里，源极Source和漏极Drain实际上是没有区别的，但是为了方便说明，在示例性实施例中通常将电压较低的一端称为源极，将电压较高的另一端称为漏极。因此，决定薄膜晶体管的导通状态的电压Vgs＝Vg-Vs，当Vgs>0时，薄膜晶体管为导通状态，电流从漏极Drain流向源极Source；当Vgs＝0，薄膜晶体管为微导通状态，电流从漏极Drain流向源极Source；当Vgs<0时器件处于截止状态。可选择地，在其他示例性实施例中，也可以将电压较低的一端称为漏极Drain，将电压较高的另一端称为源极Source，即，当薄膜晶体管处于导通状态，电流从源极Source流向漏极Drain。
图5是图3中的两个下拉维持电路单元⑤-1和⑤-2的控制信号LC1和LC2的波形图。以下参照图3和图5说明两个下拉维持电路单元⑤-1和⑤-2交替工作的原理。
以第N级GOA电路单元为例，在将扫描驱动信号G(N)维持为低电位的时段(即，低电位维持阶段)，预充电节点Q(N)始终处于低电位，即，薄膜晶体管T52、T54、T62和T64均截止。
当第一控制信号LC1为高电位且第二控制信号LC2为低电位时，下拉维持电路单元⑤-1处于工作状态，薄膜晶体管T51、T53导通。此时，第一节点A处于高电位，薄膜晶体管T32、T42受到正偏压应力PBS的作用，即，薄膜晶体管T32、T42导通，从而低电源电压VSS分别经由薄膜晶体管T42和T32传输到预充电节点Q(N)和本级扫描驱动线，以维持预充电节点Q(N)和扫描驱动信号G(N)的低电位。然而，此时下拉维持电路单元⑤-2相应地处于非工作状态，薄膜晶体管T61、T63处于微导通状态(即，Vgs＝0)，第二节点B处于低电位，薄膜晶体管T33、T43受到负偏压应力(Negative Bias Stress，NBS)的作用，即，薄膜晶体管T33、T43截止。
同理，当第一控制信号LC1为低电位且第二控制信号LC2为高电位时，下拉维持电路单元⑤-2处于工作状态，薄膜晶体管T61、T63导通。此时，第二节点B处于高电位，薄膜晶体管T33、T43受到正偏压应力PBS的作用，薄膜晶体管T33、T43导通，从而低电源电压VSS分别经由薄膜晶体管T43和T33传输到预充电节点Q(N)和本级扫描驱动线，以维持预充电节点Q(N)和扫描驱动信号G(N)的低电位。然而，此时下拉维持电路单元⑤-1相应地处于非工作状态，薄膜晶体管T51、T53处于微导通状态(即，Vgs＝0)，第一节点A处于低电位，薄膜晶体管T32、T42受到负偏压应力PBS的作用，即，薄膜晶体管T33、T43截止。
因此，在一段时间内，下拉维持电路单元⑤-1和⑤-2交替工作以维持预充电节点Q(N)和扫描驱动信号G(N)的低电位，薄膜晶体管T32和T42根据第一节点A的电位变化既受到PBS的作用也受到NBS的作用，同样地，薄膜晶体管T33和T43根据第二节点B的电位变化既受到PBS的作用也受到NBS的作用，这样由于电荷俘获导致的器件失效就可以在一定程度上得到缓解。
图6是根据本发明的示例性实施例的单级GOA电路单元的示意图。图7是根据本发明的示例性实施例的时钟信号的波形图。
如图6所示，根据本发明的示例性实施例的包括GOA电路的液晶面板的GOA电路包括级联的多个单级GOA电路单元，其中，每个单级GOA电路单元包括：上拉控制电路单元100、上拉电路单元200、下传电路单元300、下拉电路单元400、自举电容Cbt、第一下拉维持电路单元501和第二下拉维持电路单元502。
参照图6，在每个单级GOA电路单元中，第一下拉维持电路单元501的第一控制端被输入第一时钟信号CK，第二下拉维持电路单元502的第二控制端被输入第二时钟信号XCK，下拉电路单元400被输入下两级GOA电路单元的扫描驱动信号，第一时钟信号CK和第二时钟信号XCK交替地输入到相邻级的GOA电路单元中的上拉电路单元200和下传电路单元300。参照图7，第一时钟信号CK与第二时钟信号XCK具有相同长度的周期，第二时钟信号XCK相对于第一时钟信号CK延迟，使得第二时钟信号XCK在第一时钟信号CK的每个高电位周期内的第一时段t1’和第三时段t3’具有高电位，并且在第一时段t1’与第三时段t3’之间的第二时段t2’具有低电位。
根据本发明的示例性实施例，液晶面板的每个单级GOA电路单元可由第一时钟信号CK和第二时钟信号XCK驱动，即，第一时钟信号CK和第二时钟信号XCK可以代替下拉维持电路单元中的控制信号LC1和LC2，而且可以满足上拉电路单元的信号要求，可减少信号线的数量并高效利用信号线，从而节省了显示面板中布线所占的空间。
以下将参照图6，以第N(N为大于或等于1的自然数)级GOA电路单元的结构为例进行详细说明，其他级GOA电路单元具有类似的结构。
在本发明的示例性实施例中，GOA电路中包括的薄膜晶体管可以为高电位导通的薄膜晶体管，例如，高电位导通的非晶硅(a-Si)薄膜晶体管或NMOS晶体管。但发明构思不限于此，在其他示例性实施例中，GOA电路中包括的薄膜晶体管也可以为低电位导通的薄膜晶体管，诸如PMOS薄膜晶体管。为了便于说明，在下文中将以所有的薄膜晶体管均为高电位导通的NMOS晶体管为例展开描述。
在第N级GOA电路单元中，上拉控制电路单元100可以包括：第一薄膜晶体管T11，其栅极被输入上一级GOA电路单元的级传信号ST(N-1)，其漏极被输入上一级GOA电路单元的扫描驱动信号G(N-1)，其源极连接到预充电节点Q(N)。
上拉电路单元200可以包括：第二薄膜晶体管T21，其漏极被输入第一时钟信号CK或第二时钟信号XCK，其栅极连接到预充电节点Q(N)，其源极连接到本级的扫描驱动线以输出扫描驱动信号G(N)。上拉电路单元200主要用于提高扫描驱动信号G(N)的电位。
下传电路单元300可以包括：第三薄膜晶体管T22，其漏极被输入第一时钟信号CK或第二时钟信号XCK(即，与本级的第二薄膜晶体管T22的漏极被输入的时钟信号相同)，其栅极连接到预充电节点Q(N)，其源极连接到本级的级传信号线以输出级传信号ST(N)。
以在GOA电路中使用两个时钟信号CK和XCK为例，第一时钟信号CK和第二时钟信号XCK交替地输入到相邻级的GOA电路单元中，即，第一时钟信号CK和第二时钟信号XCK交替地输入到相邻级的GOA电路单元中的上拉电路单元200和下传电路单元300。具体地，根据本发明的示例性实施例，当第N级GOA电路单元中的上拉电路单元200和下传电路单元300被输入第一时钟信号CK时，第(N+1)级GOA电路单元中的上拉电路单元200和下传电路单元300被输入第二时钟信号XCK，第(N+2)级GOA电路单元中的上拉电路单元200和下传电路单元300被输入第一时钟信号CK，第(N+3)级GOA电路单元中的上拉电路单元200和下传电路单元300被输入第二时钟信号XCK，以此类推。然而，本发明构思不限于此，在其他示例性实施例中，第N级GOA电路单元中的上拉电路单元200和下传电路单元300可以被输入第二时钟信号XCK，第(N+1)级GOA电路单元中的上拉电路单元200和下传电路单元300可以被输入第一时钟信号CK，以此类推。换个角度来说，例如，奇数级GOA电路单元中的上拉电路单元200和下传电路单元300可以被输入第一时钟信号CK，偶数级GOA电路单元中的上拉电路单元200和下传电路单元300可以被输入第二时钟信号XCK，反之亦可。
自举电容Cbt是利用了电容两端电压不能突变的特性，当电容两端保持有一定电压时，提高电容负端电压，正端电压仍保持与负端的原始压差，等于正 端的电压被负端举起来了。如图6所示，自举电容Cbt的一端可以连接到预充电节点Q(N)，另一端可以连接到本级的扫描驱动线。自举电容Cbt主要用于维持并提高预充电节点Q(N)的电位。
下拉电路单元400可以包括其栅极彼此对接的第四薄膜晶体管T31和第五薄膜晶体管T41，并且与图3所示的下拉电路单元被输入第N+1级GOA电路单元的扫描驱动信号G(N+1)不同，第四薄膜晶体管T31和第五薄膜晶体管T41的栅极可以被输入下两级(即，第(N+2)级)GOA电路单元的扫描驱动信号G(N+2)。第四薄膜晶体管T31的漏极可以连接到低电源电压线，其源极可以连接到本级的扫描驱动线。另外，第五薄膜晶体管T41的漏极可以连接到低电源电压线，其源极可以连接到预充电节点Q(N)。下拉电路单元400主要用于拉低预充电节点Q(N)和扫描驱动信号G(N)的电位至低电源电压VSS。
在本发明的示例性实施例中，下拉维持电路单元所包括的反相器可以是达灵顿反相器，其可以具有如图2所示的结构，但发明构思不限于此。为了便于说明，在下文中将以达灵顿反相器为例展开描述。
参照图6，第一下拉维持电路单元501可以包括：第一反相器，具有第一输入端Input、第一输出端Output(对应第一节点A)和第一控制端，其中，第一输入端Input可以连接到预充电节点Q(N)，第一输出端Output可以连接到第六薄膜晶体管T32和第七薄膜晶体管T42的栅极；第六薄膜晶体管T32，其栅极可以连接到第七薄膜晶体管T42的栅极，其漏极可以连接到低电源电压线VSS，其源极可以连接到本级的扫描驱动线；第七薄膜晶体管T42，其栅极可以连接到第六薄膜晶体管T32的栅极，其漏极可以连接到低电源电压线VSS，其源极可以连接到预充电节点Q(N)。
类似地，第二下拉维持电路单元502可以包括：第二反相器，具有第二输入端Input、第二输出端Output(对应第一节点B)和第二控制端，其中，第二输入端Input可以连接到预充电节点，第二输出端Output可以连接到第八薄膜晶体管T33和第九薄膜晶体管的栅极T43；第八薄膜晶体管T33，其栅极可以连接到第九薄膜晶体管T43的栅极，其漏极可以连接到低电源电压线VSS，其源极可以连接到本级的扫描驱动线；第九薄膜晶体管T43，其栅极可以连接到第八薄膜晶体管T33的栅极，其漏极可以连接到低电源电压线VSS，其源极可以连接到预充电节点Q(N)。
除了第二控制端被输入第二时钟信号XCK之外，第二下拉维持电路单元502可以具有与第一下拉维持电路单元501基本相同的电路结构。下拉维持电路单元501和502主要用于将预充电节点Q(N)、扫描驱动信号G(N)的电位维持在低电源电压VSS不变。
图7是根据本发明的示例性实施例的时钟信号的波形图。
如图7中所示，第一时钟信号CK与第二时钟信号XCK具有相同长度的周期。以一个周期为例，第一时钟信号CK和第二时钟信号XCK每者的一个周期可以包括第一时段t1’、第二时段t2’、第三时段t3’和第四时段t4’。另外，第一时钟信号CK和第二时钟信号XCK可以为方波脉冲信号，其各自的每一个周期可以由高电位周期和低电位周期组成。
根据本发明的示例性实施例，第二时钟信号XCK相对于第一时钟信号CK延迟，使得第二时钟信号XCK在第一时钟信号CK的每个高电位周期内的第一时段t1’和第三时段t3’具有高电位，并且在第一时段t1’与第三时段t3’之间的第二时段t2’具有低电位。
在一个示例性实施例中，对于第一时钟信号CK的每个高电位周期，第一时段t1’可以为第一时钟信号CK的初始时段和第二时钟信号XCK的前一高电位周期的结束时段，第二时段t2’可以为第一时钟信号CK的中间时段和第二时钟信号XCK的低电位时段，第三时段t3’可以为第一时钟信号CK的结束时段和第二时钟信号XCK的后一高电位周期的初始时段。
根据本发明的示例性实施例，第一时钟信号CK和第二时钟信号XCK的高电位时间可以占一个周期的60％，低电位时间可以占一个周期的40％。即，第一时钟信号CK和第二时钟信号XCK中的每个的占空比可以为60/40。
在一个示例性实施例中，第一时段t1’和第三时段t3’可以彼此间隔开，并且各自可以占每个周期的10％。第二时段t2’和第四时段t4’可以各自占一个周期的40％。第一时钟信号CK与第二时钟信号XCK可以在第二时段t2’和第四时段t4’期间完全反相。
可选择地，根据本发明的其他示例性实施例，第一时钟信号CK和第二时钟信号XCK的高低电位的占空比(即，高电位时间与低电位时间的比)可以为其他比例，例如，50/50、70/30、80/20等；第一时段t1’和第三时段t3’各自 占一个周期时间也可以为其他比例，例如，5％、20％等。
返回参照图6，当预充电节点Q(N)处于高电位(未示出)时，根据达灵顿反相器的原理，第一反相器的第一输出端(即，第一节点A)和第二反相器的第二输出端(即，第二节点B)均处于低电位，薄膜晶体管T32、T42、T33和T43均截止，此时，下拉维持电路单元501和502均不工作。然而，在低电位维持阶段，预充电节点Q(N)处于低电位，薄膜晶体管T52、T54、T62和T64均截止，此时，下拉维持电路单元501和502交替工作以维持扫描驱动信号G(N)的低电位，以下将结合图6和图7说明交替工作的原理。
在第一时段t1’期间，第一时钟信号CK为高电位，第二时钟信号XCK也为高电位。此时，作为第一反相器的第一输出端的第一节点A和作为第二反相器的第二输出端的第二节点B均处于高电位，薄膜晶体管T32、T42、T33和T43均导通，第一下拉维持电路单元501和第二下拉维持电路单元502均处于工作状态，低电源电压VSS可以分别传输到预充电节点Q(N)和本级扫描驱动线以维持预充电节点Q(N)和扫描驱动信号G(N)的低电位。
在第二时段t2’期间，第一时钟信号CK仍然为高电位，第二时钟信号XCK转变为低电位。此时，作为第一反相器的第一输出端的第一节点A可以处于高电位，薄膜晶体管T32和T42导通，第一下拉维持电路单元501可以处于工作状态，低电源电压VSS可以分别传输到预充电节点Q(N)和本级扫描驱动线以维持预充电节点Q(N)和扫描驱动信号G(N)的低电位。然而，由于作为第二反相器的第二输出端的第二节点B此时处于低电位，因此薄膜晶体管T33和T43截止，第二下拉维持电路单元502不工作。
在第三时段t3’期间，第一时钟信号CK仍然为高电位，第二时钟信号XCK转变为高电位。此时，作为第一反相器的第一输出端的第一节点A和作为第二反相器的第二输出端的第二节点B均处于高电位，薄膜晶体管T32、T42、T33和T43均导通，第一下拉维持电路单元501和第二下拉维持电路单元502均处于工作状态，低电源电压VSS可以分别传输到预充电节点Q(N)和本级扫描驱动线以维持预充电节点Q(N)和扫描驱动信号G(N)的低电位。
在第四时段t4’期间，第一时钟信号CK转变为低电位，第二时钟信号XCK仍然为高电位。此时，作为第一反相器的第一输出端的第一节点A可以处于低电位，薄膜晶体管T32和T42截止，第一下拉维持电路单元501不工作；而作 为第二反相器的第二输出端的第二节点B此时却处于高电位，薄膜晶体管T33和T43导通，第二下拉维持电路单元502处于工作状态，低电源电压VSS可以分别传输到预充电节点Q(N)和本级扫描驱动线以维持预充电节点Q(N)和扫描驱动信号G(N)的低电位。
在现有技术中，由于两个下拉维持单元交替工作，通常采用如图5所示的完全反相的控制信号LC1和LC2，当两个下拉维持单元出现交替的时刻，控制信号LC1和LC2属于高频交流信号，在电阻-电容的作用下会出现信号延迟的情形，即信号会出现一定程度的渐变情况，可能导致扫描驱动信号G(N)间断或电位不稳定。
本发明很好地解决了上述技术问题。根据本发明的示例性实施例，将时钟信号CK和XCK设置为具有同为高电位的时间段(即，第一时段t1’和第三时段t3’)，例如，参照图7，在第二下拉维持单元502的工作状态即将结束的时段(例如，第一时段t1’)，第一下拉维持单元501开始进入工作状态；而在第一下拉维持单元501的工作状态即将结束的时段(例如，第三时段t3’)，第二下拉维持单元502开始进入工作状态，从而保证了下拉维持单元501和502正常的交替工作，稳定地维持预充电节点Q(N)和扫描驱动信号G(N)的低电位，而不会出现扫描驱动信号G(N)的间断或电位不稳定。
此外，根据本发明的示例性实施例，当使用图7的时钟信号CK和XCK来驱动GOA电路时，图6的单级GOA电路单元中的下拉电路单元400被输入下两级GOA电路单元的扫描驱动信号G(N+2)，使得可以更好地维持扫描驱动信号G(N)的稳定。以下将参照图6和图8来说明此情况。
图8是图6的单级GOA电路单元的信号波形图。图8示出了如图7所示的时钟信号CK和XCK、第N级GOA电路单元的扫描输出信号G(N)、第N+1级GOA电路单元的扫描输出信号G(N+1)以及第N+2级GOA电路单元的扫描输出信号G(N+2)。
如前所述，当向第N级GOA电路单元中的上拉电路单元200输入第一时钟信号CK时，向第(N+1)级GOA电路单元中的上拉电路单元200输入第二时钟信号XCK，并且向第(N+2)级GOA电路单元中的上拉电路单元200输入第一时钟信号CK，以此类推。相应地，参照图8，在扫描输出阶段，第N级GOA电路单元的扫描输出信号G(N)对应第一时钟信号CK，第N+1级 GOA电路单元的扫描输出信号G(N+1)对应第二时钟信号XCK，第N+2级GOA电路单元的扫描输出信号G(N+2)对应第一时钟信号CK。
在现有技术中，以第N级GOA电路单元为例，通常向下拉电路单元400输入下一级GOA电路单元的扫描驱动信号G(N+1)，但是这种驱动方法会造成扫描输出信号G(N)的不稳定。具体来说，在扫描输出时段t1-t3，预充电节点Q(N)为高电位(未示出)，第二薄膜晶体管T21导通，第N级GOA电路单元的扫描输出信号G(N)为高电位信号；而在复位时段t3-t5，由于第N+1级GOA电路单元的扫描输出信号G(N+1)为高电位，其会传输到第N级GOA电路单元中的下拉电路单元400，第四薄膜晶体管T31会导通，从而低电源电压VSS会经由第四薄膜晶体管T31将第N级GOA电路单元的扫描输出信号G(N)拉低至低电位。由此可见，在t3时段，第二薄膜晶体管T21和第四薄膜晶体管T31均导通，此时，第N级GOA电路单元的扫描驱动线会被同时输入高电位的第一时钟信号CK和低电位的低电源电压VSS，高电位和低电位的同时竞争会导致扫描输出信号G(N)的不稳定。
在根据本发明的示例性实施例中，如图6所示，以第N级GOA电路单元为例，向下拉电路单元400输入来自下两级(即，第(N+2)级)GOA电路单元的扫描驱动信号G(N+2)。这种驱动方法可以有效地避免上述“高、低电位的同时竞争”的问题。具体来说，在扫描输出时段t1-t4，预充电节点Q(N)为高电位(未示出)，第二薄膜晶体管T21导通，第N级GOA电路单元的扫描输出信号G(N)与第一时钟信号CK对应，先为高电位，后为低电位；而在复位时段t5-t6，第N+2级GOA电路单元的扫描输出信号G(N+2)为高电位，其传输到第N级GOA电路单元中的下拉电路单元400，第四薄膜晶体管T31导通，从而低电源电压VSS经由第四薄膜晶体管T31将第N级GOA电路单元的扫描输出信号G(N)拉低至低电位。由此可见，扫描输出时段t1-t4与复位时段t5-t6不叠置，不会出现高电位和低电位同时输入到第N级GOA电路单元的扫描驱动线的情况。在t6时段之后的时段(即，低电位维持阶段)，如前面参照图6和图7所述，下拉维持电路单元501和502交替工作以维持预充电节点Q(N)和扫描驱动信号G(N)的低电位，将不再重复描述。
综上所述，根据图6和图8的示例性实施例，提供了一种驱动包括GOA电路的液晶面板的方法。
参照图6，根据本发明的示例性实施例的包括GOA电路的液晶面板的GOA电路包括级联的多个单级GOA电路单元，其中，每个单级GOA电路单元可以包括上拉控制电路单元100、上拉电路单元200、下传电路单元300、下拉电路单元400、自举电容Cbt、第一下拉维持电路单元501以及第二下拉维持电路单元502。如图6和图8中所示，所述方法包括：向第一下拉维持电路单元501的第一控制端输入第一时钟信号CK，并且向第二下拉维持电路单元502的第二控制端输入第二时钟信号XCK，向相邻两级的GOA电路单元中的上拉电路单元200交替地输入第一时钟信号CK和第二时钟信号XCK；在扫描输出时段(例如，时段t1-t4)，上拉电路单元200将第一时钟信号CK或第二时钟信号XCK输出到本级的扫描驱动线以输出扫描驱动信号G(N)；在复位时段(例如，时段t5-t6)，向下拉电路单元400输入来自下两级GOA电路单元的扫描驱动信号G(N+2)以对预充电节点Q(N)和扫描驱动信号G(N)的电位进行复位；在低电位维持阶段(例如，在时段t6之后的时段)，第一下拉维持电路单元501和第二下拉维持电路单元502交替工作以维持扫描驱动信号G(N)和预充电节点Q(N)的低电位。
由于图8中的第一时钟信号CK和第二时钟信号XCK的时序与图7中所示的时序一致，将不再重复其详细描述。
综上所述，根据本发明的示例性实施例的包括GOA电路的液晶面板的每个单级GOA电路被输入一组新的时钟信号CK和XCK，该组时钟信号既可以满足上拉电路单元的信号要求，也可以替代下拉维持电路单元中的控制信号，从而高效利用了时钟信号线且有效节省了显示面板中布线所占的空间，此外，根据本发明的示例性实施例的包括GOA电路的液晶面板还改进了下拉电路单元400的输入控制信号，进一步提高了扫描输出信号的稳定性，为未来GOA电路的设计提供了一种新的可能。
此外，除了上述GOA电路以外，根据本发明的示例性实施例的液晶面板还可以包括偏光片、滤光片、液晶层和背光模块等本领域常见的各种元件，这里不再详细阐述。
虽然已表示和描述了本发明的一些示例性实施例，但本领域技术人员应该理解，在不脱离由权利要求及其等同物限定其范围的本发明的原理和精神的情 况下，可以对这些实施例进行修改。

Claims (10)

  1. 一种包括GOA电路的液晶面板，所述GOA电路包括级联的多个单级GOA电路单元，其中，每个单级GOA电路单元包括上拉控制电路单元、上拉电路单元、下拉电路单元、自举电容、下传电路单元、第一下拉维持电路单元和第二下拉维持电路单元，
    其中，在每个单级GOA电路单元中，第一下拉维持电路单元的第一控制端被构造为接收第一时钟信号，第二下拉维持电路单元的第二控制端被构造为接收第二时钟信号，下拉电路单元被构造为接收来自下两级GOA电路单元的扫描驱动信号，
    其中，相邻两级的GOA电路单元中的上拉电路单元被构造为交替地接收第一时钟信号和第二时钟信号，
    其中，第一时钟信号与第二时钟信号具有相同长度的周期，
    其中，第二时钟信号相对于第一时钟信号延迟，使得第二时钟信号在第一时钟信号的每个高电位周期内的第一时段和第三时段具有高电位，并且在第一时段与第三时段之间的第二时段具有低电位。
  2. 根据权利要求1所述的液晶面板，其中，第一下拉维持电路单元包括：
    第一反相器，具有第一输入端、第一输出端和第一控制端，其中，第一输入端连接到预充电节点，第一输出端连接到第六薄膜晶体管和第七薄膜晶体管的栅极；
    第六薄膜晶体管，其栅极连接到第七薄膜晶体管的栅极，其漏极连接到低电源电压线，其源极连接到本级的扫描驱动线；
    第七薄膜晶体管，其栅极连接到第六薄膜晶体管的栅极，其漏极连接到低电源电压线，其源极连接到预充电节点。
  3. 根据权利要求2所述的液晶面板，其中，第二下拉维持电路单元包括：
    第二反相器，具有第二输入端、第二输出端和第二控制端，其中，第二输入端连接到预充电节点，第二输出端连接到第八薄膜晶体管和第九薄膜晶体管的栅极；
    第八薄膜晶体管，其栅极连接到第九薄膜晶体管的栅极，其漏极连接到低 电源电压线，其源极连接到本级的扫描驱动线；
    第九薄膜晶体管，其栅极连接到第八薄膜晶体管的栅极，其漏极连接到低电源电压线，其源极连接到预充电节点。
  4. 根据权利要求3所述的液晶面板，其中，下拉电路单元包括：
    第四薄膜晶体管，其栅极与第五薄膜晶体管的栅极对接并且被构造为接收来自下两级GOA电路单元的扫描驱动信号，其漏极连接到低电源电压线，其源极连接到本级的扫描驱动线；
    第五薄膜晶体管，其栅极与第四薄膜晶体管的栅极对接并且被构造为接收来自下两级GOA电路单元的扫描驱动信号，其漏极连接到低电源电压线，其源极连接到预充电节点。
  5. 根据权利要求1所述的液晶面板，其中，上拉电路单元包括：
    第二薄膜晶体管，其漏极连接到下传电路单元并且被构造为接收第一时钟信号或第二时钟信号，其栅极连接到预充电节点，其源极连接到本级的扫描驱动线以输出扫描驱动信号。
  6. 根据权利要求1所述的液晶面板，其中，下传电路单元包括：
    第三薄膜晶体管，其漏极连接到上拉电路单元并且被构造为接收第一时钟信号或第二时钟信号，其栅极连接到预充电节点，其源极连接到本级的级传信号线以输出级传信号。
  7. 一种驱动包括GOA电路的液晶面板的方法，所述GOA电路包括级联的多个单级GOA电路单元，其中，每个单级GOA电路单元包括上拉控制电路单元、上拉电路单元、下拉电路单元、自举电容、下传电路单元、第一下拉维持电路单元和第二下拉维持电路单元，所述方法包括：
    向第一下拉维持电路单元的第一控制端输入第一时钟信号，并且向第二下拉维持电路单元的第二控制端输入第二时钟信号，向相邻两级的GOA电路单元中的上拉电路单元交替地输入第一时钟信号和第二时钟信号；
    在扫描输出时段，上拉电路单元将第一时钟信号或第二时钟信号输出到本级的扫描驱动线以输出扫描驱动信号；
    在复位时段，向下拉电路单元输入来自下两级GOA电路单元的扫描驱动信号以对预充电节点和扫描驱动信号的电位进行复位；
    在低电位维持阶段，第一下拉维持电路单元和第二下拉维持电路单元交替 工作以维持扫描驱动信号和预充电节点的低电位，
    其中，第一时钟信号与第二时钟信号具有相同长度的周期，
    其中，第二时钟信号相对于第一时钟信号延迟，使得第二时钟信号在第一时钟信号的每个高电位周期内的第一时段和第三时段具有高电位，并且在第一时段与第三时段之间的第二时段具有低电位。
  8. 根据权利要求7所述的方法，其中，第一时段为第一时钟信号的初始时段和第二时钟信号的前一高电位周期的结束时段，第二时段为第一时钟信号的中间时段和第二时钟信号的低电位时段，第三时段为第一时钟信号的结束时段和第二时钟信号的后一高电位周期的初始时段。
  9. 根据权利要求8所述的方法，其中，第一时钟信号和第二时钟信号中的每个的占空比为60/40。
  10. 根据权利要求9所述的方法，其中，第一时段和第三时段各自占每个周期的10％。
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