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WO2020019433A1 - 包括goa电路的液晶面板及其驱动方法 - Google Patents

包括goa电路的液晶面板及其驱动方法 Download PDF

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Publication number
WO2020019433A1
WO2020019433A1 PCT/CN2018/105435 CN2018105435W WO2020019433A1 WO 2020019433 A1 WO2020019433 A1 WO 2020019433A1 CN 2018105435 W CN2018105435 W CN 2018105435W WO 2020019433 A1 WO2020019433 A1 WO 2020019433A1
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Prior art keywords
circuit unit
thin film
film transistor
pull
goa circuit
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PCT/CN2018/105435
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English (en)
French (fr)
Inventor
陈帅
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深圳市华星光电技术有限公司
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Priority to US16/322,036 priority Critical patent/US20200035179A1/en
Publication of WO2020019433A1 publication Critical patent/WO2020019433A1/zh

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    • GPHYSICS
    • G09EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09GARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/34Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
    • G09G3/36Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
    • G09G3/3611Control of matrices with row and column drivers
    • G09G3/3674Details of drivers for scan electrodes

Definitions

  • the present invention relates to the field of liquid crystal display technology, and more particularly, to a liquid crystal panel including a GOA (Gate Driver On Array) circuit and a driving method thereof.
  • GOA Gate Driver On Array
  • Liquid crystal displays have the advantages of low radiation, small size, and low energy consumption. They have been widely used in notebook computers, personal digital assistants, PDAs, flat-screen televisions, or mobile phones.
  • the traditional liquid crystal display method uses an external driving chip to drive the chip on the panel to display the image.
  • it has gradually developed to directly drive the circuit structure on the display panel, for example, using GOA technology. .
  • the GOA technology integrates a TFT LCD (Thin Film Transistor Liquid Crystal Display) gate drive circuit on a glass substrate to form a scan drive for a liquid crystal panel.
  • TFT LCD Thin Film Transistor Liquid Crystal Display
  • COF Chip, Flex / Film
  • GOA technology can greatly save manufacturing costs, and eliminates the Bonding process of the gate-side COF, which is also extremely beneficial to the improvement of production capacity. Therefore, GOA is a key technology for the development of LCD panels in the future.
  • the existing GOA circuit usually includes a plurality of single-stage GOA circuit units cascaded, and each single-stage GOA circuit unit corresponds to a scan driving line of a corresponding stage.
  • the single-stage GOA circuit unit includes: a pull-up control circuit unit 1, a pull-up circuit unit 2, a signal download circuit unit 3, a pull-down circuit unit 4, a pull-down sustain circuit unit 5, and a bootstrap capacitor 6 .
  • the pull-up control circuit unit 1 mainly implements pre-charging for the pre-charging node Q (N), which is usually input to the down-going signal ST (N-1) and the scan driving signal G ( N-1); the pull-up circuit unit 2 is mainly used to increase the potential of the scan driving signal G (N); the signal transmission unit 3 includes a thin film transistor, which mainly controls the next by outputting the downstream signal ST (N) of this stage
  • the pull-up control circuit unit in the first-level GOA circuit unit is turned on and off;
  • the pull-down circuit unit 4 is mainly used to pull down the potential of the pre-charge node Q (N) and the scan drive signal G (N) to a low power supply voltage VSS; pull-down maintenance
  • the circuit unit 5 includes an inverter and a plurality of thin film transistors, which are mainly used to maintain the potentials of the precharge node Q (N) and the scan driving signal G (N) at a low power supply voltage VSS; the bootstrap capacitor 6 is mainly Provide
  • the inverter of the pull-down sustaining circuit unit 5 can use a Darlington inverter.
  • the specific circuit structure is shown in Figure 2.
  • the Darlington inverter can include four thin film transistors and can have input terminals Input and output terminals. Output. If the control signal LC is set to always be a high-potential signal and the low power supply voltage VSS is set to always be a low-potential signal, when a high-potential signal is input at the input terminal Input, a low-potential signal is output at the output terminal; When a low potential signal is output, the output terminal Output outputs a high potential signal.
  • the pull-down sustaining circuit unit 5 includes a Darlington inverter, its structure is shown in FIG. 3.
  • An exemplary embodiment of the present invention is to provide a liquid crystal panel including a GOA circuit and a driving method thereof, wherein the GOA circuit includes a plurality of cascaded single-stage GOA circuit units, and in each single-stage GOA circuit unit, completely Cancel the signal transmission circuit unit, simplify the circuit structure of the pull-down maintenance circuit unit, improve the control signal of the pull-up control circuit unit so that it can also play part of the function of the pull-down maintenance circuit unit, simplify the GOA circuit structure, and realize The narrow bezel design of the LCD panel.
  • a liquid crystal panel including a GOA circuit, the GOA circuit including a plurality of cascaded single-stage GOA circuit units, wherein each single-stage GOA circuit unit includes: a pull-up control circuit
  • the unit includes a first thin film transistor, wherein a gate of the first thin film transistor is input with a first clock signal, a drain of the first thin film transistor is input with a scan driving signal of a previous stage GOA circuit unit, and a source of the first thin film transistor.
  • the pull-up circuit unit includes a second thin film transistor, wherein the drain of the second thin film transistor is input with a second clock signal that is opposite to the first clock signal; the pull-down sustaining circuit unit is controlled by Daring
  • the frame inverter is composed of a third inverter and a third thin film transistor; the circuit unit is pulled down to pull down the potentials of the precharge node and the scan driving signal to a low potential; and a bootstrap capacitor to maintain and increase the potential of the precharge node.
  • Each single-level GOA circuit unit does not include a signal download circuit unit.
  • the gate of the second thin film transistor is connected to the precharge node, and the source of the second thin film transistor is connected to the scan driving line of the stage to output a scan driving signal.
  • the Darlington inverter In the pull-down sustaining circuit unit of each single-stage GOA circuit unit, the Darlington inverter has an input terminal and an output terminal, whose input terminal is connected to the precharge node, and its output terminal is connected to the gate of the third thin film transistor.
  • the drain of the third thin film transistor is connected to the low power supply voltage line, and the source thereof is connected to the scan drive line of the current stage to output a scan drive signal.
  • the pull-down circuit unit includes a fourth thin film transistor and a fifth thin film transistor, wherein the gates of the fourth and fifth thin film transistors are docked with each other and are input to the next level of the GOA circuit unit.
  • one end of the bootstrap capacitor is connected to the precharge node, and the other end of the bootstrap capacitor is connected to the scanning drive line of the stage.
  • the first clock signal and the second clock signal are inverted square wave signals.
  • the thin-film transistors included in each single-stage GOA circuit unit are amorphous silicon thin-film transistors that are turned on at a high level.
  • a display device including the above-mentioned liquid crystal panel.
  • a driving method of a liquid crystal panel including a GOA circuit is provided.
  • the liquid crystal panel adopts the foregoing liquid crystal panel.
  • the driving method includes: in each single-stage GOA circuit unit, In the precharge period, the pull-up control circuit unit inputs the scan driving signal of the upper-level GOA circuit unit to the pre-charge node under the control of the first clock signal, and charges the bootstrap capacitor.
  • the pull-up circuit unit is in Under the control of the potential of the precharge node and the bootstrap capacitor, a second clock signal that is opposite to the first clock signal is output to the scanning driving line of this stage to output the scanning driving signal; during the reset period, the pull-down circuit unit is at the next GOA
  • the low-voltage supply is input to the pre-charge node and the scan drive line of this stage under the control of the scan drive signal of the circuit unit to reset the potentials of the pre-charge node and the scan drive signal.
  • the pull-up control Under the control of the first clock signal, the circuit unit inputs the scan driving signal of the upper GOA circuit unit to the precharge node to maintain The low potential of the precharge node, and the pull-down sustaining circuit unit inputs a low power voltage to the scanning driving line of this stage under the control of the potential of the precharging node to maintain the low potential of the scanning driving signal.
  • FIG. 1 is a schematic diagram of a single-stage GOA circuit unit in the prior art
  • FIG. 2 is a circuit diagram of a Darlington inverter included in the pull-down sustaining circuit unit of FIG. 1;
  • Figure 3 is a detailed circuit diagram of Figure 1;
  • FIG. 5 is a circuit diagram of a single-stage GOA circuit unit according to an exemplary embodiment of the present invention.
  • FIG. 6 is a signal waveform diagram of the single-stage GOA circuit unit of FIG. 5.
  • a GOA circuit in a liquid crystal panel includes a plurality of thin film transistors.
  • FIG. 4 is an equivalent circuit diagram of a thin film transistor.
  • the three electrodes of the thin film transistor are called a gate, a source, and a drain, respectively.
  • the voltages applied to the electrodes can be labeled as Vg, Vs, and Vd, respectively.
  • the lower voltage end is generally referred to as the source Source, and the other higher voltage end is referred to as Drain.
  • Vgs>0 the thin film transistor is in the on state, and the current flows from drain Drain to the source Source.
  • Vgs ⁇ 0 the device is in the off state.
  • one end with a lower voltage may be referred to as a drain Drain, and the other end with a higher voltage may be referred to as a source Source, that is, when the thin film transistor is in an on state, Current flows from source to drain Drain.
  • FIG. 5 is a circuit diagram of a single-stage GOA circuit unit according to an exemplary embodiment of the present invention.
  • a liquid crystal panel includes a GOA circuit.
  • the GOA circuit includes a plurality of cascaded single-stage GOA circuit units.
  • Each single-stage GOA circuit unit includes: a pull-up control circuit unit 1, an upper The pull-down circuit unit 2, the pull-down sustain circuit unit 3, the pull-down circuit unit 4, and the bootstrap capacitor 5.
  • the connection structure of the N-th GOA circuit unit will be described as an example, and other GOA circuit units have similar structures.
  • the pull-up control circuit unit 1 in the N-th GOA circuit unit includes a first thin film transistor T11, wherein a gate of the first thin film transistor T11 is input with a first clock signal XCK, and the first thin film transistor T11
  • the drain electrode of the first stage (ie, the (N-1) th stage) GOA circuit unit's scan drive signal G (N-1) is input, and the source of the first thin film transistor T11 is connected to the precharge node Q (N ).
  • the pull-up control circuit unit 1 is mainly used to implement pre-charge for the pre-charge node Q (N).
  • the pull-up circuit unit 2 includes a second thin-film transistor T21, wherein a drain of the second thin-film transistor T21 is input with a second clock signal CK that is opposite to the first clock signal XCK.
  • the pull-up circuit unit 2 is mainly used to increase the potential of the scan driving signal G (N).
  • the gate of the first thin film transistor T11 in the pull-up control circuit unit 1 of this stage is input with the first clock signal XCK, and the second thin film transistor T21 in the pull-up circuit unit 2 of this stage The drain is input to the second clock signal CK.
  • the inventive concept is not limited to this.
  • the gate of the first thin film transistor T11 in the pull-up control circuit unit 1 of this stage may be input with the second clock signal CK, and the pull-up circuit unit of this stage
  • the drain of the second thin film transistor T21 in 2 may be input with a first clock signal XCK which is inversely opposite to the second clock signal CK.
  • a first clock signal XCK which is inversely opposite to the second clock signal CK.
  • the pull-down sustaining circuit unit 3 is composed of a Darlington inverter and a third thin film transistor T32.
  • the pull-down sustaining circuit unit 3 is mainly used to maintain the potentials of the precharge node Q (N) and the scan driving signal G (N) at a low power supply voltage VSS.
  • the single-stage GOA circuit unit of the liquid crystal panel according to the present exemplary embodiment further includes a pull-down circuit unit and a bootstrap capacitor.
  • the pull-down circuit unit is used to pull down the potentials of the precharge node and the scan driving signal to a low potential.
  • the bootstrap capacitor is used to maintain and increase the potential of the precharge node.
  • the single-stage GOA circuit unit included in the liquid crystal panel according to the exemplary embodiment of the present invention uses a clock signal instead of the down-signal from the upper stage, and eliminates the figure
  • the thin-film transistor T42 in the pull-down sustaining circuit unit 5 shown in FIG. 3 simplifies the circuit structure and facilitates the realization of the narrow bezel design of the liquid crystal panel.
  • the single-stage GOA circuit unit shown in FIG. 5 may not include a signal download circuit unit.
  • the pull-up circuit unit 2 may include only the second thin film transistor T21.
  • the gate of the second thin film transistor T21 may be connected to a precharge node Q (N).
  • the drain of the second thin film transistor T21 may be inputted with a second clock signal CK which is inverse to the first clock signal XCK.
  • the source of the second thin film transistor T21 may be connected to a scan driving line of this stage to output a scan driving signal G (N).
  • the single-stage GOA circuit unit in the liquid crystal panel according to the exemplary embodiment of the present invention does not include a signal downloading circuit unit, it does not have to send a downloading signal to the next stage, nor does the pull-up control circuit unit of the next stage. Receiving the downlink signal from this stage, instead of receiving the downlink signal by receiving the clock signal, the circuit structure can be further simplified.
  • the pull-down sustaining circuit unit 3 may not include the thin film transistor T42, but may be composed of only a Darlington inverter and a third thin film transistor T32.
  • a Darlington inverter may have an input terminal Input and an output terminal Output.
  • the gate of the third thin film transistor T32 can be connected to the output terminal Output of the Lington inverter, and its drain can be connected to a low power supply voltage line that outputs a low power supply voltage VSS of DC, and its source can be connected to the scanning of this stage.
  • the driving line outputs a scanning driving signal G (N).
  • the Darlington inverter of FIG. 5 may include four thin film transistors T51, T52, T53, and T54.
  • the gates of the thin film transistors T52 and T54 may be connected to the input terminal Input, and thus all connected to the The charging node Q (N), the drains of the thin film transistors T52 and T54 can be connected to the low power voltage line VSS, the source of the thin film transistor T54 can be connected to the output terminal Output, and the source of the thin film transistor T52 can be connected to the thin film transistor T51.
  • the source of the thin film transistor T53 and the gate of the thin film transistor T53; the thin film transistors T51 and T53 can be connected in series, that is, the drain of the thin film transistor T53, the drain and the gate of the thin film transistor T51 can be input with the control signal LC, The source can be connected to the output.
  • control signal LC is always a high-potential signal and the low power supply voltage VSS is always a low-potential signal.
  • VSS low power supply voltage
  • the pull-down circuit unit 4 may include a fourth thin film transistor T41 and a fifth thin film transistor T31, where the gates of the two thin film transistors T31 and T41 may be docked with each other, and both may be input to the next stage (that is, Scanning driving signal G (N + 1) of the (N + 1) th stage GOA circuit unit; the drains of the two thin film transistors T31 and T41 can be connected to the low power supply voltage line; the source of the fifth thin film transistor T31 It can be connected to the scan drive line of this stage to output the scan drive signal G (N), and the source of the fourth transistor T41 can be connected to the precharge node Q (N).
  • the next stage that is, Scanning driving signal G (N + 1) of the (N + 1) th stage GOA circuit unit
  • the drains of the two thin film transistors T31 and T41 can be connected to the low power supply voltage line
  • the source of the fifth thin film transistor T31 It can be connected to the scan drive line of this stage to output the scan
  • one end of the bootstrap capacitor Cbt may be connected to the pre-charge node Q (N), and the other end thereof may be connected to a scanning driving line of this stage.
  • the bootstrap capacitor 5 takes advantage of the fact that the voltage across the capacitor cannot be abruptly changed. When a certain voltage is maintained across the capacitor, the voltage at the negative terminal of the capacitor is increased. The voltage at the positive terminal still maintains the original voltage difference from the negative terminal, which is equal to the voltage at the positive terminal being lifted by the negative terminal. With this characteristic, the bootstrap capacitor Cbt can maintain and increase the potential of the precharge node Q (N).
  • all the thin film transistors in the GOA circuit may be N-type thin film transistors that are turned on at a high level, for example, N-type amorphous silicon (a-Si) films that are turned on at a high level Transistor or NMOS thin film transistor.
  • a-Si N-type amorphous silicon
  • the inventive concept is not limited thereto, and in other exemplary embodiments, the thin film transistors in the GOA circuit may also be P-type thin film transistors that are turned on at a low level, such as a PMOS thin film transistor.
  • FIG. 6 is a signal waveform diagram of the single-stage GOA circuit unit of FIG. 5. The driving method of the single-stage GOA circuit unit will be described in detail below with reference to FIGS. 5 and 6.
  • the second clock signal CK may be a square wave signal with a duty cycle (ie, the time ratio of the high level occupied in one cycle) of 50%, or the duty cycle may be another ratio. signal of.
  • the second clock signal CK is inverted from the first clock signal XCK.
  • the control signal LC may be a high-potential signal
  • the low power supply voltage VSS may be a low-potential signal.
  • a second clock signal CK is input to the drain of the second thin film transistor T21 and a first clock signal XCK is input to the gate of the first thin film transistor T11
  • a first clock signal XCK may be input to a drain of the second thin film transistor T21
  • a second clock signal CK may be input to a gate of the first thin film transistor T11.
  • the thin film transistors included in the N-th GOA circuit unit are all N-type thin film transistors that are turned on at a high level.
  • the pull-up control circuit unit 1 since the first clock signal XCK is at a high potential, the first thin film transistor T11 is turned on, so that the scan driving signal of the GOA circuit unit of the upper stage (ie, the (N-1) th stage) The high potential of G (N-1) is transferred from the drain of the first thin film transistor T11 to the precharge node Q (N) connected to the source of the first thin film transistor T11. Therefore, the precharge node Q (N) is charged. High voltage, and charge the bootstrap capacitor Cbt to realize the pre-charging function.
  • the second thin film transistor T21 is turned on, so that the low potential of the second clock signal CK which is opposite to the first clock signal XCK is changed from the second
  • the drain of the thin film transistor T21 is transmitted to a scan driving line connected to the source of the second thin film transistor T21, that is, a scan driving signal G (N) having a low potential is output.
  • the output terminal Output outputs a low potential, so that the third thin film transistor T32 ends.
  • the first clock signal XCK changes from a high potential to a low potential
  • the second clock signal CK changes from a low potential to a high potential.
  • the first clock signal XCK is at a low potential
  • the first thin film transistor T11 is turned off.
  • the second thin film transistor T21 is still turned on, so that the second clock signal CK
  • the high potential is transmitted from the drain of the second thin film transistor T21 to a scan driving line connected to the source of the second thin film transistor T21, that is, a high potential scan driving signal G (N) is output.
  • the output terminal Output outputs a low potential, so that the third thin film transistor T32 is still off.
  • the fifth thin film transistor T31 and The fourth thin film transistor T41 is turned on, and the low power supply voltage VSS is transmitted to the precharge node Q (N) via the fourth thin film transistor T41, and is transmitted to the scanning driving line of this stage via the fifth thin film transistor T31, so that the precharge node Q ( N) and the potential of the scan drive signal G (N) are both pulled to a low potential.
  • the first clock signal XCK transitions from a low potential to a high potential again during t2, and the first thin film transistor T11 is turned on; at this time, since the upper stage (ie, the (N-1) th Level)
  • the scan driving signal G (N-1) of the GOA circuit unit is at a low potential, which is transmitted to the precharge node Q (N) via the first thin film transistor T11, so as to keep the precharge node Q (N) at a low potential.
  • the second thin film transistor T21 is turned off.
  • the precharge node Q (N) is kept at a low potential, that is, the inverter input terminal Input is input with a low potential, the output terminal Output outputs a high potential, and the third thin film transistor T32 is turned on.
  • the low power supply voltage VSS is transmitted to the scanning driving line of this stage via the third thin film transistor T32, that is, the low potential of the scanning driving signal G (N) is maintained.
  • the present application also provides a method for driving a liquid crystal panel including a GOA circuit.
  • the GOA circuit may have a circuit structure as shown in FIG. 5.
  • the method for driving a liquid crystal panel includes: In the circuit unit, during the precharge period t1, the pull-up control circuit unit 1 inputs the scan driving signal G (N-1) of the upper-level GOA circuit unit to the precharge node Q under the control of the first clock signal XCK.
  • the pull-up circuit unit 2 will be inverted from the first clock signal under the control of the potential of the precharge node Q (N) and the bootstrap capacitor Ct
  • the second clock signal CK is output to the scan drive line of the current stage to output the scan drive signal G (N); during the reset period t3, the pull-down circuit unit 4 scans the drive signal G (N + 1) of the next stage GOA circuit unit.
  • the low power supply voltage VSS is input to the pre-charge node Q (N) and the scanning drive line of the current stage under the control of the power source to reset the potentials of the pre-charge node Q (N) and the scan drive signal G (N) (that is, pull Low to low potential), during the reset period, the pull-up control circuit Element 1 inputs the scan driving signal G (N-1) of the upper GOA circuit unit to the precharge node Q (N) under the control of the first clock signal XCK to maintain the low potential of the precharge node Q (N).
  • the pull-down sustaining circuit unit 3 inputs the low power supply voltage VSS to the scanning driving line of this stage under the control of the potential of the precharge node Q (N) to maintain the low potential of the scanning driving signal G (N).
  • the precharge node Q (N) When the signal G (N-1) is at a low potential, the precharge node Q (N) will be pulled to a low potential, that is, part of the function of the pull-down sustaining circuit unit is realized. Therefore, canceling the pull-down sustaining circuit unit of the thin-film transistor T42 shown in FIG. 3 in the single-level GOA circuit unit will not affect maintaining the low potential of the precharge node Q (N).
  • the present disclosure provides a liquid crystal panel including a GOA circuit and a driving method thereof.
  • the GOA circuit includes a plurality of cascaded single-stage GOA circuit units. In each single-stage GOA circuit unit, it is completely eliminated.
  • the signal transmission circuit unit is simplified, the circuit structure of the pull-down maintenance circuit unit is simplified, and the control signal of the pull-up control circuit unit is improved so that it can also perform part of the function of the pull-down maintenance circuit unit, thereby reducing the use of the GOA circuit.
  • the number of thin film transistors reduces the number of signal lines, simplifies the structure of the GOA circuit, and provides new ideas and ideas for the narrow bezel design of future LCD panels.
  • the liquid crystal panel according to the exemplary embodiment of the present invention may further include various elements common in the art such as a polarizer, a filter, a liquid crystal layer, and a backlight module, which will not be described in detail here.

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Abstract

一种包括GOA电路的液晶面板及其驱动方法。GOA电路包括级联的多个单级GOA电路单元,其中,每个单级GOA电路单元包括:上拉控制电路单元(1),包括第一薄膜晶体管(T11),其中,第一薄膜晶体管(T11)的栅极被输入第一时钟信号(XCK/CK),第一薄膜晶体管(T11)的漏极被输入上一级GOA电路单元的扫描驱动信号(G(N-1)),第一薄膜晶体管(T11)的源极连接到预充电节点(Q(N));上拉电路单元(2),包括第二薄膜晶体管(T21),其中,第二薄膜晶体管(T21)的漏极被输入与第一时钟信号(XCK/CK)反相的第二时钟信号(CK/XCK);下拉维持电路单元(3),由达灵顿反相器和一个第三薄膜晶体管(T32)组成;下拉电路单元(4),将预充电节点(Q(N))和扫描驱动信号(G(N))的电位拉低至低电位;以及自举电容(5),维持并提高预充电节点(Q(N))的电位。

Description

包括GOA电路的液晶面板及其驱动方法 技术领域
本发明涉及液晶显示技术领域,更具体地讲,涉及一种包括GOA(Gate Driver On Array,阵列基板行驱动)电路的液晶面板及其驱动方法。
背景技术
液晶显示器具有低辐射、体积小及低耗能等优点,已经被广泛地应用于笔记本电脑、个人数字助理PDA、平面电视或移动电话等产品上。传统液晶显示器的方式是利用外部驱动芯片来驱动面板上的芯片以显示图像,但为了减少元件数目并降低制造成本,近年来逐渐发展成将驱动电路结构直接制作于显示面板上,例如采用GOA技术。
GOA技术是将TFT LCD(Thin Film Transistor Liquid Crystal Display,薄膜晶体管液晶显示器)的栅极驱动电路集成在玻璃基板上,形成对液晶面板的扫描驱动。GOA技术相比传统的利用COF(Chip On Flex/Film,覆晶薄膜)的驱动技术可以大幅度节约制造成本,而且省去了Gate侧COF的Bonding制程,对产能提升也是极为有利的。因此,GOA是未来液晶面板发展的重点技术。
现有的GOA电路通常包括级联的多个单级GOA电路单元,每个单级GOA电路单元均与相应级的扫描驱动线对应。例如,如图1所示,单级GOA电路单元包括:上拉控制电路单元①、上拉电路单元②、信号下传电路单元③、下拉电路单元④、下拉维持电路单元⑤以及自举电容⑥。参照图1,上拉控制电路单元①主要为预充电节点Q(N)实现预充电,通常被输入上一级GOA电路单元传递过来的下传信号ST(N-1)和扫描驱动信号G(N-1);上拉电路单元②主要为提高扫描驱动信号G(N)的电位;信号下传单元③包括薄膜晶体管,其主要通过输出本级的下传信号ST(N)来控制下一级GOA电路单元中的上拉控制电路单元的打开和关闭;下拉电路单元④主要用于拉低预充电节点Q(N)和扫描驱动信号G(N)的电位至低电源电压VSS;下拉维持电路单元⑤包括反相器和多个薄膜晶体管,其主要用于将预充电节点Q(N)、扫描驱动信号G(N)的电位 维持在低电源电压VSS不变;自举电容⑥主要为提供并维持预充电节点Q(N)电位,这样有利于上拉电路单元②输出扫描驱动信号G(N)。
下拉维持电路单元⑤的反相器可以采用达灵顿反相器,其具体的电路结构如图2所示,达灵顿反相器可以包括四个薄膜晶体管并且可以具有输入端Input和输出端Output。如果将控制信号LC设置成始终为高电位信号并且将低电源电压VSS设置成始终为低电位信号,则当输入端Input输入高电位信号时,输出端Output输出低电位信号;当输入端Input输入低电位信号时,输出端Output输出高电位信号。当下拉维持电路单元⑤包括达灵顿反相器时,其结构如图3所示。
从GOA电路的发展来看,越来越多的功能结构被集成在GOA电路的级联单元中,导致GOA电路结构越来越复杂,其所占的空间也越来越大,这对于窄边框液晶面板的设计是极为不利的,因此,如何提高GOA电路中功能单元的使用效能且简化电路结构是未来液晶面板行业急需解决的问题。
发明内容
本发明的示例性实施例旨在提供一种包括GOA电路的液晶面板及其驱动方法,其中,GOA电路包括级联的多个单级GOA电路单元,在每个单级GOA电路单元中,完全取消了信号下传电路单元,简化了下拉维持电路单元的电路结构,改进了上拉控制电路单元的控制信号使其同样可以起到下拉维持电路单元的部分功能,简化了GOA电路结构,实现了液晶面板的窄边框设计。
根据发明的示例性实施例,提供了一种包括GOA电路的液晶面板,所述GOA电路包括级联的多个单级GOA电路单元,其中,每个单级GOA电路单元包括:上拉控制电路单元,包括第一薄膜晶体管,其中,第一薄膜晶体管的栅极被输入第一时钟信号,第一薄膜晶体管的漏极被输入上一级GOA电路单元的扫描驱动信号,第一薄膜晶体管的源极连接到预充电节点;上拉电路单元,包括第二薄膜晶体管,其中,第二薄膜晶体管的漏极被输入与第一时钟信号反相的第二时钟信号;下拉维持电路单元,由达灵顿反相器和一个第三薄膜晶体管组成;下拉电路单元,将预充电节点和扫描驱动信号的电位拉低至低电位;以及自举电容,维持并提高预充电节点的电位。
每个单级GOA电路单元不包括信号下传电路单元。
在每个单级GOA电路单元的上拉电路单元中,第二薄膜晶体管的栅极连接到预充电节点,第二薄膜晶体管的源极连接本级的扫描驱动线以输出扫描驱动信号。
在每个单级GOA电路单元的下拉维持电路单元中,达灵顿反相器具有输入端和输出端,其输入端连接到预充电节点,其输出端连接到第三薄膜晶体管的栅极。
在每个单级GOA电路单元的下拉维持电路单元中,第三薄膜晶体管的漏极连接到低电源电压线,其源极连接到本级的扫描驱动线以输出扫描驱动信号。
在每个单级GOA电路单元中,下拉电路单元包括第四薄膜晶体管和第五薄膜晶体管,其中,第四和第五薄膜晶体管的栅极彼此对接,并且均被输入下一级GOA电路单元的扫描驱动信号;第四和第五薄膜晶体管的漏极均连接到低电源电压线;第四薄膜晶体管的源极连接到预充电节点,第五薄膜晶体管的源极连接到本级的扫描驱动线以输出扫描驱动信号。
在每个单级GOA电路单元中,自举电容的一端连接到预充电节点,自举电容的另一端连接到本级的扫描驱动线。
第一时钟信号和第二时钟信号为反相的方波信号。
每个单级GOA电路单元中包括的薄膜晶体管均为高电平导通的非晶硅薄膜晶体管。
根据本发明的示例性实施例,提供了一种显示装置,包括上述的液晶面板。
根据本发明的示例性实施例,提供了一种包括GOA电路的液晶面板的驱动方法,所述液晶面板采用前述的液晶面板,所述驱动方法包括:在每个单级GOA电路单元中,在预充电时段,上拉控制电路单元在第一时钟信号的控制下将上一级GOA电路单元的扫描驱动信号输入到预充电节点,且对自举电容充电;在输出时段,上拉电路单元在预充电节点的电位和自举电容的控制下将与第一时钟信号反相的第二时钟信号输出到本级的扫描驱动线以输出扫描驱动信号;在复位时段,下拉电路单元在下一级GOA电路单元的扫描驱动信号的控制下将低电源电压输入到预充电节点和本级的扫描驱动线,以对预充电节点和扫描驱动信号的电位进行复位,其中,在复位时段内,上拉控制电路单元 在第一时钟信号的控制下将上一级GOA电路单元的扫描驱动信号输入到预充电节点以维持预充电节点的低电位,下拉维持电路单元在预充电节点的电位的控制下将低电源电压输入到本级的扫描驱动线以维持扫描驱动信号的低电位。
附图说明
通过下面结合附图进行的对实施例的描述,本发明的上述和/或其它目的和优点将会变得更加清楚,其中:
图1是现有技术中单级GOA电路单元的示意图;
图2是图1的下拉维持电路单元中包括的达灵顿反相器的电路图;
图3是图1的详细电路图;
图4是薄膜晶体管的等效电路图;
图5是根据本发明的示例性实施例的单级GOA电路单元的电路图;以及
图6是图5的单级GOA电路单元的信号波形图。
具体实施方式
现在将参照附图更详细地描述本公开的一个或更多个示例性实施例。相同或相对应的那些组件可以使用相同的附图标记并且省略重复的解释。
在此使用的术语仅用于描述示例实施例,发明构思不限于此。如这里使用的,除非上下文另外清楚指出,否则单数形式的“一个(种/者)”和“该(所述)”也意图包括复数形式。还将理解的是,当术语“包含”和“包括”在本说明书中使用时,说明存在所述特征、整体、步骤、操作、构件、元件和/或它们的组,但不排除存在或附加一个或更多个其他特征、整体、步骤、操作、构件、元件和/或它们的组。
为了便于之后的理解,首先对基本元件进行说明。根据本发明的示例实施例的液晶面板中的GOA电路包括多个薄膜晶体管。图4是薄膜晶体管的等效电路图,薄膜晶体管的三个电极分别称为栅极Gate、源极Source和漏极Drain,相应地,加载在各个电极上的电压可以分别标记为Vg、Vs和Vd。在这里,源 极Source和漏极Drain实际上是没有区别的,但是为了方便说明,在示例性实施例中,通常将电压较低的一端称为源极Source,将电压较高的另一端称为漏极Drain。因此,决定薄膜晶体管的导通状态的电压Vgs=Vg-Vs,当Vgs>0时,薄膜晶体管处于导通状态,电流从漏极Drain流向源极Source;当Vgs<0时器件处于截止状态。可选择地,在其他示例性实施例中,也可以将电压较低的一端称为漏极Drain,将电压较高的另一端称为源极Source,即,当薄膜晶体管处于导通状态时,电流从源极Source流向漏极Drain。
图5是根据本发明的示例性实施例的单级GOA电路单元的电路图。
参照图5,根据本发明的示例性实施例的液晶面板包括GOA电路,GOA电路包括级联的多个单级GOA电路单元,每个单级GOA电路单元包括:上拉控制电路单元1、上拉电路单元2、下拉维持电路单元3、下拉电路单元4和自举电容5。以下,将以第N级GOA电路单元的连接结构为例进行说明,其他级GOA电路单元具有类似的结构。
如图5所示,第N级GOA电路单元中的上拉控制电路单元1包括第一薄膜晶体管T11,其中,第一薄膜晶体管T11的栅极被输入第一时钟信号XCK,第一薄膜晶体管T11的漏极被输入上一级(即,第(N-1)级)GOA电路单元的扫描驱动信号G(N-1),并且第一薄膜晶体管T11的源极连接到预充电节点Q(N)。上拉控制电路单元1主要用于为预充电节点Q(N)实现预充电。
如图5所示,上拉电路单元2包括第二薄膜晶体管T21,其中,第二薄膜晶体管T21的漏极被输入与第一时钟信号XCK反相的第二时钟信号CK。上拉电路单元2主要用于提高扫描驱动信号G(N)的电位。
在本示例性实施例中,本级的上拉控制电路单元1中的第一薄膜晶体管T11的栅极被输入第一时钟信号XCK,本级的上拉电路单元2中的第二薄膜晶体管T21的漏极被输入第二时钟信号CK。然而,发明构思不限于此,根据其他示例性实施例,本级的上拉控制电路单元1中的第一薄膜晶体管T11的栅极可以被输入第二时钟信号CK,本级的上拉电路单元2中的第二薄膜晶体管T21的漏极可以被输入与第二时钟信号CK反相的第一时钟信号XCK。为了便于说明,以下将详细描述第一薄膜晶体管T11被输入第一时钟信号XCK而第二薄膜晶体管T21被输入第二时钟信号CK的示例性实施例。
如图5所示,下拉维持电路单元3由达灵顿反相器和一个第三薄膜晶体管T32组成。下拉维持电路单元3主要用于将预充电节点Q(N)、扫描驱动信号G(N)的电位维持在低电源电压VSS不变。
另外,根据本示例性实施例的液晶面板的单级GOA电路单元还包括下拉电路单元和自举电容。下拉电路单元用于将预充电节点和扫描驱动信号的电位拉低至低电位。自举电容用于维持并提高预充电节点的电位。与现有技术中的单级GOA电路单元相比,根据本发明的示例实施例的液晶面板所包括的单级GOA电路单元利用时钟信号代替来自上一级的下传信号,并且取消了如图3所示的下拉维持电路单元⑤中的薄膜晶体管T42,从而简化了电路结构,有利于实现液晶面板的窄边框设计。
下面,将参照图5详细描述根据本发明的示例性实施例的液晶面板所包括的单级GOA电路单元的结构。
与图3所示的单级GOA电路单元不同,如图5所示的单级GOA电路单元可以不包括信号下传电路单元。例如,上拉电路单元2可以仅包括第二薄膜晶体管T21。第二薄膜晶体管T21的栅极可以被连接到预充电节点Q(N)。第二薄膜晶体管T21的漏极可以被输入与第一时钟信号XCK反相的第二时钟信号CK。第二薄膜晶体管T21的源极可以被连接到本级的扫描驱动线以输出扫描驱动信号G(N)。由于根据本发明的示例性实施例的液晶面板中的单级GOA电路单元不包括信号下传电路单元,因此其不必向下一级发送下传信号,下一级的上拉控制电路单元也不再接收来自本级的下传信号,而是以接收时钟信号来代替接收下传信号,使得可以进一步简化电路结构。
在图5所示的单级GOA电路单元中,下拉维持电路单元3可以不包括薄膜晶体管T42,而是仅由达灵顿反相器和第三薄膜晶体管T32组成。例如,达灵顿反相器可以具有输入端Input和输出端Output。第三薄膜晶体管T32的栅极可以连接到达灵顿反相器的输出端Output,其漏极可以连接到输出直流的低电源电压VSS的低电源电压线,其源极可以连接到本级的扫描驱动线以输出扫描驱动信号G(N)。
图5的达灵顿反相器可以包括四个薄膜晶体管T51、T52、T53和T54,在这种情况下,薄膜晶体管T52和T54的栅极均可以连接到输入端Input,从而 均连接到预充电节点Q(N),薄膜晶体管T52和T54的漏极均可以连接到低电源电压线VSS,薄膜晶体管T54的源极可以连接到输出端Output,薄膜晶体管T52的源极可以连接到薄膜晶体管T51的源极和薄膜晶体管T53的栅极;薄膜晶体管T51和T53可以串联连接,即,薄膜晶体管T53的漏极、薄膜晶体管T51的漏极和栅极均可以被输入控制信号LC,薄膜晶体管T53的源极可以连接到输出端Output。
在本示例性实施例中,假设控制信号LC始终为高电位信号,并且低电源电压VSS始终为低电位信号,当达灵顿反相器的输入端Input被输入高电位信号时,其输出端Output输出低电位信号;当达灵顿反相器的输入端Input被输入低电位信号时,其输出端Output输出高电位信号。
如图5所示,下拉电路单元4可以包括第四薄膜晶体管T41和第五薄膜晶体管T31,其中,两个薄膜晶体管T31和T41的栅极可以彼此对接,并且可以均被输入下一级(即,第(N+1)级)GOA电路单元的扫描驱动信号G(N+1);两个薄膜晶体管T31和T41的漏极均可以连接到低电源电压线;第五薄膜晶体管T31的源极可以连接到本级的扫描驱动线以输出扫描驱动信号G(N),第四晶体管T41的源极可以连接到预充电节点Q(N)。
如图5所示,自举电容Cbt的一端可以连接到预充电节点Q(N),其另一端可以连接到本级的扫描驱动线。自举电容5是利用了电容两端电压不能突变的特性。当电容两端保持有一定电压时,提高电容负端电压,正端电压仍保持与负端的原始压差,等于正端的电压被负端举起来了。利用这种特性,自举电容Cbt可以维持并提高预充电节点Q(N)的电位。
在本发明的示例性实施例中,GOA电路中的所有薄膜晶体管可以均为高电平导通的N型薄膜晶体管,例如,高电平导通的N型非晶硅(a-Si)薄膜晶体管或NMOS薄膜晶体管。然而,发明构思不限于此,在其他示例性实施例中,GOA电路中的薄膜晶体管也可以均为低电平导通的P型薄膜晶体管,诸如PMOS薄膜晶体管。
图6是图5的单级GOA电路单元的信号波形图。下面将参照图5和图6对单级GOA电路单元的驱动方法做详细说明。
在本示例性实施例中,第二时钟信号CK可以为占空比(即,高电平在一个周期内占有的时间比值)为50%的方波信号,也可以是占空比为其他比值的信号。第二时钟信号CK与第一时钟信号XCK反相。控制信号LC可以为高电位信号,低电源电压VSS可以为低电位信号。
在本示例性实施例中,为便于说明,将描述向第二薄膜晶体管T21的漏极输入第二时钟信号CK并且向第一薄膜晶体管T11的栅极输入第一时钟信号XCK的实施例作为示例,但是发明构思不限于此,可以向第二薄膜晶体管T21的漏极输入第一时钟信号XCK并且向第一薄膜晶体管T11的栅极输入第二时钟信号CK。另外,假设第N级GOA电路单元所包括的薄膜晶体管均为高电平导通的N型薄膜晶体管。
1、在预充电时段t1期间
在上拉控制电路单元1中,由于第一时钟信号XCK为高电位,所以第一薄膜晶体管T11导通,从而上一级(即,第(N-1)级)GOA电路单元的扫描驱动信号G(N-1)的高电位从第一薄膜晶体管T11的漏极传输到与第一薄膜晶体管T11的源极连接的预充电节点Q(N),因此,预充电节点Q(N)被充入高电位,且对自举电容Cbt充电,实现预充电功能。
在上拉电路单元2中,由于预充电节点Q(N)为高电位,所以第二薄膜晶体管T21导通,从而与第一时钟信号XCK反相的第二时钟信号CK的低电位从第二薄膜晶体管T21的漏极传输到与第二薄膜晶体管T21的源极连接的扫描驱动线,即,输出低电位的扫描驱动信号G(N)。
在下拉维持电路单元3中,由于预充电节点Q(N)为高电位,即,达灵顿反相器的输入端Input被输入高电位,则输出端Output输出低电位,从而第三薄膜晶体管T32截止。
2、在输出时段t2期间
第一时钟信号XCK由高电位变为低电位,第二时钟信号CK由低电位变为高电位。在上拉控制电路单元1中,由于第一时钟信号XCK为低电位,所以第一薄膜晶体管T11截止。
在上拉电路单元2中,由于预充电节点Q(N)在自举电容Cbt的作用下被拉至某一更高电位,所以第二薄膜晶体管T21仍然导通,从而第二时钟信号CK的高电位从第二薄膜晶体管T21的漏极传输到与第二薄膜晶体管T21的源极连接的扫描驱动线,即,输出高电位的扫描驱动信号G(N)。
在下拉维持电路单元3中,由于预充电节点Q(N)为高电位,即,达灵顿反相器的输入端Input被输入高电位,则输出端Output输出低电位,从而第三薄膜晶体管T32仍然截止。
3、在复位时段t3期间
在下拉电路单元4中,由于下一级(即,第(N+1)级)GOA电路单元的扫描驱动信号G(N+1)从低电位转变为高电位,则第五薄膜晶体管T31和第四薄膜晶体管T41导通,低电源电压VSS经由第四薄膜晶体管T41传输到预充电节点Q(N),且经由第五薄膜晶体管T31传输到本级的扫描驱动线,从而预充电节点Q(N)和扫描驱动信号G(N)的电位均被拉至低电位。
在上拉控制电路单元1中,第一时钟信号XCK由t2期间的低电位再次转变为高电位,第一薄膜晶体管T11导通;此时,由于上一级(即,第(N-1)级)GOA电路单元的扫描驱动信号G(N-1)为低电位,其经由第一薄膜晶体管T11传输到预充电节点Q(N),进而使预充电节点Q(N)保持低电位。
在上拉电路单元2中,由于预充电节点Q(N)保持为低电位,所以第二薄膜晶体管T21截止。
在下拉维持电路单元3中,由于预充电节点Q(N)保持为低电位,即,反相器输入端Input被输入低电位,则输出端Output输出高电位,从而第三薄膜晶体管T32导通,低电源电压VSS经由第三薄膜晶体管T32传输到本级的扫描驱动线,即,维持扫描驱动信号G(N)的低电位。
概括而言,本申请还提供了一种包括GOA电路的液晶面板的驱动方法,该GOA电路可以具有如图5所示的电路结构,所述液晶面板的驱动方法包括:在每个单级GOA电路单元中,在预充电时段t1期间,上拉控制电路单元1在第一时钟信号XCK的控制下,将上一级GOA电路单元的扫描驱动信号G(N-1) 输入到预充电节点Q(N),且对自举电容Ct充电;在输出时段t2期间,上拉电路单元2在预充电节点Q(N)的电位和自举电容Ct的控制下,将与第一时钟信号反相的第二时钟信号CK输出到本级的扫描驱动线以输出扫描驱动信号G(N);在复位时段t3期间,下拉电路单元4在下一级GOA电路单元的扫描驱动信号G(N+1)的控制下将低电源电压VSS输入到预充电节点Q(N)和本级的扫描驱动线,以对预充电节点Q(N)和扫描驱动信号G(N)的电位进行复位(即,拉低至低电位),其中,在复位时段内,上拉控制电路单元1在第一时钟信号XCK的控制下将上一级GOA电路单元的扫描驱动信号G(N-1)输入到预充电节点Q(N)以维持预充电节点Q(N)的低电位,下拉维持电路单元3在预充电节点Q(N)的电位的控制下将低电源电压VSS输入到本级的扫描驱动线以维持扫描驱动信号G(N)的低电位。
从图5和图6的电路驱动方法可以看出,由于采取时钟信号CK和XCK来代替下传信号而输入到上拉控制电路单元,所以在单级GOA电路单元中取消信号下传单元并不会造成信号级传异常的情况。此外,尽管时钟信号CK和XCK周期性地在高、低电位之间跳变,但是在每个单级GOA电路单元中,当第一时钟信号XCK为高电位时,第一薄膜晶体管T11被导通,此时只有当上一级GOA电路单元的扫描驱动信号G(N-1)同样为高电位时,预充电节点Q(N)才会被拉至高电位;除此之外,当扫描驱动信号G(N-1)为低电位时,预充电节点Q(N)均会被拉至低电位,即,实现了下拉维持电路单元的部分功能。因此,在单级GOA电路单元中取消下拉维持电路单元中的如图3所示的薄膜晶体管T42,不会对维持预充电节点Q(N)的低电位造成影响。
综上所述,本公开提供了一种包括GOA电路的液晶面板及其驱动方法,所述GOA电路包括级联的多个单级GOA电路单元,在每个单级GOA电路单元中,完全取消了信号下传电路单元,简化了下拉维持电路单元的电路结构,改进了上拉控制电路单元的控制信号,使其同样可以起到下拉维持电路单元的部分功能,从而减少了GOA电路中使用的薄膜晶体管的数量,并且减少了信号线的数量,简化了GOA电路结构,为未来液晶面板的窄边框设计提供了新的构想和思路。
此外,除了GOA电路以外,根据本发明的示例性实施例液晶面板还可以包括偏光片、滤光片、液晶层和背光模块等本领域常见的各种元件,这里将不 再作详细阐述。
前述内容是本发明的示例且不应被解释为限制本发明。虽然已经描述了本发明的一些实施例,但是本领域技术人员将容易地理解,在实质上不脱离本发明的特征和方面的情况下,可在实施例中进行许多修改。因此,所有这样的修改意在被包括在由权利要求及其等同物限定的本发明的范围内。

Claims (10)

  1. 一种包括GOA电路的液晶面板,所述GOA电路包括级联的多个单级GOA电路单元,其中,每个单级GOA电路单元包括:
    上拉控制电路单元,包括第一薄膜晶体管,其中,第一薄膜晶体管的栅极被输入第一时钟信号,第一薄膜晶体管的漏极被输入上一级GOA电路单元的扫描驱动信号,第一薄膜晶体管的源极连接到预充电节点;
    上拉电路单元,包括第二薄膜晶体管,其中,第二薄膜晶体管的漏极被输入与第一时钟信号反相的第二时钟信号;
    下拉维持电路单元,由达灵顿反相器和一个第三薄膜晶体管组成;
    下拉电路单元,将预充电节点和扫描驱动信号的电位拉低至低电位;以及
    自举电容,维持并提高预充电节点的电位。
  2. 根据权利要求1所述的液晶面板,其中,每个单级GOA电路单元不包括信号下传电路单元。
  3. 根据权利要求1所述的液晶面板,其中,在每个单级GOA电路单元的上拉电路单元中,第二薄膜晶体管的栅极连接到预充电节点,第二薄膜晶体管的源极连接本级的扫描驱动线以输出扫描驱动信号。
  4. 根据权利要求1所述的液晶面板,其中,在每个单级GOA电路单元的下拉维持电路单元中,达灵顿反相器具有输入端和输出端,其输入端连接到预充电节点,其输出端连接到第三薄膜晶体管的栅极。
  5. 根据权利要求4所述的液晶面板,其中,在每个单级GOA电路单元的下拉维持电路单元中,第三薄膜晶体管的漏极连接到低电源电压线,其源极连接到本级的扫描驱动线以输出扫描驱动信号。
  6. 根据权利要求1所述的液晶面板,其中,在每个单级GOA电路单元中,下拉电路单元包括第四薄膜晶体管和第五薄膜晶体管,
    其中,第四和第五薄膜晶体管的栅极彼此对接,并且均被输入下一级GOA电路单元的扫描驱动信号;第四和第五薄膜晶体管的漏极均连接到低电源电压线;第四薄膜晶体管的源极连接到预充电节点,第五薄膜晶体管的源极连接到本级的扫描驱动线以输出扫描驱动信号。
  7. 根据权利要求1所述的液晶面板,其中,在每个单级GOA电路单元中,自举电容的一端连接到预充电节点,自举电容的另一端连接到本级的扫描驱动线。
  8. 根据权利要求1所述的液晶面板,其中,第一时钟信号和第二时钟信号为反相的方波信号。
  9. 根据权利要求1所述的液晶面板,其中,每个单级GOA电路单元中包括的薄膜晶体管均为高电平导通的非晶硅薄膜晶体管。
  10. 一种包括GOA电路的液晶面板的驱动方法,其中,所述液晶面板采用权利要求1所述的液晶面板,所述驱动方法包括:
    在每个单级GOA电路单元中,
    在预充电时段,上拉控制电路单元在第一时钟信号的控制下,将上一级GOA电路单元的扫描驱动信号输入到预充电节点,且对自举电容充电;
    在输出时段,上拉电路单元在预充电节点的电位和自举电容的控制下,将与第一时钟信号反相的第二时钟信号输出到本级的扫描驱动线以输出扫描驱动信号;
    在复位时段,下拉电路单元在下一级GOA电路单元的扫描驱动信号的控制下将低电源电压输入到预充电节点和本级的扫描驱动线,以对预充电节点和扫描驱动信号的电位进行复位,
    其中,在复位时段内,上拉控制电路单元在第一时钟信号的控制下将上一级GOA电路单元的扫描驱动信号输入到预充电节点以维持预充电节点的低电位,下拉维持电路单元在预充电节点的电位的控制下将低电源电压输入到本级的扫描驱动线以维持扫描驱动信号的低电位。
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