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WO2015105149A1 - 半導体装置の実装方法および実装装置 - Google Patents

半導体装置の実装方法および実装装置 Download PDF

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Publication number
WO2015105149A1
WO2015105149A1 PCT/JP2015/050380 JP2015050380W WO2015105149A1 WO 2015105149 A1 WO2015105149 A1 WO 2015105149A1 JP 2015050380 W JP2015050380 W JP 2015050380W WO 2015105149 A1 WO2015105149 A1 WO 2015105149A1
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WO
WIPO (PCT)
Prior art keywords
substrate
thermosetting resin
mounting
semiconductor device
plate
Prior art date
Application number
PCT/JP2015/050380
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English (en)
French (fr)
Japanese (ja)
Inventor
昇 朝日
芳範 宮本
敏史 竹上
Original Assignee
東レ株式会社
東レエンジニアリング株式会社
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 東レ株式会社, 東レエンジニアリング株式会社 filed Critical 東レ株式会社
Priority to JP2015556832A priority Critical patent/JP6461822B2/ja
Priority to KR1020167018167A priority patent/KR20160105415A/ko
Publication of WO2015105149A1 publication Critical patent/WO2015105149A1/ja

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Definitions

  • the present invention is a semiconductor in which a semiconductor device such as an IC or LSI is bonded to a circuit board such as a flexible board, a glass epoxy board, a glass board, a ceramic board, a silicon interposer, or a silicon board and directly mounted in an electrically bonded or laminated state.
  • the present invention relates to a device mounting method and a mounting device.
  • a method has been proposed in which a semiconductor chip or a substrate with a bump on which an adhesive has been formed in advance is flip-chip connected to perform electrical bonding and resin sealing at the same time.
  • a substrate on which a semiconductor device is temporarily mounted via an insulating adhesive is placed on a substrate holding plate that is spring-biased upward from the lower die and separated from the lower die, and the upper die with a built-in heater is used as the substrate. Proximity to face. In this state, the substrate is preheated by radiant heat from the upper die, and then the upper die is lowered to fix the semiconductor device to the substrate while pressing and heating (see Patent Document 1).
  • the semiconductor device when the semiconductor device is pushed into the insulating adhesive on the substrate held away from the lower mold, heat from the upper mold is transferred first, so the substrate reaches the lower mold depending on the type of insulating adhesive. Then, the insulating adhesive is cured before pressing is started in a supported state. As a result, the insulating adhesive is hardened before the bumps reach the electrodes on the substrate, causing a problem that electrical connection cannot be ensured.
  • the present invention has been made in view of such circumstances, and a main object thereof is to provide a semiconductor device mounting method and a mounting apparatus capable of mounting a semiconductor device on a substrate with high accuracy in a short time.
  • This invention has the following configuration in order to achieve such an object.
  • thermosetting resin a mounting method for mounting a semiconductor device having bumps on a substrate via a thermosetting resin
  • the semiconductor device With the heat conduction delay plate interposed between the holding stage and the semiconductor device, the semiconductor device is added by the pressing member while the holding stage is heated by the first heater above the curing temperature of the thermosetting resin.
  • the bumps are connected to the electrodes of the substrate, the thermosetting resin is cured, and the pressure bonding is performed to the substrate.
  • the heat conducted from the holding stage to the substrate can be delayed by interposing the plate between the holding stage and the substrate. Therefore, after the plate and the substrate are placed and held on the holding stage, the thermosetting resin can be suppressed from being cured until the semiconductor device is pressurized by the pressing member. As a result, after securely connecting the bumps of the semiconductor device and the electrodes of the substrate, the thermosetting resin can be cured and finally bonded (fixed) to the substrate.
  • the holding stage is equal to or higher than the curing temperature of the thermosetting resin
  • the temperature transmitted to the substrate is adjusted to the curing temperature of the physical properties and the delay time is adjusted in consideration of heat conduction by the plate. Can do.
  • the plate may be interposed between the holding table and the substrate as follows.
  • the substrate on which the semiconductor device is temporarily press-bonded with the uncured thermosetting resin is transferred onto the plate.
  • a substrate on which a semiconductor device is temporarily press-bonded with the uncured thermosetting resin and a plate for heat conduction delay may be overlapped and conveyed to a holding stage.
  • the superposition of the substrate and the heat conduction delay plate may be merely superposition, for example.
  • the substrate and the heat conduction delay plate may be bonded in advance with a double-sided adhesive tape or an adhesive.
  • solder when solder is provided as a bump, it is preferable to set the temperature so that the solder of the bump is melt bonded to the electrode of the substrate before the thermosetting resin is cured.
  • the electrode of the substrate and the bump can be reliably electrically connected.
  • the plate is cooled after the substrate after the main-bonding process is carried out from the holding stage until the new substrate to be processed is placed on the plate.
  • thermosetting resin When reusing a plate, when a new substrate to be processed is placed on the plate, it is possible to prevent the thermosetting resin from being cured by the residual heat accumulated in the plate during the previous processing.
  • the present invention has the following configuration in order to achieve such an object.
  • a mounting device for mounting a semiconductor device having bumps on a substrate via a thermosetting resin, Holding stage;
  • a first heater for heating the holding stage;
  • a transport mechanism for transporting a substrate on which a semiconductor device is temporarily pressure-bonded by the uncured thermosetting resin onto the plate after transporting the heat conduction delay plate to the holding stage;
  • a pressure-bonding mechanism that presses the semiconductor device on the substrate placed and held in the order of the plate and the substrate on the holding stage with a pressing member;
  • a control unit for controlling the temperature of the holding stage to be equal to or higher than the curing temperature of the thermosetting resin by the first heater; It is provided with.
  • the plate is placed and held on the holding stage in a heated state by the transport mechanism, and the substrate is placed and held on the plate.
  • heat transfer from the holding stage to the substrate is delayed by the plate. That is, the said structure can implement the said method suitably.
  • a mounting device for mounting a semiconductor device having a bump on a substrate via a thermosetting resin, Holding stage; A first heater for heating the holding stage; A transport mechanism for transporting a heat conduction delay plate superimposed on a substrate on which a semiconductor device is temporarily press-bonded with the uncured thermosetting resin; A pressure-bonding mechanism that presses the semiconductor device of the substrate placed and held on the holding stage with a pressing member; A control unit for controlling the temperature of the holding stage to be equal to or higher than the curing temperature of the thermosetting resin by the first heater; It is provided with.
  • the said structure can implement the said method suitably.
  • the substrate and the plate can be transported integrally, when the substrate is a semiconductor wafer, the thinned semiconductor wafer can be reinforced. Therefore, it is possible to suppress the substrate from being bent during the conveyance process and the semiconductor device on the substrate from being damaged. Further, the processing time can be shortened as compared with the case where the plate and the substrate are individually conveyed.
  • the pressing member includes a second heater
  • the controller preferably controls the temperature of the pressing member to be equal to or higher than the curing temperature of the thermosetting resin by the second heater.
  • the substrate can be pressurized and heated while being sandwiched between the holding stage and the pressing member via the plate. Therefore, the delay time of the heat transfer to the thermosetting resin on the substrate can be adjusted in a short time.
  • the residual heat accumulated in the plate can be removed. Accordingly, it is possible to avoid curing of the thermosetting resin due to residual heat before pressurizing the semiconductor device to the substrate.
  • thermosetting resin it is possible to suppress the thermosetting resin from being cured until the semiconductor device on the substrate placed and held on the heated holding stage is pressurized. it can. That is, the thermosetting resin can be cured at high speed and securely fixed to the substrate in a state where the electrical connection between the substrate and the bump is securely connected.
  • thermosetting resin is preferably NCF (non-conductive adhesive film).
  • the “semiconductor device” in the present invention includes bumps such as an IC chip, a semiconductor chip, an optical element, a surface mount component, a chip, a wafer, TCP (Tape Carrier Package), FPC (Flexible Printed Circuit), etc. is there. Further, these semiconductor devices show all forms on the side to be bonded to the substrate regardless of the type and size. For example, COG (Chip On Glass), which is chip bonding to a flat display panel, TCP, OLB (Outer Lead On Bonding), which is FPC bonding, and the like are used.
  • substrate for example, a flexible substrate, a glass epoxy substrate, a glass substrate, a ceramic substrate, a silicon interposer, a silicon substrate, or the like is used.
  • FIG. 1 is a perspective view showing a schematic configuration of a main crimping device constituting a mounting device according to the present invention
  • FIG. 2 is a plan view showing a main configuration of the mounting device
  • FIG. 3 shows a main configuration of the mounting device.
  • the mounting apparatus includes a transport mechanism 1 and a main crimping apparatus 2.
  • a transport mechanism 1 As shown in FIGS. 1 and 2, the mounting apparatus according to the present invention includes a transport mechanism 1 and a main crimping apparatus 2.
  • a main crimping apparatus 2 As shown in FIGS. 1 and 2, the mounting apparatus according to the present invention includes a transport mechanism 1 and a main crimping apparatus 2.
  • the transport mechanism 1 includes a movable table 3 and a transport arm 4.
  • the movable table 3 is configured to move in the horizontal axis direction along the guide rail 5.
  • the transfer arm 4 is connected at its base end side to the lifting / lowering drive mechanism of the movable table 3 and is configured to be movable in the vertical (Z) direction and the Z axis ( ⁇ ) direction.
  • the transfer arm 4 includes a holding frame 6 at the tip. As shown in FIGS. 2 and 3, the holding frame 6 has a horseshoe shape, and includes a plurality of locking claws 7 for locking the plate for heat conduction delay and the substrate W at the corners.
  • the main crimping device 2 includes a movable table 8 and a pressing mechanism 9.
  • the movable table 8 includes a holding stage 10 that holds the substrate W by suction.
  • the holding stage 10 is configured to be movable in two horizontal axes (X, Y), up and down (Z), and around the Z axis ( ⁇ ).
  • the outer shape of the holding stage 10 is set to a size that fits inside the holding frame 6.
  • the holding stage 10 has a heater 11 embedded therein.
  • the heater 11 corresponds to the first heater of the present invention.
  • the pressing mechanism 9 includes a cylinder 13 and a pressure bonding head 14. That is, the cylinder 13 is connected to the upper side of the crimping head 14 so that the crimping head 1314 moves up and down.
  • the pressure bonding head 14 has a downward convex shape and extends in the alignment direction of the plurality of semiconductor devices C aligned on the edge side of the substrate W. In other words, the plurality of semiconductor devices C are simultaneously pressurized by the tips of the convex portions.
  • a heater 15 is embedded in the crimping head 14.
  • the crimping head 14 corresponds to a pressing member of the present invention, and the heater 15 corresponds to a second heater.
  • the controller 20 adjusts the temperature of the heaters 11 and 15 so that the temperature of the heater 15 of the crimping head 14 and the heater 11 of the holding stage 10 is maintained at a temperature equal to or higher than the temperature at which the thermosetting resin G is cured. I have control.
  • thermosetting resin is completely cured with respect to the one in which a plurality of semiconductor devices C are transported in a pre-press-bonded state to the substrate W by NCF in the temporary press-bonding step of the previous step.
  • the case of crimping will be described as an example.
  • the temperature of both heaters 11 and 15 provided in the holding stage 10 and the pressure bonding head 14 is set by operating the operation unit 21.
  • the temperatures of both heaters 11 and 15 are set such that the temperature at the interface between the plate P and the substrate W for delaying heat conduction and the interface between the pressure bonding head 14 and the semiconductor device C are higher than the curing temperature of the thermosetting resin G.
  • the curing temperature is set (step S1).
  • the plate P is set so that, for example, the relationship between the heat transfer coefficient (W / m ⁇ K) L and the plate thickness (mm) T, that is, L / T is 1 or more and 20 or less.
  • the plate P is not limited to stainless steel, and may be any material that is not deformed by the pressing of the pressure-bonding head 14, and may be a metal, ceramic, carbon, a porous material, or the like.
  • step S2 When the initial setting is completed, the device is operated (step S2). On the main crimping apparatus side, the control unit 20 turns on the heaters 11 and 15 and starts temperature control so as to keep the preset temperature constant.
  • the plate P is placed on the holding frame 6 of the transport mechanism 1 by the transport robot (not shown) arranged on the temporary press-bonding process side, and then the substrate W is placed on the plate P. (Step S3).
  • the plate P and the substrate W are conveyed to the main crimping apparatus 2.
  • the substrate W is transferred to the holding stage 10 as indicated by the two-dot chain line in FIG.
  • a plurality of through holes are formed in the plate P and are sucked and held by the holding stage 10 through the through holes (step S4).
  • the holding stage 10 is moved to a predetermined mounting position below the pressure-bonding head 14 which is the front (Y direction in FIG. 1) by a driving mechanism (not shown).
  • the heating is started by the heater 11 from the time when the plate P and the substrate W are attracted and held on the holding stage 10 (step S5).
  • the crimping head 14 When the holding stage 10 reaches the mounting position, as shown in FIG. 6, the crimping head 14 is lowered by the operation of the cylinder 13, and a plurality of semiconductor devices C are sandwiched simultaneously. At this time, the semiconductor device C is pressed while being heated by the heated crimping head 14 (step S6).
  • thermosetting resin G when the pressure bonding head 14 is lowered to a predetermined height, the thermosetting resin G is in an uncured state, so that the bump B of the semiconductor device C is heated by the pressure of the pressure bonding head 14 as shown in FIG. It is pushed into the curable resin G. That is, after the bump B of the semiconductor device C reaches the electrode of the substrate W, the thermosetting resin is cured.
  • step S7 When the semiconductor device C is pressurized and heated until a predetermined time until the thermosetting resin G is completely cured (step S7), the pressure bonding head 14 is returned to the upper standby position to release the pressure, and the transport mechanism 1 The plate P and the substrate W are carried out (step S8).
  • the plate P and the substrate W are transported to a predetermined position, they are transferred to another transport robot or stored in a stocker.
  • the heat conduction delay plate P is placed on the holding stage maintained at a temperature equal to or higher than the curing temperature of the thermosetting resin G, and the temporarily bonded substrate W of the semiconductor device C is sucked and held. Therefore, the thermosetting resin G is not cured until the pressure-bonding head 14 is lowered and fully pressurized. That is, in this embodiment, as shown by the solid line in FIG. 8, pressurization is started by bringing the pressure-bonding head 14 into contact with the semiconductor device C from time T1 when the plate P and the substrate W are placed and held on the holding stage 10.
  • the temperature gradient up to the time point T2 (for example, set at the time of the solder melting temperature in this embodiment) is smaller than the temperature gradient of the conventional method indicated by the one-dot chain line without the plate P interposed therebetween, and the thermosetting resin G It is possible to keep the temperature lower than the curing temperature.
  • the pressure bonding head 14 since the temperature gap until the press of the semiconductor device C by the pressure bonding head 14 is larger than that in the conventional method, the pressure bonding head 14 is lowered to a predetermined height and the bump B of the semiconductor device C is used as the electrode of the substrate W.
  • the thermosetting resin G can be kept in an uncured state. As a result, the electrical connection between the electrode of the substrate W and the bump B can be ensured.
  • the curing temperature of the thermosetting resin G can be measured by DSC (differential scanning calorimetry).
  • the present invention is not limited to the embodiment described above, and can be modified as follows.
  • the pressure-bonding head 14 of the above-described embodiment apparatus can be used for a single type for main-bonding one semiconductor device C or a multi-type having a plurality of the single types as shown in FIG. it can.
  • the temperatures of the heaters 11 and 15 provided in the holding stage 10 and the pressure-bonding head 14 are set to be the same, but the temperature may be set as follows, for example.
  • the time during which heat is transmitted to the thermosetting resin G through the semiconductor device C from the start of pressurization of the semiconductor device C by the crimping head 14 and the heat to the thermosetting resin G through the substrate W and the plate P may be appropriately changed so that the time for transmission is the same.
  • the temperature transmission time may be adjusted not only by the temperature setting of the heaters 11 and 15 but also by the thickness of the plate P. According to this method, it is possible to suppress warpage of the substrate W that may be caused by a difference in heat transfer between the substrate W and the semiconductor device C.
  • the bump B of the semiconductor device has a configuration in which the solder ball or the copper electrode pillar is soldered
  • the bump pressed into the thermosetting resin G by the press contacts the electrode of the substrate W, What is necessary is just to control temperature so that the thermosetting resin G will be in an unhardened state for the time from a contact state to a solder melt-bonding.
  • the holding stage 10 is configured to be movable by the movable table 8, but may be a fixed configuration. In this case, it is only necessary that the alignment is maintained when the plate P and the substrate W are transported by the holding frame 6. Further, the plate P may be fixed or integrally formed with the holding frame 6. Therefore, in the present invention, it is sufficient that the plate P and the substrate W are stacked and held on the holding stage 6 in this order. It may be placed on the holding stage 10 first.
  • one substrate W is used, but a substrate W before break in which a plurality of substrates W are connected may be used.
  • the plurality of substrates W may be placed on a plate having a size corresponding to the substrate W before the break, and the main bonding may be performed while shifting the substrate below the pressure bonding head.
  • the plate P and the substrate W are placed on the holding stage 10 at the same time, but they may be transported and placed individually. In this case, the substrate W is placed after the plate P is placed on the holding stage 10.
  • the plate P when the plate P is reused, the plate P may be cooled by a cooler after the main pressure bonding process and before the new substrate W is placed on the plate P. What is necessary is just to comprise a cooler, for example so that air may be sprayed with a nozzle.
  • the plate P may be attached in advance to the substrate W with an adhesive as shown in FIGS.
  • the size of the plate P may be the same shape as the substrate W and the same size or larger than the substrate.
  • a plate what was shape
  • the substrate W with reduced rigidity can be reinforced. That is, when the substrate W is transported, the semiconductor device C can be prevented from being bent due to the substrate W being bent.
  • the number of conveyances to the holding stage 10 can be reduced compared to the processing of the above embodiment. That is, in step S3 shown in FIG. 4, the plate-equipped substrate W only needs to be transported and placed on the holding stage 10 only once. Further, in step S8, the substrate W with the plate may be carried out only once from the holding stage 10 after the main pressure bonding. Therefore, this embodiment can improve the processing speed.
  • substrate W with a plate may convey the said board
  • the substrate W and the plate P may be transported in a state where they are simply overlapped.
  • the substrate W and the plate P carried out from the holding stage 10 may be cooled.
  • air may be blown to the holding plate P during the conveyance process or at a predetermined position.
  • the present invention is suitable for curing a thermosetting resin while electrically connecting a semiconductor device and an electrode of a substrate with high accuracy.

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  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Manufacturing & Machinery (AREA)
  • Wire Bonding (AREA)
PCT/JP2015/050380 2014-01-08 2015-01-08 半導体装置の実装方法および実装装置 WO2015105149A1 (ja)

Priority Applications (2)

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Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2003249532A (ja) * 2002-02-26 2003-09-05 Seiko Epson Corp 実装構造体及びその製造方法及びその製造装置並びに電子機器
JP2010010628A (ja) * 2008-06-30 2010-01-14 Nikon Corp 接合装置および接合方法
JP2010114208A (ja) * 2008-11-05 2010-05-20 Nikon Corp 冷却装置および接合システム
JP2010245195A (ja) * 2009-04-02 2010-10-28 Nec Corp 半導体装置の製造装置及び半導体装置の製造方法
WO2011089863A1 (ja) * 2010-01-22 2011-07-28 ソニーケミカル＆インフォメーションデバイス株式会社 加熱装置および実装体の製造方法

Family Cites Families (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP4832107B2 (ja) * 2006-02-23 2011-12-07 ソニーケミカル＆インフォメーションデバイス株式会社 実装方法
JP2008294396A (ja) * 2007-04-23 2008-12-04 Hitachi Chem Co Ltd 接続方法、接続装置及び接続方法を用いて得られる接続構造体
JP5401709B2 (ja) 2010-02-02 2014-01-29 アピックヤマダ株式会社 半導体装置の接合装置及び接合方法
JP5892682B2 (ja) * 2011-04-27 2016-03-23 アピックヤマダ株式会社 接合方法

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2003249532A (ja) * 2002-02-26 2003-09-05 Seiko Epson Corp 実装構造体及びその製造方法及びその製造装置並びに電子機器
JP2010010628A (ja) * 2008-06-30 2010-01-14 Nikon Corp 接合装置および接合方法
JP2010114208A (ja) * 2008-11-05 2010-05-20 Nikon Corp 冷却装置および接合システム
JP2010245195A (ja) * 2009-04-02 2010-10-28 Nec Corp 半導体装置の製造装置及び半導体装置の製造方法
WO2011089863A1 (ja) * 2010-01-22 2011-07-28 ソニーケミカル＆インフォメーションデバイス株式会社 加熱装置および実装体の製造方法

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JPWO2015105149A1 (ja) 2017-03-23

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