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US20160020236A1 - Solid-state imaging device, method of manufacturing the same, and electronic apparatus - Google Patents

Solid-state imaging device, method of manufacturing the same, and electronic apparatus Download PDF

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Publication number
US20160020236A1
US20160020236A1 US14/772,196 US201414772196A US2016020236A1 US 20160020236 A1 US20160020236 A1 US 20160020236A1 US 201414772196 A US201414772196 A US 201414772196A US 2016020236 A1 US2016020236 A1 US 2016020236A1
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United States
Prior art keywords
epitaxial layer
photodiode
solid
imaging device
state imaging
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US14/772,196
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English (en)
Inventor
Yosuke Tanaka
Toshifumi Wakano
Keiji Tatani
Takashi Nagano
Hayato Iwamoto
Keiichi Nakazawa
Tomoyuki Hirano
Shinpei Yamaguchi
Shunsuke Maruyama
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Sony Corp
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Sony Corp
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Assigned to SONY CORPORATION reassignment SONY CORPORATION ASSIGNMENT OF ASSIGNORS INTEREST (SEE DOCUMENT FOR DETAILS). Assignors: YAMAGUCHI, SHINPEI, IWAMOTO, HAYATO, TANAKA, YUSUKE, NAKAZAWA, KEIICHI, HIRANO, TOMOYUKI, MARUYAMA, SHUNSUKE, NAGANO, TAKASHI, TATANI, KEIJI, WAKANO, TOSHIFUMI
Publication of US20160020236A1 publication Critical patent/US20160020236A1/en
Abandoned legal-status Critical Current

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/14—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation
    • H01L27/144—Devices controlled by radiation
    • H01L27/146—Imager structures
    • H01L27/14601—Structural or functional details thereof
    • H01L27/14609—Pixel-elements with integrated switching, control, storage or amplification elements
    • H01L27/14612—Pixel-elements with integrated switching, control, storage or amplification elements involving a transistor
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/14—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation
    • H01L27/144—Devices controlled by radiation
    • H01L27/146—Imager structures
    • H01L27/14601—Structural or functional details thereof
    • H01L27/14609—Pixel-elements with integrated switching, control, storage or amplification elements
    • H01L27/1461—Pixel-elements with integrated switching, control, storage or amplification elements characterised by the photosensitive area
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/14—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation
    • H01L27/144—Devices controlled by radiation
    • H01L27/146—Imager structures
    • H01L27/14601—Structural or functional details thereof
    • H01L27/14609—Pixel-elements with integrated switching, control, storage or amplification elements
    • H01L27/14612—Pixel-elements with integrated switching, control, storage or amplification elements involving a transistor
    • H01L27/14614—Pixel-elements with integrated switching, control, storage or amplification elements involving a transistor having a special gate structure
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/14—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation
    • H01L27/144—Devices controlled by radiation
    • H01L27/146—Imager structures
    • H01L27/14601—Structural or functional details thereof
    • H01L27/14638—Structures specially adapted for transferring the charges across the imager perpendicular to the imaging plane
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/14—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation
    • H01L27/144—Devices controlled by radiation
    • H01L27/146—Imager structures
    • H01L27/14601—Structural or functional details thereof
    • H01L27/1464—Back illuminated imager structures
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/14—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation
    • H01L27/144—Devices controlled by radiation
    • H01L27/146—Imager structures
    • H01L27/14643—Photodiode arrays; MOS imagers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/14—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation
    • H01L27/144—Devices controlled by radiation
    • H01L27/146—Imager structures
    • H01L27/14683—Processes or apparatus peculiar to the manufacture or treatment of these devices or parts thereof
    • H01L27/14689—MOS based technologies
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/14—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation
    • H01L27/144—Devices controlled by radiation
    • H01L27/146—Imager structures
    • H01L27/14601—Structural or functional details thereof
    • H01L27/1462—Coatings
    • H01L27/14621—Colour filter arrangements
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/14—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation
    • H01L27/144—Devices controlled by radiation
    • H01L27/146—Imager structures
    • H01L27/14601—Structural or functional details thereof
    • H01L27/14625—Optical elements or arrangements associated with the device
    • H01L27/14627—Microlenses
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/14—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation
    • H01L27/144—Devices controlled by radiation
    • H01L27/146—Imager structures
    • H01L27/14601—Structural or functional details thereof
    • H01L27/14641—Electronic components shared by two or more pixel-elements, e.g. one amplifier shared by two pixel elements
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/14—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation
    • H01L27/144—Devices controlled by radiation
    • H01L27/146—Imager structures
    • H01L27/14643—Photodiode arrays; MOS imagers
    • H01L27/14645—Colour imagers
    • H01L27/14647—Multicolour imagers having a stacked pixel-element structure, e.g. npn, npnpn or MQW elements

Definitions

  • the present disclosure relates to a solid-state imaging device and a method of manufacturing the same, and an electronic apparatus.
  • the present disclosure relates to a solid-state imaging device capable of further improving the amount of saturation charge and sensitivity characteristics, a method of manufacturing the same, and an electronic apparatus.
  • solid-state imaging devices such as a Charge Coupled Device (CCD) or Complementary Metal Oxide Semiconductor (CMOS) image sensor
  • CCD Charge Coupled Device
  • CMOS Complementary Metal Oxide Semiconductor
  • CMOS image sensor a technology sharing pixels is often employed in order to maximize the photodiode aperture ratio accompanying increased miniaturization of the pixel size.
  • a transistor is shared among a plurality of pixels, and the area of the photodiode is secured by minimizing the area occupied by the elements other than the photodiode in the pixel portion. Then, it is possible to improve, for example, the amount of saturation signal and the sensitivity characteristics of the photodiode by using the pixel sharing technology.
  • the transistors necessary for driving the photodiodes and the pixels are formed on the same plane as the silicon substrate, and the sensor is constrained in terms of area in order to secure the characteristics of the lower limits thereof. For example, if the photodiode area is expanded in order to improve the amount of saturation charge and the sensitivity characteristics of the photodiode, because the region of the transistors accompanying this is reduced, random noise caused by the transistors worsens, and the gain of the circuit lowers. On the other hand, when the area of the transistors is secured, the amount of saturation charge and the sensitivity characteristics of the photodiode are lowered. Accordingly, there is demand for improving the amount of saturation signal and the sensitivity characteristics of the photodiode without reducing the area of the transistors.
  • a solid-state imaging device with a silicon substrate. At least a first photodiode is formed in the silicon substrate. An epitaxial layer, with a first surface adjacent to a surface of the silicon substrate, and a transfer transistor, with a gate electrode that extends from the at least a first photodiode to a second surface of the epitaxial layer opposite the first surface are also included.
  • the solid-state imaging device includes a floating diffusion that is formed in the epitaxial layer and that is in electrical contact with the gate electrode of the transfer transistor.
  • a plurality of pixel transistors formed on the epitaxial layer can also be included.
  • the plurality of pixel transistors can overlay at least a portion of the silicon substrate in which the at least a first photodiode is formed.
  • the solid-state imaging device can further include a second photodiode that is formed in the epitaxial layer.
  • the second photodiode can be in electrical contact with the gate electrode of the transfer transistor.
  • a plurality of photodiodes can be formed in the epitaxial layer.
  • the first photodiode and the photodiodes formed in the epitaxial layer can be in electrical contact with the gate electrode of the transfer transistor.
  • a plurality of pinning layers can be provided, and the plurality of photodiodes formed in the epitaxial layer can be laminated in a depth direction with the plurality of pinning layers.
  • an area of at least one of the plurality of photodiodes formed in the epitaxial layer can have an area in a plane parallel to the first surface of the epitaxial layer that is different than at least one or the other of the plurality of photodiodes formed in the epitaxial layer.
  • the photodiodes formed in the epitaxial layer can overlay at least a portion of the photodiodes formed in the silicon substrate.
  • a floating diffusion can also be included, with at least a portion of the floating diffusion overlaying at least a portion of the first photodiode.
  • the solid-state imaging device can further include a plurality of pixel transistors that are formed on the epitaxial layer and that overlay at least a portion of the first photodiode.
  • a solid-state imaging device includes a plurality of pixels, wherein each pixel in the plurality of pixels is formed in a semiconductor substrate, and wherein the pixels are symmetrical with respect to a center point.
  • the solid-state imaging device also includes an epitaxial layer on the semiconductor substrate, and a floating diffusion formed in the epitaxial layer.
  • a plurality of transfer gate electrodes are also provided, with each of the pixels electrically connected to the floating diffusion by one of the transfer gate electrodes.
  • the plurality of pixels are arranged symmetrically about the floating diffusion.
  • the solid-state imaging device can also include a plurality of pixel transistors formed in the epitaxial layer.
  • the plurality of transfer gate electrodes can be arranged symmetrically about the floating diffusion.
  • a method of producing a solid-state imaging device includes forming a photodiode in a silicon substrate, and forming an epitaxial layer on the silicon substrate.
  • the method further includes forming an excavated portion by excavating from a surface of the epitaxial layer to the silicon substrate, wherein the excavated portion reaches a p-well surrounding n type regions of the photodiode.
  • the method includes forming a gate electrode by forming a gate oxide film on an inside surface of the excavated portion.
  • an electronic apparatus that includes an optical system.
  • an image capture element that includes a solid-state imaging device that receives light from the optical system.
  • a solid-state imaging device of the apparatus includes an on-chip lens, an antireflection film, and a silicon substrate, wherein the antireflection film is connected to the first surface of the silicon substrate, and wherein the on-chip lens is separated from the first surface of the silicon substrate by at least the antireflection film.
  • At least a first photodiode is formed in the silicon substrate.
  • An epitaxial layer with a first surface adjacent a surface of the silicon substrate is also provided.
  • the solid-state imaging device further includes a transfer transistor, wherein a gate electrode of the transfer transistor extends from at least a first photodiode to a second surface of the epitaxial layer opposite the first surface.
  • the apparatus additionally includes a signal processing circuit that receives a signal from the image capture element.
  • an electronic apparatus includes an optical system, and an image capture element including a solid-state imaging device that receives light from the optical system.
  • the solid-state imaging device includes a plurality of pixels formed in a semiconductor substrate, wherein the pixels are symmetrical with respect to a center point.
  • the solid-state imaging device also includes an epitaxial layer on the semiconductor substrate, and a floating diffusion formed in the epitaxial layer.
  • a plurality of transfer gate electrodes is included, with each of the pixels electrically connected to the floating diffusion by one of the transfer gate electrodes.
  • the apparatus further includes a signal processing circuit that receives a signal from the image capture element.
  • FIG. 1 is a cross-sectional view showing a configuration example of a first embodiment of a pixel having a solid-state imaging device to which the present technology is applied.
  • FIG. 2A is a plan view showing a structure of a pixel in which a 4 -pixel shared structure is employed.
  • FIG. 2B is a plan view showing a structure of a pixel in which a 4 -pixel shared structure is employed.
  • FIG. 3A is a plan view showing a structure of a pixel of the related art.
  • FIG. 3B is a cross-sectional view showing a structure of a pixel of the related art.
  • FIG. 4 is a cross-sectional view showing a configuration example of a first embodiment of a pixel.
  • FIG. 5 is a cross-sectional view showing a configuration example of a second embodiment of a pixel.
  • FIG. 6 is a cross-sectional view showing a configuration example of a third embodiment of a pixel.
  • FIG. 7 is a cross-sectional view showing a configuration example of a fourth embodiment of a pixel.
  • FIG. 8 is a cross-sectional view showing a configuration example of a fifth embodiment of a pixel.
  • FIG. 9 is a cross-sectional view showing a configuration example of a sixth embodiment of a pixel.
  • FIG. 10 is a cross-sectional view showing a configuration example of a seventh embodiment of a pixel.
  • FIG. 11 is a cross-sectional view describing a first step.
  • FIG. 12 is a cross-sectional view describing a second step.
  • FIG. 13 is a cross-sectional view describing a third step.
  • FIG. 14 is a cross-sectional view describing a fourth step.
  • FIG. 15 is a cross-sectional view describing a fifth step.
  • FIG. 16 is a cross-sectional view describing a sixth step.
  • FIG. 17 is a cross-sectional view describing a seventh step.
  • FIG. 18 is a cross-sectional view describing an eighth step.
  • FIG. 19 is a cross-sectional view describing a ninth step.
  • FIG. 20 is a cross-sectional view describing a tenth step.
  • FIG. 21 is a cross-sectional view describing an eleventh step.
  • FIG. 22 is a cross-sectional view describing a twelfth step.
  • FIG. 23 is a cross-sectional view showing a configuration example of an eighth embodiment of a pixel.
  • FIG. 24 is a diagram showing an SOI substrate used in a structure of a solid-state imaging device.
  • FIG. 25 is a cross-sectional view describing a twenty-first step.
  • FIG. 26 is a cross-sectional view describing a twenty-second step.
  • FIG. 27 is a cross-sectional view describing a twenty-third step.
  • FIG. 28 is a cross-sectional view describing a twenty-fourth step.
  • FIG. 29 is a cross-sectional view describing a twenty-fifth step.
  • FIG. 30 is a cross-sectional view describing a twenty-sixth step.
  • FIG. 31 is a cross-sectional view describing a twenty-seventh step.
  • FIG. 32 is a plan view describing a twenty-seventh step.
  • FIG. 33 is a cross-sectional view describing a twenty-eighth step.
  • FIG. 34 is a plan view describing a twenty-eighth step.
  • FIG. 35 is a cross-sectional view describing a twenty-ninth step.
  • FIG. 36 is a cross-sectional view describing a thirtieth step.
  • FIG. 37 is a cross-sectional view describing a thirty-first step.
  • FIG. 38 is a cross-sectional view describing a thirty-second step.
  • FIG. 39 is a cross-sectional view describing a thirty-third step.
  • FIG. 40 is a cross-sectional view describing a thirty-fourth step.
  • FIG. 41 is a cross-sectional view describing a thirty-fifth step.
  • FIG. 42 is a cross-sectional view describing a thirty-sixth step.
  • FIG. 43 is a cross-sectional view describing a thirty-seventh step.
  • FIG. 44 is a cross-sectional view describing a thirty-eighth step.
  • FIG. 45 is a cross-sectional view showing a configuration example of a ninth embodiment of a pixel.
  • FIG. 46 is a cross-sectional view describing a forty-first step.
  • FIG. 47 is a cross-sectional view describing a forty-second step.
  • FIG. 48 is a cross-sectional view describing a forty-third step.
  • FIG. 49 is a cross-sectional view describing a forty-fourth step.
  • FIG. 50 is a cross-sectional view showing a configuration example of a tenth embodiment of a pixel.
  • FIG. 51 is a cross-sectional view showing a configuration example of an eleventh embodiment of a pixel.
  • FIG. 52 is a cross-sectional view showing a configuration example of a twelfth embodiment of a pixel.
  • FIG. 53 is a block diagram showing a configuration example of an imaging device mounted in an electronic apparatus.
  • FIG. 1 is a cross-sectional view showing a configuration example of a first embodiment of a pixel having a solid-state imaging device to which the present technology is applied. Moreover, in FIG. 1 , the upper side of FIG. 1 is set as the rear face side of the solid-state imaging device 1 , and the lower side of FIG. 1 is set as the front face side of the solid-state imaging device 1 .
  • the solid-state imaging device 1 is formed such that the pixel transistor region 2 and photodiode region 3 are separated in the depth direction (vertical direction in FIG. 1 ) of the solid-state imaging device 1 .
  • the solid-state imaging device 1 is configured by layering, in order from the lower side of FIG. 1 , a P-type epitaxial layer 21 , a silicon substrate 22 , an anti-reflection film 23 , a color filter layer 24 and an on-chip lens 25 . Then, in the solid-state imaging device 1 , a pixel transistor 32 is provided on the P-type epitaxial layer 21 for each pixel 11 , and a photodiode 33 is provided on the silicon substrate 22 . In addition, in the pixel 11 , a transfer transistor 31 is provided for transferring a charge from the photodiode 33 .
  • the pixel transistor 32 transistors other than the transfer transistor 31 are included among the predetermined number of transistors necessary for driving the pixel 11 .
  • the pixel transistor 32 in a 4 -transistor-type configuration, is an amplification transistor, selection transistor and a reset transistor; in a 3 -transistor-type configuration, the pixel transistor 32 is an amplification transistor and a reset transistor.
  • any one of this predetermined number of transistors is represented and depicted as the pixel transistor 32 .
  • the gate electrode 41 configuring the transfer transistor 31 is formed by being embedded so as to penetrate the P-type epitaxial layer 21 so as to reach from the surface (surface facing upwards in FIG. 1 ) of the P-type epitaxial layer 21 to the photodiode 33 .
  • An N-type region 42 formed on front face side of the P-type epitaxial layer 21 so as to neighbor the gate electrode 41 functions as an FD (floating diffusion) portion. That is, the N-type region 42 is connected to the gate electrode of the amplification transistor via a wiring not shown in the drawings, and a charge transferred from the photodiode 33 via the transfer transistor 31 is accumulated and the accumulated charge applied to the gate electrode of the amplification transistor.
  • the pixel transistor 32 is configured from the N-type regions 44 and 45 formed on the front face side of the P-type epitaxial layer 21 so as to neighbor the gate electrode 43 laminated on the surface of the P-type epitaxial layer 21 and both sides of the gate electrode 43 .
  • the N-type regions 44 and 45 one functions as a source of the pixel transistor 32 and the other functions as a drain of the pixel transistor 32 .
  • the element separation in the P-type epitaxial layer 21 is performed by impurity injection.
  • the photodiode 33 is formed on the silicon substrate 22 , and performs photoelectric conversion by receiving light irradiated toward the rear face (surface facing upper side of FIG. 1 ) of the solid-state imaging device 1 , and generates and accumulates a charge according to the amount of light.
  • the on-chip lens 25 collects light irradiated to the photodiode 33 for each pixel 11 , and the color filter layer 24 is transparent to light in a wavelength region of a specific color (for example, three colors of red, blue and green) for each pixel 11 .
  • the anti-reflection film 23 prevents light passing through the on-chip lens 25 and the color filter layer 24 from reflecting.
  • the solid-state imaging device 1 is configured such that the pixel transistor 32 is formed on the P-type epitaxial layer 21 which is a pixel transistor region 2 , and a photodiode 33 is formed on the silicon substrate 22 which is the photodiode region 3 .
  • the solid-state imaging device 1 for example, it is possible to avoid a structure in which the regions forming the pixel transistor 32 are eroded in a portion of the photodiode 33 (refer to FIGS. 3A and 3B described later), and it is possible to avoid decreasing the region of the photodiode 33 . That is, by setting the structure of the pixel 11 , it is possible to enlarge the area of the photodiode 33 greater than in the related art, and possible to avoid lowering of the amount of saturation charge and the sensitivity characteristics of the photodiode 33 , and to further improve these characteristics.
  • the solid-state imaging device 1 it is possible to avoid the generation of differences in the characteristics between the pixels by arranging the transistors asymmetrically, along with being possible to enlarge the area of the transfer transistor 31 and pixel transistor 32 .
  • FIGS. 2A and 2B the structure of a pixel 11 to which a 4 -pixel shared structure is employed is shown; a planar layout in the photodiode region 3 is shown in FIG. 2A , and a planar layout in the pixel transistor region 2 is shown in FIG. 2B .
  • FIGS. 3A and 3B the structure of a pixel 11 ′ of the related art is shown; a cross-sectional layout of a pixel 11 ′ is shown in FIG. 3A , and a planar layout of a pixel 11 ′ is shown in FIG. 3B .
  • a photodiode 33 ′ and a pixel transistor 32 ′ are formed in the same region, that is, both are formed on the silicon substrate 22 . Therefore, in the pixel 11 ′, there is a structure in which the region forming the pixel transistor 32 is eroded at a portion of the photodiode 33 ′.
  • the pixel 11 it is possible to enlarge the area of the photodiode 33 greater than the configuration of the pixel 11 ′ by forming the photodiode 33 and the pixel transistor 32 in different regions. In so doing, it is possible to improve the amount of saturation charge and the sensitivity characteristics of the photodiode 33 .
  • the pixel transistor 32 A′, pixel transistor 32 B′ and pixel transistor 32 C′ become asymmetrical through differing in their respective uses, and also through differing in the areas thereof.
  • the characteristics of pixel 11 ′- 3 and pixel 11 ′- 4 are substantially the same.
  • the areas of the pixel transistor 32 C′ and pixel transistor 32 B′ which separate and come into contact are different, influence of reflection due to the gate or potential modulation due to the gate voltage is different, and characteristic differences occur.
  • the pixel 11 ′- 1 is not influenced due to not neighboring the pixel transistors, and the characteristics of the pixel 11 ′- 2 , pixel 11 ′- 3 and pixel 11 ′- 4 become different.
  • the pixels 11 - 1 to 11 - 4 may be arranged completely symmetrically, it is possible to avoid the occurrence of a difference in the characteristics there between. In so doing, it is possible to improve the characteristics of the pixels 11 - 1 to 11 - 4 .
  • the pixel 11 it is possible to secure an area enabling arranging the pixel transistor 32 A, pixel transistor 32 B and pixel transistor 32 C to be wide, and it is possible to sufficiently secure the ratio between the channel width (W) and the channel length (L). In so doing, it is possible to suppress the occurrence of random noise caused by the pixel transistor 32 , and possible to improve the characteristics of the pixels 11 - 1 to 11 - 4 .
  • FIG. 4 the upper side of FIG. 4 is set as the front face side of the solid-state imaging device 1 and the lower side of FIG. 4 is set as the rear face side of the solid-state imaging device 1 .
  • a part of the photodiode 33 which is not shown in the drawings is an N-type region
  • a rear face pinning layer 51 is formed on the rear face side with respect to the photodiode 33
  • a front face pinning layer 52 is formed on the front face side with respect to the photodiode 33 . That is, the rear face pinning layer 51 is formed between the silicon substrate 22 and the anti-reflection film 23 so as to contact the rear surface of the photodiode 33 which is an N-type region.
  • the front face pinning layer 52 is formed on the silicon substrate 22 so as to contact the front face of the photodiode 33 which is an N-type region.
  • a P-well 53 is formed on the silicon substrate 22 so as to surround the side face of the photodiode 33 .
  • the gate electrode 41 of the transfer transistor 31 is embedded in the P-type epitaxial layer 21 and the silicon substrate 22 , and a channel region 54 suppressing the flow of charge from the photodiode 33 is formed so as to surround the embedded part of the gate electrode 41 .
  • a channel region 55 suppressing the flow of charge between the N-type regions 44 and 45 is formed so as to cover the bottom face of the gate electrode 43 of the pixel transistor 32 .
  • a light blocking metal 56 for preventing the incidence of the light from the oblique direction is formed on the anti-reflection film 23 .
  • a pixel transistor 32 is formed on the P-type epitaxial layer 21 and the photodiode 33 and the pixel transistor 32 are formed in different regions in the depth direction, along with the photodiode 33 being formed on the silicon substrate 22 . Then, in the pixel 11 , a transfer transistor 31 formed such that the gate electrode 41 is embedded is used in the transfer of charge from the photodiode 33 .
  • the pixel 11 it is possible to improve the amount of saturation charge and the sensitivity characteristics of the photodiode 33 by forming the photodiode 33 and the pixel transistor 32 in different regions, as described above.
  • FIG. 5 a cross-sectional view showing a configuration example of a second embodiment of a pixel 11 is shown in FIG. 5 .
  • configurations shared with the pixel 11 in FIG. 4 are given the same reference numbers, and detailed description thereof will not be made.
  • the pixel 11 A has a configuration shared with the pixel 11 in FIG. 4 on the point of a photodiode 33 being formed on a silicon substrate 22 and the pixel transistor 32 being formed on the P-type epitaxial layer 21 .
  • the pixel 11 A has a configuration differing from the pixel 11 in FIG. 4 on the point of a transfer transistor 31 A being formed by forming an excavated portion 61 in the P-type epitaxial layer 21 .
  • the transfer transistor 31 A formed in the excavated portion 61 is used in transferring the charge of the photodiode 33 , in contrast to the embedded-type transfer transistor 31 being used in the pixel 11 in FIG. 4 .
  • the transfer transistor 31 A is configured having a gate electrode 41 A formed so as to be laminated on the bottom face of the excavated portion 61 , that is, the surface of the silicon substrate 22 , formed by excavating the P-type epitaxial layer 21 until the silicon substrate 22 is exposed.
  • a channel region 54 A is formed on the silicon substrate 22 so as to cover the bottom face of the gate electrode 41 A.
  • the N-type region 42 A functioning as an FD portion is formed at a position on the surface of the silicon substrate 22 which is the opposite side with respect to the photodiode 33 so as to neighbor the gate electrode 41 A.
  • the pixel 11 A it is possible to improve the transfer characteristics of the charge by shortening the transfer path from the photodiode 33 to the N-type region 42 A (FD portion).
  • FIG. 6 a cross-sectional view showing a configuration example of a third embodiment of the pixel 11 is shown in FIG. 6 .
  • the pixel 11 B has a configuration shared with the pixel 11 in FIG. 4 on the point of a photodiode 33 B being formed on a silicon substrate 22 and the pixel transistor 32 being formed on the P-type epitaxial layer 21 .
  • the pixel 11 B has a configuration differing from the pixel 11 in FIG. 4 on the point of a transfer transistor 31 B being formed on the surface of the P-type epitaxial layer 21 along with the N-type diffusion layer 71 being formed on the P-type epitaxial layer 21 so as to be connected to the photodiode 33 B.
  • the charge of the photodiode 33 is transferred using an embedded-type transfer transistor 31 .
  • the charge is accumulated in the N-type diffusion layer 71 and the photodiode 33 B, and the charge of the photodiode 33 B is transferred via the N-type diffusion layer 71 .
  • a photodiode 33 B and a surface pinning layer 52 B are formed such that a portion of the photodiode 33 B is exposed in the surface of the silicon substrate 22 .
  • the N-type diffusion layer 71 is formed so as to extend in the depth direction of the P-type epitaxial layer 21 and connect to a portion of the photodiode 33 B exposed in the surface of the silicon substrate 22 .
  • a surface pinning layer 72 is formed on the P-type epitaxial layer 21 that is the front face side of the N-type diffusion layer 71 so as to contact the N-type diffusion layer 71 .
  • the transfer transistor 31 B is configured having a gate electrode 41 B formed so as to be laminated on the surface of the P-type epitaxial layer 21 , and a channel region 54 B is formed on the P-type epitaxial layer 21 so as to cover the bottom face of the gate electrode 41 B.
  • the N-type region 42 B which functions as an FD portion is formed at a position on the surface of the P-type epitaxial layer 21 which is the opposite side with respect to the N-type diffusion layer 71 so as to neighbor the gate electrode 41 B.
  • the pixel 11 B a PN junction due to the N-type diffusion layer 71 and the surface pinning layer 72 is formed, and the N-type diffusion layer 71 is able to accumulate a charge by performing photoelectric conversion, similarly to the photodiode 33 B.
  • the pixel 11 B is more able to increase the amount of saturation charge than the pixel 11 in FIG. 4 .
  • the N-type diffusion layer 71 is able to perform photoelectric conversion of light in the wavelength region of the color red because of being formed in a deep region from the direction in which light is incident on the pixel 11 B, and the pixel 11 B is able to achieve increases in sensitivity to red light.
  • the pixel 11 B is able to shorten the transfer path from the N-type diffusion layer 71 to the N-type region 42 B (FD portion) via the transfer transistor 31 B and able to improve the transfer characteristics of the charge.
  • FIG. 7 a cross-sectional view showing a configuration example of a fourth embodiment of a pixel 11 is shown in FIG. 7 .
  • the pixel 11 C has a configuration shared with the pixel 11 in FIG. 4 on the point of a photodiode 33 B being formed on a silicon substrate 22 and the pixel transistor 32 being formed on the P-type epitaxial layer 21 .
  • the pixel 11 C has a configuration differing from the pixel 11 in FIG. 4 on the point of an element separation portion 81 being formed on the surface of the P-type epitaxial layer 21 .
  • an element separation portion 81 configured by an oxide film is formed in order to separate the pixel transistor 32 and the N-type region 42 B in the P-type epitaxial layer 21 .
  • an oxide film other than an impurity diffusion layer is used in element separation in the P-type epitaxial layer 21 .
  • the pixel 11 C configured in this way, similarly to the pixel 11 in FIG. 4 , it is possible to improve the amount of saturation charge and the sensitivity characteristics of the photodiode 33 by forming the photodiode 33 and the pixel transistor 32 in different regions.
  • FIG. 8 a cross-sectional view showing a configuration example of a fifth embodiment of a pixel 11 is shown in FIG. 8 .
  • the pixel 11 D has a configuration shared with the pixel 11 in FIG. 4 on the point of a photodiode 33 being formed on a silicon substrate 22 and the pixel transistor 32 being formed on the P-type epitaxial layer 21 .
  • the pixel 11 D has a configuration differing from the pixel 11 of FIG. 4 on the point of an embedded oxide film 91 being formed so as to surround the side face of the photodiode 33 , and an oxide film 92 being formed on the P-type epitaxial layer 21 so as to connect to the embedded oxide film 91 .
  • an oxide film 93 for performing element separation is formed between the pixel transistor 32 and the transfer transistor 31 .
  • the pixel 11 D configured in this way, similarly to the pixel 11 in FIG. 4 , it is possible to improve the amount of saturation charge and the sensitivity characteristics of the photodiode 33 by forming the photodiode 33 and the pixel transistor 32 in different regions.
  • the pixel 11 D it is possible to suppress mixed colors and blooming in the interior of the silicon substrate 22 by embedding the embedded oxide film 91 from the rear face side. Further, in the pixel 11 D, it is possible to completely separate the pixel 11 D from neighboring pixels by setting a structure in which the embedded oxide film 91 formed on the silicon substrate 22 and the oxide film 92 formed on the P-type epitaxial layer 21 are connected to each other.
  • the embedded oxide film 91 is formed so as to connect to the light blocking metal 56 .
  • the embedded oxide film 91 is formed so as to connect to the light blocking metal 56 .
  • the light concentrated by the on-chip lens 25 it is possible for the light concentrated by the on-chip lens 25 to be reliably received by the photodiode 33 , and possible to improve the sensitivity of the photodiode 33 .
  • a metal such as the same material as the light blocking metal 56 , for example, tungsten, may be embedded in the silicon substrate 22 so as to surround the side face of the photodiode 33 , instead of the embedded oxide film 91 .
  • FIG. 9 a cross-sectional view showing a configuration example of a sixth embodiment of a pixel 11 is shown in FIG. 9 .
  • the pixel 11 E has a configuration shared with the pixel 11 in FIG. 4 on the point of a photodiode 33 being formed on a silicon substrate 22 and the pixel transistor 32 being formed on the P-type epitaxial layer 21 .
  • the pixel 11 E has a configuration differing from the pixel 11 in FIG. 4 on the point of a concentrated P-type epitaxial layer 101 being formed so as to be arranged between P-type epitaxial layer 21 and the silicon substrate 22 .
  • a concentrated P-type epitaxial layer 101 is formed by performing doping (In situ doped epitaxial deposition) when performing epitaxial growth with respect to the surface of the silicon substrate 22 .
  • heating conditions of approximately 1000 degrees are necessary in order to perform good quality epitaxial growth.
  • epitaxial growth is started after the surface pinning layer 52 is formed by performing impurity injection in the silicon substrate 22 .
  • impurities in the vicinity of the interface diffuse due to heating during epitaxial growth.
  • the capacitance of the PN junction decreases, and the amount of saturation charge decreases.
  • FIG. 10 a cross-sectional view showing a configuration example of a seventh embodiment of a pixel 11 is shown in FIG. 10 .
  • the pixel 11 F has a configuration shared with the pixel 11 in FIG. 4 on the point of a photodiode 33 being formed on a silicon substrate 22 and the pixel transistor 32 being formed on the P-type epitaxial layer 21 .
  • the pixel 11 F has a configuration differing from the pixel 11 in FIG. 4 on the point of, in the P-type epitaxial layer 21 , a well 111 which is an impurity region with a higher P-type impurity concentration than the P-type epitaxial layer 21 being formed between the pixel transistor 32 and the photodiode 33 .
  • the pixel 11 F for example, even in a case in which the impurity concentration of the P-type epitaxial layer 21 is low, it is possible to reliably perform separation of the photodiode 33 and the pixel transistor 32 by forming the well 111 . In so doing, for example, it is possible to shorten the distance between the photodiode 33 and the pixel transistor 32 , that is, make the thickness of the P-type epitaxial layer 21 thinner, and achieve thinning of the solid-state imaging device 1 .
  • the impurity concentration of the P-type epitaxial layer 21 is high and the concentration enables separation of the photodiode 33 and the pixel transistor 32 , formation of the well 111 becomes unnecessary.
  • the thickness of the P-type epitaxial layer 21 is unrestricted if it is in a region in which the characteristics of the photodiode 33 of the silicon substrate 22 and the pixel transistor 32 of the P-type epitaxial layer 21 do not interfere.
  • a photodiode 33 is formed with respect to an n-type silicon substrate 22 (n-Si).
  • n-Si n-type silicon substrate 22
  • an N-type region 33 b (n) is formed inside the silicon substrate 22 by injecting n-type impurities in the silicon substrate 22
  • an N-type region 33 a (n+) with a higher impurity concentration than the N-type region 33 b is formed further to the front face side than the N-type region 33 b .
  • a photodiode 33 is formed by forming a surface pinning layer 52 (p+) on the surface of the silicon substrate 22 by injecting concentrated p-type impurities in the silicon substrate 22 .
  • a P-well 53 (p) which is a separation layer is formed so as to surround the N-type regions 33 a and 33 b , along with the side face of the surface pinning layer 52 , by injecting p-type impurities in the silicon substrate 22 .
  • a P-type epitaxial layer 21 (p-epi) is formed by performing epitaxial growth in which a thin film of a single crystal in which the crystal orientation is aligned on the silicon substrate 22 is grown.
  • an excavated portion 121 is formed by excavating from the surface of the P-type epitaxial layer 21 to the silicon substrate 22 .
  • the excavated portion 121 is excavated such that the channel region 54 formed on the side face of the gate electrode 41 reaches the P-well 53 at a position so as to contact the photodiode 33 .
  • the channel region 54 and the channel region 55 is formed by injecting n-type impurities in the P-type epitaxial layer 21 . Then, a gate oxide film 123 is formed on the surface of the P-type epitaxial layer 21 and on the inside surface of the excavated portion 121 .
  • a gate electrode 41 configuring the transfer transistor 31 and a gate electrode 43 configuring the pixel transistor 32 are formed.
  • an N-type region 42 (n++) functioning as an FD portion is formed by injecting concentrated n-type impurities in a location neighboring the gate electrode 41 of the P-type epitaxial layer 21 .
  • a pixel transistor 32 is formed by forming N-type regions 44 and 45 (n++) by concentrated injecting n-type impurities in locations on both sides neighboring the gate electrode 43 of the P-type epitaxial layer 21 .
  • a wiring layer 131 is formed on the P-type epitaxial layer 21 .
  • wirings 132 - 1 to 132 - 4 arranged in multiple layers are formed, as shown in the drawing.
  • contact portions 133 - 1 to 133 - 4 are formed so as to respectively connect to the gate electrode 43 and gate electrode 41 , along with the wirings 132 - 1 to 132 - 4 .
  • the front face of the silicon substrate 22 is faced upward, and the processing is performed with respect to the front face side of the silicon substrate 22 .
  • the silicon substrate 22 is reversed, the rear face of the silicon substrate 22 is faced upward, and thereafter, processing is begun with respect to the rear face side of the silicon substrate 22 .
  • etching of the silicon substrate 22 is performed from the rear face side to the photodiode 33 .
  • a rear face pinning layer 51 is formed with respect to the silicon substrate 22 .
  • an anti-reflection film 23 is formed on the rear face pinning layer 51 , and a light blocking metal 56 is formed so as to be embedded in the anti-reflection film 23 between the pixel 11 and neighboring pixels.
  • a color filter layer 24 is laminated on the anti-reflection film 23 , and an on-chip lens 25 is laminated on the color filter layer 24 .
  • the pixel 11 is formed through the steps as described above.
  • the pixel 11 it is possible to improve the amount of saturation charge and the sensitivity characteristics of the photodiode 33 by forming the photodiode 33 and the pixel transistor 32 in different regions through such a method of manufacturing.
  • the P-type epitaxial layer 21 is formed so as to be laminated with respect to the silicon substrate 22 after the photodiode 33 is formed on the silicon substrate 22 , it is possible to form the photodiode 33 such that the gradient of the potential becomes sharp. In so doing, it is possible to further improve the amount of saturation charge and the sensitivity characteristics of the photodiode 33 .
  • FIG. 23 a cross-sectional view showing a configuration example of an eighth embodiment of a pixel 11 is shown in FIG. 23 .
  • the pixel 11 G has a configuration shared with the pixel 11 in FIG. 4 on the point of a photodiode 33 being formed on a silicon substrate 22 and the pixel transistor 32 being formed on the P-type epitaxial layer 21 .
  • the pixel 11 G has a configuration differing from the pixel 11 in FIG. 4 on the point of an N-type region 201 functioning as an FD portion being formed on the silicon substrate 22 , and charge being transferred from the photodiode 33 to the N-type region 201 with only the bottom face of the embedded-type transfer transistor 31 .
  • the bottom face of the gate electrode 41 configuring the transfer transistor 31 is formed so as to contact the silicon substrate 22 via an oxide film 123 , and a channel region 203 is formed on the silicon substrate 22 which is a region corresponding to the bottom face of the gate electrode 41 .
  • the N-type region 201 is formed on the silicon substrate 22 which is a position separated from the photodiode 33 via the channel region 203 .
  • a P-type region 202 is formed between the N-type region 201 and the N-type region 33 b in order to separate the N-type region 201 and the N-type region 33 b.
  • a contact portion 211 is formed by a conductor embedded in the P-type epitaxial layer 21 so as to connect to the N-type region 201 by penetrating the P-type epitaxial layer 21 , and the contact portion 211 is connected to the wiring 132 - 6 of the wiring layer 131 .
  • an insulating film 212 - 1 formed from an oxide film is formed, and the capacitance is reduced.
  • an insulating film 212 - 2 is formed on the side face of the contact portion 133 - 4 connecting the gate electrode 41 and the wiring 132 - 4
  • an insulating film 212 - 3 is formed on the side face of the contact portion 133 - 3 connecting the gate electrode 43 and the wiring 132 - 3 .
  • a sidewall 213 - 1 is formed on the side face of the gate electrode 43
  • a sidewall 213 - 2 is formed on the side face of the gate electrode 41 .
  • separation portions 204 and 205 for separating the pixel transistor 32 are formed on the P-type epitaxial layer 21 .
  • the pixel 11 G employing such a structure similarly to the rear face illumination-type CMOS image sensor of the related art, is able to transfer charge from the photodiode 33 to the N-type region 201 (FD portion). In so doing, it is possible to make the potential of the photodiode 33 sufficiently deep, and to ensure the amount of saturation charge. In other words, as in the pixel 11 G, even employing a configuration forming the photodiode 33 and the pixel transistor 32 in different regions in the depth direction, it is possible to set the potential of the photodiode 33 to the same depth as a rear face illumination-type CMOS image sensor of the related art.
  • the impurity concentration in the P-type epitaxial layer 21 is set to be sufficiently higher than in the silicon substrate 22 , and possible for a channel to be formed only on the bottom face portion by setting a threshold voltage Vth of the sidewall portion of the gate electrode 41 configuring the transfer transistor 31 to be high with respect to the bottom face.
  • an SOI substrate 221 on which a BOX layer (silicon dioxide insulating film) 222 and an SOI layer (single crystal silicon film) 223 are laminated on a silicon substrate 22 is used.
  • a surface pinning layer 52 (p+) is formed by injecting p-type impurities with respect to the silicon substrate 22
  • an N-type region 33 a (n+) is formed by injecting n-type impurities.
  • a PN junction formed from the surface pinning layer 52 and the N-type region 33 a is formed.
  • a photodiode 33 is formed by forming the N-type region 33 b (n) by injecting n-type impurities with respect to the silicon substrate 22 .
  • concentrated n-type impurities are injected and an N-type region 201 (n) functioning as an FD portion is formed.
  • a P-type region 202 (p) is formed between the N-type region 33 b and the N-type region 201 so as to connect to a P-well 53 , along with forming the P-well 53 (p) so as to surround the side face of the photodiode 33 , by injecting p-type impurities.
  • a P-type epitaxial layer 21 which becomes a pixel transistor region 2 is formed by performing doping during epitaxial growth (In situ doped epitaxial deposition) with respect to the surface of the silicon substrate 22 .
  • a mark is formed for use as a target when the front and rear are matched in the lithography step in processing of the rear face side.
  • a trench 232 is formed in a region different from the region in which the pixel 11 G is formed, for example, a location separating chips, or the like.
  • the trench 232 is formed by forming a mask 231 at locations other than those forming the trench 232 and performing etching.
  • an insulator 233 such as silicon nitride (SiN) is embedded in the trench 232 and flattening is performed along with removing the mask 231 , thereby forming a mark.
  • impurity injection for forming the well and channel is performed with respect to the P-type epitaxial layer 21 . Moreover, since doping is performed during epitaxial growth when forming the P-type epitaxial layer 21 , performing impurity injection for forming the well may not be necessary. In addition, an oxide film 123 is formed on the P-type epitaxial layer 21 .
  • a trench 235 for forming an embedded-type gate electrode 41 is formed.
  • the trench 235 is formed by, for example, creating a hard mask 234 , such as silicon nitride (SiN) on locations other than those forming the trench 235 , and performing etching.
  • a hard mask 234 such as silicon nitride (SiN)
  • SiN silicon nitride
  • a channel region 203 is formed by injecting n-type impurities in the bottom face of the trench 235 .
  • a threshold voltage Vth applied to the gate electrode 41 when transferring charge by the transfer transistor 31 is set to be adjustable.
  • self-aligning of the gate electrode 41 and the channel region 203 of the transfer transistor 31 becomes possible.
  • FIG. 32 a planar layout of the pixel 11 G when the twenty-seventh step is performed is shown in FIG. 32 .
  • a P-well 53 is formed at the periphery of the photodiode 33 and the N-type region 201 , and a trench 235 is formed so as to separate the photodiode 33 and the N-type region 201 .
  • the trench 235 is formed such that both ends of the trench 235 extend to the P-well 53 when viewed planarly.
  • a gate oxide film 123 is formed on the surface of the P-type epitaxial layer 21 and the inside surface of the trench 235 .
  • the gate electrode 43 and gate electrode 41 are formed, and the pixel transistor 32 and the transfer transistor 31 are formed by performing gate working.
  • the use of a material made to be conductive, such as of amorphous silicon doped in-situ with phosphorous is suitable even without performing impurity injection. This is because, in a case in which impurity injection is performed, it is difficult to inject impurities to the deep parts of the trench 235 .
  • FIG. 34 a planar layout of the pixel 11 G when the twenty-eighth step is performed is shown in FIG. 34 .
  • a P-well 53 is formed at the periphery of the photodiode 33 and the N-type region 201 , and a trench 235 is formed so as to separate the photodiode 33 and the N-type region 201 .
  • the trench 235 is formed such that both ends of the trench 235 extend to the P-well 53 when viewed planarly.
  • the gate electrode 43 here, the gate electrode of the amplification transistor is shown in the drawing as the gate electrode 43
  • the photodiode 33 are arranged so as to overlap when viewed planarly.
  • separation portions 204 and 205 for separating the pixel transistors 32 are formed by injecting p-type impurities.
  • a sidewall 213 - 1 is formed on the side face of the gate electrode 43
  • a sidewall 213 - 2 is formed on the side face of the gate electrode 41 .
  • activation annealing for activating the impurities injected in the silicon substrate 22 and the P-type epitaxial layer 21 is performed.
  • an interlayer film 131 - 1 configuring the wiring layer 131 is formed.
  • an opening portion 236 for forming a contact portion 133 - 3 As shown in FIG. 38 , in the thirty-second step, an opening portion 236 for forming a contact portion 133 - 3 , an opening portion 237 for forming a contact portion 133 - 4 and an opening portion 238 for forming a contact portion 211 are formed.
  • the opening portion 238 is formed by the interlayer film 131 - 1 and the P-type epitaxial layer 21 being worked at the same time until the N-type region 201 functioning as an FD portion is exposed.
  • an insulating film 239 is formed on the surface of the interlayer film 131 - 1 and the inside surface of the opening portions 236 to 238 .
  • the insulating film 239 formed on the bottom face of the opening portions 236 to 238 is removed by etchback.
  • an insulating film 212 - 3 is formed on the side face of the opening portion 236
  • an insulating film 212 - 2 is formed on the side face of the opening portion 237
  • an insulating film 212 - 1 is formed on the side face of the opening portion 238 .
  • the insulating film 212 - 1 it is possible to prevent the contact portion 211 from shorting with the P-type epitaxial layer 21 .
  • a metal such as tungsten (W), titanium nitride (TiN) or titanium (Ti) is embedded in the opening portions 236 to 238 .
  • the contact portion 133 - 3 , the contact portion 133 - 4 and the contact portion 211 are formed by polishing using Chemical Mechanical Polishing (CMP).
  • CMP Chemical Mechanical Polishing
  • a wiring 132 - 3 , a wiring 132 - 4 and a wiring 132 - 6 are formed so as to connect to the contact portion 133 - 3 , the contact portion 133 - 4 and the contact portion 211 .
  • a wiring layer 131 formed from a multi-layer wiring layer is formed by laminating an interlayer film, forming a wiring 132 - 1 , a wiring 132 - 2 and a wiring 132 - 5 , and further laminating an interlayer film.
  • the thirty-seventh step for example, after a support substrate 242 is bonded to the wiring layer 131 via an insulating film 241 for bonding formed from silicon dioxide (SiO2) and reversed, stripping to the BOX layer 222 ( FIG. 23 ) is performed with respect to the rear face side.
  • SiO2 silicon dioxide
  • an on-chip lens 25 is formed on the color filter layer 24 after an anti-reflection film 23 is formed on the silicon substrate 22 , a light blocking metal 56 is formed, and the color filter layer 24 is laminated.
  • FIG. 45 a cross-sectional view showing a configuration example of the pixel 11 H which is a modification example (ninth embodiment) of the pixel 11 G in FIG. 23 is shown in FIG. 45 .
  • configurations shared with the pixel 11 G in FIG. 23 are given the same reference numbers, and detailed description thereof will not be made.
  • the pixel 11 H has a configuration differing from the pixel 11 G in FIG. 23 on the point of the N-type region 301 formed on the P-type epitaxial layer 21 and the contact portion 302 formed on the wiring layer 131 being used in order to raise a charge from the N-type region 201 functioning as an FD portion. That is, the N-type region 301 is formed so as to extend in the depth direction of the P-type epitaxial layer 21 so as to connect to the N-type region 201 by penetrating the P-type epitaxial layer 21 , and the contact portion 302 is formed so as to connect the N-type region 301 and the wiring 132 - 6 .
  • the pixel 11 H configured in this way is able to improve the amount of saturation charge and the sensitivity characteristics of the photodiode 33 , similarly to the pixel 11 G in FIG. 23 .
  • processing is performed from the twenty-first step ( FIG. 25 ) to the thirtieth step ( FIG. 36 ) described above in the same manner as the pixel 11 G, and the processing below is performed before the activation annealing in the thirtieth step is performed.
  • the N-type region 301 is formed up to the surface of the P-type epitaxial layer 21 by injecting n-type impurities to the P-type epitaxial layer 21 in multiple stages, so as to connect to the N-type region 201 so as to extend in the depth direction of the P-type epitaxial layer 21 .
  • an interlayer film 131 - 1 configuring the wiring layer 131 is formed.
  • an opening portion is formed in the same manner as the thirty-second step described above, and the contact portion 133 - 3 , the contact portion 133 - 4 and the contact portion 302 are formed in the same manner as the thirty-fifth step described above.
  • the opening portion for forming the contact portion 302 is formed such that the P-type epitaxial layer 21 is not excavated, it is possible to form the side face of the contact portion 302 so as not to contact the P-type epitaxial layer 21 , and the step forming the insulating film on the opening portion becomes unnecessary.
  • a wiring layer 131 formed of a multi-layer wiring layer is formed in the same manner to the thirty-sixth step. Subsequently, a step is performed in which an anti-reflection film 23 , a light blocking metal 56 , a color filter layer 24 and an on-chip lens 25 are formed.
  • FIG. 50 a cross-sectional view showing a configuration example of a tenth embodiment of a pixel 11 is shown in FIG. 50 .
  • the pixel 11 J has a configuration shared with the pixel 11 in FIG. 4 on the point of a photodiode 33 being formed on a silicon substrate 22 and the pixel transistor 32 being formed on the P-type epitaxial layer 21 .
  • the pixel 11 J has a configuration differing from the pixel 11 in FIG. 4 on the point of a photodiode 302 and a surface pinning layer 301 being formed on the P-type epitaxial layer 21 .
  • the photodiode 302 performing photoelectric conversion is formed on the P-type epitaxial layer 21 after the photodiode 33 is formed on the silicon substrate 22 and the P-type epitaxial layer 21 is formed on the silicon substrate 22 .
  • the photodiode 302 is formed so as to neighbor the gate electrode 41 of the transfer transistor 31 via the channel region 54 , and the charge generated by the photodiode 302 is transferred via the transfer transistor 31 , similarly to the charge of the photodiode 33 .
  • the pixel 11 J by providing a photodiode 302 on the P-type epitaxial layer 21 in addition to the photodiode 33 of the silicon substrate 22 , it is possible to perform photoelectric conversion by the photodiode 33 and the photodiode 302 , and accumulate a charge. In so doing, it is possible to increase the amount of saturation charge for the pixel 11 J as a whole, and to improve the sensitivity characteristics.
  • FIG. 51 a cross-sectional view showing a configuration example of the pixel 11 K which is a configuration example (eleventh embodiment) of the pixel 11 J in FIG. 50 is shown in FIG. 51 .
  • a plurality of photodiodes 302 is formed so as to be laminated in the depth direction (vertical direction in the diagram) of the P-type epitaxial layer 21 in the pixel 11 K. That is, as shown in FIG. 51 , in the pixel 11 K, photodiodes 302 - 1 to 302 -N and surface pinning layers 301 - 1 to 301 -N laminated on N layers are provided on the P-type epitaxial layer 21 .
  • the pixel 11 K is able to increase the photodiode capacitance (high voltage interface) over that in the pixel 11 J, and is able to achieve an increase in the amount of saturation charge, by changing the photodiodes 302 - 1 to 302 -N to multiple stages.
  • FIG. 52 a cross-sectional view showing a configuration example of the pixel 11 K which is a modification example (twelfth embodiment) of the pixel 11 L in FIG. 51 is shown in FIG. 52 .
  • a portion of the plural layers of photodiodes 302 is formed on the P-type epitaxial layer 21 so as to have different areas in the pixel 11 L.
  • the area of the photodiode 302 -N′ and surface pinning layer 301 -N′ of the Nth layer arranged in the vicinity of the silicon substrate 22 and the P-type epitaxial layer 21 is formed wider than the area of the other photodiodes 302 and the surface pinning layer 301 .
  • the area of a portion of the photodiodes 302 arranged in the vicinity of the surface of the P-type epitaxial layer 21 among the plurality of layers of photodiode 302 is formed wider than the area of the other photodiodes 302 .
  • the area of the photodiode 302 formed to be wide is set so as to become the maximum area in a region in which the pixel 11 L is formed in a range not infiltrating the region in which the pixel transistor 32 is formed in the P-type epitaxial layer 21 .
  • the area of the photodiode 302 formed to be wide is set so as to become the maximum area in a region in which the pixel 11 L is formed in a range not infiltrating the region in which the pixel transistor 32 is formed in the P-type epitaxial layer 21 .
  • the one layer of photodiode 302 -N′ is formed to be wide; however, the present disclosure is not limited to a single layer. That is, it is possible to form the area of a predetermined number of layers of the photodiode 302 in the vicinity of the surface of the P-type epitaxial layer 21 to be wider than the area of the other photodiodes 302 . In so doing, it is possible to reduce invalid regions in the P-type epitaxial layer 21 , and possible to further achieve an increase in the amount of saturation charge.
  • the solid-state imaging device 1 as described above may be applied to various electronic apparatuses, such as the image capture system of a digital still camera or a digital video camera, a mobile telephone including an image capture function, and other devices including an image capturing function.
  • FIG. 50 is a block diagram showing a configuration example of an imaging device mounted in an electronic apparatus.
  • the image capture device 501 is configured including an optical system 502 , an image capture element 503 , a signal processing circuit 504 , a monitor 505 and a memory 506 , and is able to capture still images and moving images.
  • the optical system 502 is configured to have one or a plurality of lenses, and image light (incident light) from a subject is guided to the image capture element 503 , thereby an image is formed on a light receiving face (sensor portion) of the image capture element 503 .
  • the image capture element 503 is applied to the solid-state imaging device 1 having the pixel 11 of each of the above-described configuration examples.
  • electrons are accumulated for a predetermined period according to the image formed on the light receiving face via the optical system 502 . Then, a signal according to the electrons accumulated in the image capture element 503 is provided to the signal processing circuit 504 .
  • the signal processing circuit 504 executes various signal processes with respect to the pixel signal output from the image capture element 503 .
  • the image (image data) obtained by the signal processing circuit 504 executing signal processing is displayed by being supplied to the monitor 505 or is stored (recorded) by being supplied to the memory 506 .
  • an image capture device 501 configured in this way, it is possible to improve the amount of saturation charge and the sensitivity characteristics and possible to obtain an image with better image quality by applying the configuration of a solid-state imaging device 1 having the pixel 11 of the various configuration examples described above.
  • the present technology may also adopt the following configurations.

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  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Solid State Image Pick-Up Elements (AREA)
  • Transforming Light Signals Into Electric Signals (AREA)
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