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US20040090828A1 - Semiconductor integrated circuit - Google Patents

Semiconductor integrated circuit Download PDF

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Publication number
US20040090828A1
US20040090828A1 US10/333,010 US33301003A US2004090828A1 US 20040090828 A1 US20040090828 A1 US 20040090828A1 US 33301003 A US33301003 A US 33301003A US 2004090828 A1 US2004090828 A1 US 2004090828A1
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US
United States
Prior art keywords
wiring
voltage
semiconductor integrated
integrated circuit
circuit according
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Abandoned
Application number
US10/333,010
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English (en)
Inventor
Junichi Okamura
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
THine Electronics Inc
Original Assignee
THine Electronics Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by THine Electronics Inc filed Critical THine Electronics Inc
Assigned to THINE ELECTRONICS, INC. reassignment THINE ELECTRONICS, INC. ASSIGNMENT OF ASSIGNORS INTEREST (SEE DOCUMENT FOR DETAILS). Assignors: OKAMURA, JUNICHI
Publication of US20040090828A1 publication Critical patent/US20040090828A1/en
Assigned to THINE ELECTRONICS, INC. reassignment THINE ELECTRONICS, INC. CORRECTED COVER SHEET TO CORRECT ASSIGNEE'S ADDRESS, PREVIOUSLY RECORDED AT REEL/FRAME 014330/0362 (ASSIGNMENT OF ASSIGNOR'S INTEREST) Assignors: OKAMURA, JUNICHI
Abandoned legal-status Critical Current

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Classifications

    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K3/00—Circuits for generating electric pulses; Monostable, bistable or multistable circuits
    • H03K3/02—Generators characterised by the type of circuit or by the means used for producing pulses
    • H03K3/023—Generators characterised by the type of circuit or by the means used for producing pulses by the use of differential amplifiers or comparators, with internal or external positive feedback
    • H03K3/0231—Astable circuits
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F1/00—Details not covered by groups G06F3/00 - G06F13/00 and G06F21/00
    • G06F1/04—Generating or distributing clock signals or signals derived directly therefrom
    • G06F1/10—Distribution of clock signals, e.g. skew
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K3/00—Circuits for generating electric pulses; Monostable, bistable or multistable circuits
    • H03K3/02—Generators characterised by the type of circuit or by the means used for producing pulses
    • H03K3/027—Generators characterised by the type of circuit or by the means used for producing pulses by the use of logic circuits, with internal or external positive feedback
    • H03K3/03—Astable circuits
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K3/00—Circuits for generating electric pulses; Monostable, bistable or multistable circuits
    • H03K3/02—Generators characterised by the type of circuit or by the means used for producing pulses
    • H03K3/027—Generators characterised by the type of circuit or by the means used for producing pulses by the use of logic circuits, with internal or external positive feedback
    • H03K3/03—Astable circuits
    • H03K3/0315—Ring oscillators
    • H03K3/0322—Ring oscillators with differential cells

Definitions

  • the present invention relates generally to a semiconductor integrated circuit and more particularly to a semiconductor integrated circuit including a differential ring multiphase oscillator.
  • a parallel-serial converter is required on a transmit side which converter converts parallel data into serial data by using sub-clock signals having multiple phases (hereinafter, such clock signals are referred to as multiphase clock signals).
  • the multiphase clock signals are synchronous with a base clock signal and have the same phase difference.
  • a multiphase clock generator is required which generates the multiphase clock signals and supplies them to the parallel-serial converter.
  • An example of the multiphase clock generator is a voltage-controlled or current-controlled differential ring oscillator having multiple stages of delayed differential inverted amplifiers connected in a ring form.
  • a ring oscillator By using such a ring oscillator, it is possible to easily draw multiphase clock signals having the same phase difference out of the multi-staged amplifiers.
  • the influences of electrostatic coupling between different wirings must be made uniform.
  • FIG. 1 shows a voltage-controlled differential ring oscillator used in conventional semiconductor integrated circuits.
  • the output amplifiers 102 a - 102 j buffer oscillation signals output from every other delayed differential inverted amplifiers 101 a - 101 j connected in a ring form and supply them as multiphase clock signals R 1 -R 10 to the parallel-serial converter.
  • FIG. 2 shows voltage waveforms of the multiphase clock signals R 1 -R 10 output from the voltage-controlled differential ring oscillator as shown in FIG. 1.
  • an abscissa represents time and an ordinate represents voltage.
  • FIG. 3A shows wirings or interconnects for three clock signals R 1 , R 2 , R 3 formed in a semiconductor integrated circuit and capacitors C p equivalently representing stray capacities between these wirings.
  • FIG. 3B shows how crosstalks due to stray capacities degrade the voltage waveforms of the clock signals.
  • a clock signal R 2 undergoes voltage variations under the influence of crosstalks due to stray capacities each time the adjacent clock signals R 1 and R 3 change their voltage levels.
  • An amount of voltage variation ⁇ V increases with the stray capacity C p .
  • information at the transition point is important, and therefore, crosstalk near the transition point has great effects on precision of the clock signals.
  • the stray capacities C p can be reduced, for example, by increasing the distance between the multiphase clock signal wirings as shown in FIG. 4A.
  • FIG. 4A shows an example in which an interval of the multiphase clock signal wirings is increased by two times to halve the stray capacities. This method, however, increases a wiring area for the multiphase clock signals.
  • FIG. 4B shows the new wiring added between adjacent two clock signal wirings and the new wiring is grounded.
  • the new wiring may be supplied with a stable voltage.
  • Such a technique can shield the adjacent two clock signal wirings electrostatically from one another and prevent possible degradations of clock signal waveforms which would otherwise be caused by level transitions of the adjacent clock signals.
  • This technique requires an additional area for laying the new wirings, increasing the wiring area for the multiphase clock signals.
  • a semiconductor integrated circuit comprises: multiple stages of amplifier circuits, connected in a ring form, for performing oscillating operation; a logic circuit for performing logic operation on the basis of predetermined ones of output signals of the multiple stages of amplifier circuits to output a plurality of clock signals having different phases from each other and duties not equal to 0.5; and a plurality of wirings for transmitting the plurality of clock signals output from the logic circuit.
  • FIG. 1 is a circuit diagram showing a configuration of a voltage-controlled differential ring oscillator used in conventional semiconductor integrated circuits.
  • FIG. 2 is a waveform diagram showing voltage waveforms of multiphase clock signals output from the voltage controlled differential ring oscillator as shown in FIG. 1.
  • FIG. 3A is a schematic diagram showing multiphase clock signal wirings in a conventional semiconductor integrated circuits and equivalents of stray capacities between these wirings
  • FIG. 3B is a waveform diagram showing how the voltage waveform of a clock signal is degraded by crosstalk due to the stray capacity.
  • FIGS. 4A and 4B show wirings in the conventional semiconductor integrated circuit which are modified to prevent degradations of waveforms of the multiphase clock signals.
  • FIG. 5 shows a configuration of a semiconductor integrated circuit according to a first embodiment of the present invention.
  • FIG. 6 is a waveform diagram showing voltage waveforms of multiphase clock signals output from a voltage-controlled differential ring oscillator as shown in FIG. 5.
  • FIG. 7A shows an example arrangement of wirings in the semiconductor integrated circuit according to the first embodiment of the present invention
  • FIG. 7B shows voltage waveforms of clock signals in the example arrangement of wirings as shown in FIG. 7A.
  • FIG. 8A shows an arrangement of multiphase clock signal wirings in the semiconductor integrated circuit according to the first embodiment of the present invention
  • FIG. 8B shows an example arrangement of multiphase clock signal wirings in a conventional semiconductor integrated circuit.
  • FIG. 9 is a waveform diagram showing voltage waveforms of multiphase clock signals output from a voltage-controlled differential ring oscillator in a semiconductor integrated circuit according to a second embodiment of the present invention.
  • FIG. 10A shows an arrangement of multiphase clock signal wirings in the semiconductor integrated circuit according to the second embodiment of the present invention
  • FIG. 10B shows voltage waveforms of the multiphase clock signals in the arrangement as shown in FIG. 10A.
  • FIG. 11 is a waveform diagram showing voltage waveforms of multiphase clock signals output from a voltage-controlled differential ring oscillator in a semiconductor integrated circuit according to a third embodiment of the present invention.
  • FIG. 12A shows an arrangement of multiphase clock signal wirings in the semiconductor integrated circuit according to the third embodiment of the present invention
  • FIG. 12B shows voltage waveforms of the multiphase clock signals in the wiring arrangement as shown in FIG. 12A.
  • FIG. 5 shows a configuration of a semiconductor integrated circuit according to a first embodiment of the present invention.
  • this semiconductor integrated circuit includes a voltage-controlled differential ring oscillator 500 for outputting multiphase clock signals and a parallel-serial converter 600 for converting received parallel data into serial data on the basis of the multiphase clock signals.
  • the parallel-serial converter 600 may be provided on the outside of the semiconductor integrated circuit.
  • the voltage-controlled differential ring oscillator 500 includes N stages of delayed differential inverted amplifiers 101 a , 101 b , . . . for performing oscillating operation and logic circuits 502 a , 502 b , . . . for performing logic operation on the basis of output signals of the delayed differential inverted amplifiers 101 a , 101 b , . . . to output clock signals having M phases.
  • N is a positive even number and M is an even number within a range from 2 to N.
  • Each of the delayed differential inverted amplifiers 101 a - 101 j amplifies a difference between a signal applied to a non-inverted input terminal and a signal applied to an inverted input terminal and supplies the amplified differential signal to a non-inverted output terminal and an inverted output terminal.
  • the delayed differential inverted amplifiers 101 a - 101 j are connected in a ring form so that a non-inverted output terminal of the previous stage is connected to an inverted input terminal of the subsequent stage and an inverted output terminal of the previous stage is connected to a non-inverted input terminal of the subsequent stage.
  • a non-inverted output terminal of a delayed differential inverted amplifier 101 j is connected to a non-inverted input terminal of a delayed differential inverted amplifier 101 a and that an inverted output terminal of the delayed differential inverted amplifier 101 j is connected to an inverted input terminal of the delayed differential inverted amplifier 101 a .
  • a signal phase is inverted after passing through the ring once.
  • the delay time of each of the delayed differential inverted amplifiers 101 a - 101 j is controlled by an applied control voltage or control current, allowing the oscillation frequency of the voltage-controlled differential ring oscillator 500 to be adjusted.
  • the logic circuits include M AND gates 502 a - 502 j .
  • An AND gate 502 a has one input terminal connected to the inverted output terminal of the delayed differential inverted amplifier 101 a and the other input terminal connected to the non-inverted output terminal of the delayed differential inverted amplifier 11 e .
  • One input terminal of an AND gate 502 b is connected to the inverted output terminal of the delayed differential inverted amplifier 101 c and the other input terminal is connected to the non-inverted output terminal of the delayed differential inverted amplifier 101 g .
  • the subsequent AND gates 502 c - 502 j are connected in the similar manner.
  • the AND gates 502 a - 502 j produce multiphase clock signals S 1 -S 10 as shown in FIG. 6.
  • FIG. 7A a set of clock signal wirings (S 1 , S 6 ) is shown in FIG. 7A as an example of wiring arrangement.
  • a wiring for a clock signal S 1 and a wiring for a clock signal S 6 are arranged in parallel on a semiconductor substrate.
  • ground wirings GND are arranged for electrostatic shielding.
  • FIG. 7B shows voltage waveforms of the clock signals S 1 and S 6 in the wiring arrangement as shown in FIG. 7A.
  • the set of clock signal wirings (S 1 , S 6 ) is so arranged that one clock signal changes its level when another clock signal is maintained at a low level (at a ground voltage level).
  • the clock signal wiring at the ground voltage level has a sufficiently small impedance compared with an impedance of a crosstalk source, and therefore, it has a function of electrostatic shield in the same way as a ground wiring GND.
  • a wiring for the clock signal S 1 is shielded by a ground wiring GND and a wiring for the clock signal S 6 . Therefore, as shown in FIG. 7B, if the clock signal S 1 changes its level in this period, its waveform is protected against being deformed at that time.
  • FIG. 8A shows an arrangement of multiphase clock signal wirings according to this embodiment and, for comparison, FIG. 8B shows an example of conventional arrangement of multiphase clock signal wirings.
  • the sets of clock signal wirings S 1 , S 6 ), (S 2 , S 7 ), (S 3 , S 8 ), (S 4 , S 9 ) and (S 5 , S 10 ) each has two clock signal wirings arranged parallel to each other on the semiconductor substrate are arranged with ground wirings GND inserted between respective two sets of clock signal wirings.
  • clock signal wirings R 1 -R 10 and ground wirings GND are alternately arranged on the semiconductor substrate.
  • FIG. 8A and FIG. 8B shows that the wiring area of the semiconductor substrate in this embodiment is about 25% less than that in the conventional technique.
  • FIG. 9 shows voltage waveforms of multiphase clock signals S 1 -S 12 output from the 12-stage voltage-controlled differential ring oscillator.
  • clock signal wirings are grouped into plural sets of three clock signal wirings and, in each set of three clock signal wirings, it is possible that when one clock signal changes its level, both of the other two clock signals are maintained at a low level.
  • clock signals are grouped into plural sets of three clock signals by using plural sets of clock signal wirings (S 1 , 5 , S 9 ), (S 2 , S 6 , S 10 ), (S 3 , S 7 , S 11 ) and (S 4 , S 8 , S 12 ).
  • each set of clock signal wirings when one of the three clock signals changes its level, the other two clock signals can be certainly maintained at a low level.
  • FIG. 10A shows an arrangement of multiphase clock signal wirings in the semiconductor integrated circuit according to this embodiment.
  • the sets of clock signal wirings S 1 , S 5 , S 9 ), (S 2 , S 6 , S 10 ), (S 3 , S 7 , S 11 ) and (S 4 , S 8 , S 12 )
  • three clock signal wirings are arranged parallel to each other on the semiconductor substrate, with ground wirings GND interposed between respective two sets of clock signal wirings.
  • FIG. 10B shows voltage waveforms of clock signals S 1 , S 5 , S 9 in the semiconductor integrated circuit of this embodiment.
  • the clock signal S 5 performs a voltage level transition
  • the clock signals S 1 and S 9 are certainly maintained at a low level. Therefore, the wiring for the clock signal S 5 is virtually shielded by the wirings for the clock signals S 1 and S 9 and no voltage waveform deformation is observed with the clock signal S 5 at that time.
  • the clock signal S 1 or S 9 changes its voltage level, the clock signal S 5 is certainly maintained at a low level, so that wiring for the clock signal S 1 or S 9 is virtually shielded by wiring for the clock signal S 5 and a ground wiring GND.
  • the wiring area of the semiconductor substrate can be reduced by approximately 36% compared with that of the conventional arrangement in which clock signal wirings and ground wirings are alternately arranged.
  • FIG. 11 shows voltage waveforms of multiphase clock signals S 1 -S 16 output from the 16-stage voltage-controlled differential ring oscillator.
  • clock signal wirings are grouped into plural sets of four clock signal wirings and, in each set of four clock signal wirings, it is possible that when one clock signal changes its level, the remaining three clock signals are maintained at a low level.
  • clock signals are grouped into plural sets of four clock signals by using plural sets of four clock signal wirings (S 1 , S 5 , S 9 , S 13 ), (S 2 , S 6 , S 10 , S 14 ), (S 3 , S 7 , S 11 , S 15 ) and (S 4 , S 8 , S 12 , S 16 ).
  • FIG. 12A shows an arrangement of multiphase clock signal wirings in the semiconductor integrated circuit according to this embodiment.
  • each set of clock signal wirings S 1 , S 5 , S 9 , S 13 ), (S 2 , S 6 , S 10 , S 14 ), (S 3 , S 7 , S 11 , S 15 ) and (S 4 , S 8 , S 12 , S 16 )
  • four clock signal wirings are arranged parallel to each other on the semiconductor substrate, with ground wirings GND interposed between respective two sets of clock signal wirings.
  • FIG. 12B shows voltage waveforms of clock signals S 1 , S 5 , S 9 , S 13 in the semiconductor integrated circuit according to this embodiment.
  • the remaining three clock signals are certainly maintained at a low level. Therefore, wiring of the level-changing clock signal is virtually shielded by wirings of the adjacent clock signal wirings and no voltage waveform deformation is observed with the level-changing clock signal at that time.
  • the wiring area of the semiconductor substrate can be reduced by approximately 37% compared with that of the conventional arrangement in which clock signal wirings and ground wirings are alternately arranged.
  • a ground wiring for electrostatic shielding is arranged between respective two set of clock signal wirings as a technique for preventing degradation of signals due to electrostatic coupling between respective two sets of clock signal wirings in the above embodiments
  • a technique for preventing degradation of signals between respective two sets of clock signal wirings is not limited to this arrangement.
  • the present invention can also be realized by employing other techniques.
  • An example of such techniques involves increasing a distance between respective two sets of clock signal wirings to reduce stray capacities between adjacent two sets of clock signal wirings.
  • the present invention can be applied to and implemented by any oscillator as long as it generates multiphase clock signals having the same phase difference.
  • the present invention is not limited to the voltage-controlled differential ring oscillator and can be modified within a scope of claims.
  • the present invention can be applied to semiconductor integrated circuits having a multi-stage ring oscillator that generates multiphase clock signals having the same phase difference.

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  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Semiconductor Integrated Circuits (AREA)
  • Design And Manufacture Of Integrated Circuits (AREA)
  • Manipulation Of Pulses (AREA)
US10/333,010 2000-07-27 2001-07-18 Semiconductor integrated circuit Abandoned US20040090828A1 (en)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
JP2000-226825 2000-07-27
JP2000226825A JP3615692B2 (ja) 2000-07-27 2000-07-27 多相クロック発振回路
PCT/JP2001/006204 WO2002011284A1 (fr) 2000-07-27 2001-07-18 Circuit integre a semi-conducteurs

Related Child Applications (1)

Application Number Title Priority Date Filing Date
US11/008,957 Continuation US7158441B2 (en) 2000-07-27 2004-12-13 Semiconductor integrated circuit

Publications (1)

Publication Number Publication Date
US20040090828A1 true US20040090828A1 (en) 2004-05-13

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US10/333,010 Abandoned US20040090828A1 (en) 2000-07-27 2001-07-18 Semiconductor integrated circuit
US11/008,957 Expired - Lifetime US7158441B2 (en) 2000-07-27 2004-12-13 Semiconductor integrated circuit

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US (2) US20040090828A1 (ja)
JP (1) JP3615692B2 (ja)
KR (1) KR100706041B1 (ja)
CN (1) CN1252922C (ja)
TW (1) TW498539B (ja)
WO (1) WO2002011284A1 (ja)

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US20080043545A1 (en) * 2004-04-29 2008-02-21 Jan Vink Multiple Data Rate Ram Memory Controller
WO2008149981A1 (ja) 2007-06-08 2008-12-11 Nec Corporation 変調装置及びパルス波生成装置
JP2009021870A (ja) * 2007-07-12 2009-01-29 Sony Corp 信号生成装置、フィルタ装置、信号生成方法およびフィルタ方法
CN102265349B (zh) * 2008-11-05 2014-06-18 奈克斯特生物测定学公司 用于降低电路复杂度的非二进制解码器架构以及控制信号逻辑
WO2017185072A1 (en) 2016-04-22 2017-10-26 Kandou Labs, S.A. High performance phase locked loop
US10193716B2 (en) 2016-04-28 2019-01-29 Kandou Labs, S.A. Clock data recovery with decision feedback equalization
US10411922B2 (en) 2016-09-16 2019-09-10 Kandou Labs, S.A. Data-driven phase detector element for phase locked loops
CN115333530A (zh) 2017-05-22 2022-11-11 康杜实验室公司 多模式数据驱动型时钟恢复方法和装置
US10554380B2 (en) 2018-01-26 2020-02-04 Kandou Labs, S.A. Dynamically weighted exclusive or gate having weighted output segments for phase detection and phase interpolation
EP3807996B1 (en) 2018-06-12 2022-07-06 Kandou Labs SA Low latency combined clock data recovery logic network and charge pump circuit
US10958251B2 (en) 2019-04-08 2021-03-23 Kandou Labs, S.A. Multiple adjacent slicewise layout of voltage-controlled oscillator
US11463092B1 (en) 2021-04-01 2022-10-04 Kanou Labs Sa Clock and data recovery lock detection circuit for verifying lock condition in presence of imbalanced early to late vote ratios
US11563605B2 (en) 2021-04-07 2023-01-24 Kandou Labs SA Horizontal centering of sampling point using multiple vertical voltage measurements
US11496282B1 (en) 2021-06-04 2022-11-08 Kandou Labs, S.A. Horizontal centering of sampling point using vertical vernier

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US6426662B1 (en) * 2001-11-12 2002-07-30 Pericom Semiconductor Corp. Twisted-ring oscillator and delay line generating multiple phases using differential dividers and comparators to match delays

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US6426662B1 (en) * 2001-11-12 2002-07-30 Pericom Semiconductor Corp. Twisted-ring oscillator and delay line generating multiple phases using differential dividers and comparators to match delays

Also Published As

Publication number Publication date
CN1252922C (zh) 2006-04-19
US7158441B2 (en) 2007-01-02
US20050104673A1 (en) 2005-05-19
KR20030047994A (ko) 2003-06-18
JP2002043905A (ja) 2002-02-08
JP3615692B2 (ja) 2005-02-02
CN1444797A (zh) 2003-09-24
KR100706041B1 (ko) 2007-04-11
WO2002011284A1 (fr) 2002-02-07
TW498539B (en) 2002-08-11

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