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TWI730351B - 內埋元件封裝結構 - Google Patents

內埋元件封裝結構 Download PDF

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TWI730351B
TWI730351B TW108124007A TW108124007A TWI730351B TW I730351 B TWI730351 B TW I730351B TW 108124007 A TW108124007 A TW 108124007A TW 108124007 A TW108124007 A TW 108124007A TW I730351 B TWI730351 B TW I730351B
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Taiwan
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conductive pillars
height
dielectric structure
package structure
conductive
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TW108124007A
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TW202040765A (zh
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廖玉茹
陳建汎
王建皓
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日月光半導體製造股份有限公司
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Abstract

一種內埋元件封裝結構及其製造方法。內埋元件封裝結構包括一介電結構以及一元件。元件內埋於介電結構中並設有複數個導電柱，此些導電柱係自介電結構的一上表面露出且分別具有一第一厚度及一第二厚度，第一厚度不等於第二厚度。

Description

內埋元件封裝結構
本發明是有關於一種元件封裝結構及其製造方法，且特別是有關於一種內埋元件封裝結構及其製造方法。
在系統級封裝結構中，將半導體晶片埋入封裝基板中的內埋元件技術(Semiconductor Embedded in SUBstrate，簡稱SESUB)，因為具有降低封裝基板產品受到雜訊干擾及產品尺寸減小的優點，近年來已成為本領域製造商的研發重點。為了提高生產的良率，內埋元件必須固定在線路基板的介電結構內，以利於後續製作的圖案化導電層能與內埋元件電性連接。
然而，當內埋元件因翹曲而變形，位於翹曲表面上的電性接墊將無法在同一高度上，因而增加後續導電通孔製程的難度及降低製程的良率。
本發明係有關於一種內埋元件封裝結構及其製造方法，可避免噴砂製程對內埋元件產生的傷害，並可提高內埋元件封裝製程的良率。
根據本發明之一方面，提出一種內埋元件封裝結構，其包括一介電結構以及一元件。元件內埋於介電結構中並設有複數個導電柱，此些導電柱係自介電結構的一上表面露出且分別具有一第一厚度及一第二厚度，第一厚度不等於第二厚度。
根據本發明之一方面，提出一種內埋元件封裝結構，其包括一介電結構以及一元件。元件內埋於介電結構中並設有複數個導電柱，此些導電柱各別具有一中心線，此些中心線相對於垂直線具有一第一傾斜角以及一第二傾斜角，第一傾斜角不等於第二傾斜角。
根據本發明之一方面，提出一種內埋元件封裝結構的製造方法，包括下列步驟。提供一半導體晶片於一載體上，半導體晶片設有複數個導電柱，半導體晶片具有一翹曲量使此些導電柱位於不同高度。提供一介電結構於載體上，介電結構覆蓋半導體晶片及此些導電柱。移除部分介電結構及此些導電柱的一部分。
為了對本發明之上述及其他方面有更佳的瞭解，下文特舉實施例，並配合所附圖式詳細說明如下：
100、110:內埋元件封裝結構
101:載體
102:介電材料
104:下導電層
104a:第二銲墊
105:盲孔
106:導電盲孔
108:第二焊罩層
111:元件
112:電性接墊
113a:重佈線層
113b:絕緣層
114:導電柱
114a、116a:上表面
115:導電層
115a:種子層
115b:電鍍銅層
116:介電結構
116b:盲孔
117、118b:導電盲孔
118:介電層
118a:盲孔
119:上導電層
119a:第一銲墊
120:第一焊罩層
△H:翹曲量
A、B:盲孔區域
C1-C3:中心線
D1:最小孔徑
D2:最小尺寸
D3:最小尺寸
H1:厚度
T1:第一厚度
T2:第二厚度
T:原始厚度
S1:第一側邊
S2:第二側邊
V:垂直線
θ1:第一傾斜角
θ2:第二傾斜角
θ3:第三傾斜角
第1A及1B圖繪示對內埋元件封裝結構進行噴砂製程的局部示意圖。
第2圖繪示依照本發明一實施例的內埋元件封裝結構的局部剖面 示意圖，其中內埋元件具有一翹曲量。
第3A至3E圖繪示依照本發明一實施例的內埋元件封裝結構的製造方法的流程圖。
第4A至4E圖繪示依照本發明另一實施例的內埋元件封裝結構的製造方法的流程圖。
第5A至5F圖繪示依照本發明另一實施例的內埋元件封裝結構的製造方法的流程圖。
第6A至6F圖繪示依照本發明另一實施例的內埋元件封裝結構的製造方法的流程圖。
第7A至7K圖繪示依照本發明另一實施例的內埋元件封裝結構的製造方法的流程圖。
以下係提出實施例進行詳細說明，實施例僅用以作為範例說明，並非用以限縮本發明欲保護之範圍。以下是以相同/類似的符號表示相同/類似的元件做說明。以下實施例中所提到的方向用語，例如：上、下、左、右、前或後等，僅是參考所附圖式的方向。因此，使用的方向用語是用來說明並非用來限制本發明。
請參照第1A及1B圖，其繪示對內埋元件封裝結構100進行噴砂製程的局部示意圖。首先，提供一元件111，並將元件111內埋於一介電結構116中。內埋元件111的上表面例如設有複數個電性接墊112。介電結構116的材料例如為樹脂，此 樹脂可加熱固化而將元件111固定於介電結構116中。然而，當內埋元件111的翹曲量△H大於15微米時，由於翹曲表面上的各電性接墊112與介電結構116的上表面的距離各自不同，即各電性接墊112不在同一平面上，將不利於進行噴砂製程以形成盲孔。如第1B圖所示，一部分盲孔區域A過度噴砂而造成內埋元件111受損，另一部分盲孔區域B因噴砂量不足而未形成足夠深度的盲孔。因此，如何在內埋元件111出現翹曲或傾斜現象(例如翹曲量大於10微米)時，仍能進行後續的內埋元件封裝製程，實為亟待解決的重要的課題。
此外，目前噴砂製程形成的盲孔的最小孔徑D1無法小於40微米，因此位於盲孔下方的電性接墊112的最小尺寸D2也無法小於60微米，因而無法縮小電性接墊112之間的間距。
依照本發明之一實施例，提出一種內埋元件封裝結構，不需藉由噴砂製程來形成盲孔，因而可避免因內埋元件(例如半導體晶片)翹曲而產生的後續盲孔深度過深或不足的問題。
請參照第2圖，內埋元件封裝結構110包括一元件111以及一介電結構116。元件111內埋於介電結構116中並設有複數個導電柱114，此些導電柱114係自介電結構116的一上表面露出且分別具有一第一厚度T1及一第二厚度T2，第一厚度T1不等於第二厚度T2。在一實施例中，第一厚度T1可大於第二厚度T2。在另一實施例中，第一厚度T1可小於第二厚度T2。
在一實施例中，第一厚度T1與第二厚度T2的差 值用以補償因元件111翹曲而產生的高度差(△H)，也就是說，第一厚度T1與第二厚度T2的差值實質上等於元件111最高處與最低處之間的高度差(△H)，如第2圖所示。
在一實施例中，第一厚度T1與第二厚度T2相差至少10微米，例如10-25微米左右。同樣，元件111的翹曲量△H例如介於10-25微米之間。此外，導電柱114的原始厚度(以T表示於第3A圖中)可設定為元件翹曲量△H與導電柱114研磨後的最小厚度的總和，例如當元件翹曲量為20微米時，導電柱114的原始厚度T可設定為28微米。
在一實施例中，導電柱114研磨後的最小厚度至少大於3微米，即第一厚度T1及第二厚度T2至少大於3微米，以避免研磨到元件表面而損傷元件111。另外，為了進一步考量研磨製程的誤差值(例如±5微米)，導電柱114的最終厚度應大於或等於研磨製程的誤差值與導電柱114研磨後的最小厚度的總和，即第一厚度T1及第二厚度T2至少大於或等於8微米。
請參照第2圖，導電柱114具有一第一側邊S1以及一第二側邊S2，其中第一側邊S1的長度不等於第二側邊S2的長度。也就是說，受到元件111翹曲或傾斜的影響，導電柱114研磨後的第一側邊S1的長度可大於第二側邊S2的長度。由第2圖所繪示的垂直線V來看，第一側邊S1與第二側邊S2位於垂直線V的相對兩側，其中第一側邊S1相對於第二側邊S2位於翹曲量較小的一側，而第二側邊S2相對位於翹曲量較大的一側。
另外，請參照第2圖，導電柱114各別具有一中心線C1-C3，且此些中心線C1-C3相對於垂直線V至少具有一第一傾斜角θ1以及一第二傾斜角θ2，第一傾斜角θ1不等於第二傾斜角θ2。也就是說，受到元件111翹曲或傾斜的影響，各導電柱114的下表面位於不同高度的水平上，且各導電柱114具有不同的傾斜角，其中第一傾斜角θ1例如小於第二傾斜角θ2。另外，位於最外側的導電柱114例如還具有大於第一傾斜角θ1與第二傾斜角θ2的一第三傾斜角θ3，第一傾斜角θ1至第三傾斜角θ3的大小例如由元件111中央往相對兩側依序增加，且傾斜角度θ1至θ3的範圍例如介於1至10度之間。
然而，在另一實施例中，當元件111的相對兩側相對於中央向下彎曲而非向上彎曲時，第2圖中各導電柱114的第一側邊S1的長度可小於第二側邊S2的長度，而第一厚度T1可小於第二厚度T2。本發明對此不加以限制。
請參照第2圖，內埋元件封裝結構110更可包括一導電層115，其覆蓋介電結構116，並與導電柱114電性連接。導電層115例如包括一無電電鍍的種子層115a與一電鍍銅層115b，導電層115可經由微影蝕刻製程以形成一圖案化線路層。在本實施例中，利用導電柱114來取代傳統的導電盲孔，且導電柱114的最小尺寸D3(直徑)可減少至30微米以下，因此位於導電柱114下方的電性接墊112的最小尺寸也可減少至50微米以下，因而可進一步縮小電性接墊112之間的間距，例如小於80 微米。
在一實施例中，電性接墊112可為鋁墊，而導電柱114可直接形成在鋁墊上，或者，電性接墊112可為重佈線層的一接墊部分。在形成導電柱114之前，可先形成一重佈線層113a於元件表面的一絕緣層113b(例如氮氧化物)上，再將導電柱114分別設置於重佈線層113a的電性接墊112上。本發明對此不加以限制。
請參照第3A至3E圖，其繪示依照本發明一實施例的內埋元件封裝結構110的製造方法的流程圖。在第3A圖中，提供一元件111(例如半導體晶片)於一載體101上，載體101可為一預先形成一介電材料102的金屬基板，元件111設有複數個導電柱114，其中元件111具有一翹曲量△H使此些導電柱114位於不同高度。也就是說，受到元件111翹曲或傾斜的影響，各導電柱114的上表面114a具有不同高度。為了使各導電柱114的上表面114a具有相同高度，後續需進行壓膜以及研磨製程。
請參照第3B圖，提供一介電結構116於載體101上，介電結構116覆蓋元件111及此些導電柱114。介電結構116可由半固化態的介電材料(例如樹脂)以壓膜的方式覆蓋在元件111上並經由加熱固化而形成介電結構116。為了使介電材料具有良好的壓合均勻性，壓膜的厚度H1例如大於12微米。請參照第3C圖，移除部分介電結構116及此些導電柱114的一部分，以使各導電柱114的上表面114a與介電結構116的上表面116a 具有相同高度(相互切齊，不管有無研磨製程的誤差值)。在本實施例中，研磨前與研磨後的介電結構116的高度差至少大於或等於元件111的翹曲量，即H1-H2
Figure 108124007-A0305-02-0010-1
△H，以使導電柱114自介電結構116的上表面116a露出且分別具有不同高度，即具有第一厚度T1及第二厚度T2，第一厚度T1不等於第二厚度T2。元件111的翹曲量△H例如介於10至25微米之間。然而，在其他可控制的條件下，當元件111的翹曲量△H大於25微米時，仍可應用本發明來提高封裝製程的良率。
請參照第3D圖，提供一導電層115以覆蓋介電結構116的上表面116a，包括先形成一無電電鍍的種子層115a於介電結構116的上表面，再形成一電鍍銅層115b於種子層115a上。導電層115與導電柱114電性連接。接著，請參照第3E圖，蝕刻部分導電層115，以形成一圖案化導電層115。
請參照第4A至4E圖，其繪示依照本發明另一實施例的內埋元件封裝結構110的製造方法的流程圖。本實施例與上述實施例不同之處在於，在第4D圖中，將導電層115(例如銅箔)壓合在半固化態的介電結構116上，再加熱固化樹脂以將元件111固定於介電結構116中。接著，蝕刻部分導電層115，以形成一圖案化導電層115。其餘步驟如上述實施例所述，在此不再贅述。
請參照第5A至5F圖，其繪示依照本發明另一實施例的內埋元件封裝結構110的製造方法的流程圖。本實施例與 上述二實施例不同之處在於，在第5B圖中，先移除導電柱114的一部分，以使各導電柱114的上表面114a具有相同高度。在本實施例中，研磨前與研磨後的導電柱114的高度差大於或等於元件111的翹曲量△H，即第一厚度T1與第二厚度T2相差大致上等於元件111的翹曲量△H。接著，提供一介電結構116於載體101上，介電結構116覆蓋元件111及此些導電柱114。移除部分介電結構116，以使導電柱114自介電結構116的上表面116a露出。其餘步驟如上述實施例所述，在此不再贅述。
請參照第6A至6F圖，其繪示依照本發明另一實施例的內埋元件封裝結構110的製造方法的流程圖。如第6B圖所示，先移除導電柱114的一部分，以使各導電柱114的上表面114a具有相同高度。接著，在第6E圖中，將導電層115(例如銅箔)壓合在半固化態的介電結構116上，再加熱固化樹脂以將元件111固定於介電結構116中。其餘步驟如上述實施例所述，在此不再贅述。
請參照第7A至7K圖，其繪示依照本發明另一實施例的內埋元件封裝結構110的製造方法的流程圖。第7A至7C圖的步驟已於上述實施例中提及，用以提供一元件111(例如半導體晶片)於一載體101上，以介電結構116覆蓋元件111及此些導電柱114，並移除部分介電結構116及此些導電柱114的一部分。在第7D圖中，以噴砂或蝕刻方式形成至少一盲孔116b於介電結構116中，接著，在第7E圖中，形成一上導電層115於 介電結構116的上表面，且上導電層115延伸至盲孔116b中成為導電盲孔117與下導電層103電性連接。在第7F圖中，形成圖案化的上導電層115，接著，在第7G圖中，形成一介電層118(例如含玻纖的樹脂)於介電結構116上，並壓合另一上導電層119(例如銅箔)在介電層118上，再加熱固化樹脂以使二個上導電層115、119相互疊合。在第7H圖中，形成多個盲孔118a於介電層118中，接著，在第7I圖中，形成一無電電鍍的種子層於上導電層119的上表面及盲孔118a中，再形成一電鍍銅層於種子層上，以使二個上導電層115、119之間經由導電盲孔118b電性連接。此外，在第7H圖中，載體101更可包括另一下導電層104，經由蝕刻下導電層104以形成圖案化的下導電層104，並以噴砂形成多個盲孔105於載體101中，接著，在第7I圖中，形成一無電電鍍的種子層於下導電層104上及盲孔105中，再形成一電鍍銅層於種子層上，以使二個下導電層103、104之間經由導電盲孔106電性連接。
在第7J圖中，形成圖案化的上導電層119以及圖案化的下導電層104，接著，在第7K圖中，形成圖案化的第一焊罩層120(solder mask layer)於圖案化的上導電層119上，並顯露出部分上導電層119做為多個第一銲墊119a；以及形成圖案化的第二焊罩層108於圖案化的下導電層104上，並顯露出部分下導電層104做為多個第二銲墊104a。
在本實施例中，由於半導體晶片上預先形成不等高 的導電柱114，因此不需藉由噴砂製程來形成盲孔，因而可避免因內埋元件(例如半導體晶片)翹曲而產生的後續盲孔深度過深或不足的問題。同時，研磨後各導電柱114的上表面具有相同高度，因而方便後續壓膜製程及穿孔製程，進而提高製作導電層及導電盲孔的良率。
綜上所述，雖然本發明已以實施例揭露如上，然其並非用以限定本發明。本發明所屬技術領域中具有通常知識者，在不脫離本發明之精神和範圍內，當可作各種之更動與潤飾。因此，本發明之保護範圍當視後附之申請專利範圍所界定者為準。
110:內埋元件封裝結構
111:元件
112:電性接墊
113a:重佈線層
113b:絕緣層
114:導電柱
115:導電層
115a:種子層
115b:電鍍銅層
116:介電結構
△H:翹曲量
T1:第一厚度
T2:第二厚度
S1:第一側邊
S2:第二側邊
V:垂直線
C1-C3:中心線
D3:最小尺寸
θ1:第一傾斜角
θ2:第二傾斜角
θ3:第三傾斜角

Claims (20)

  1. 一種內埋元件封裝結構，包括：一介電結構；一元件，內埋於該介電結構中，其中該元件設有複數個導電柱，該些導電柱係自該介電結構的一上表面露出且該些導電柱各分別具有一第一高度及一第二高度，該第一高度不等於該第二高度；以及一導電層，覆蓋該介電結構，並與該些導電柱電性連接。
  2. 如申請專利範圍第1項所述之封裝結構，其中該元件具有一翹曲量介於10至25微米之間。
  3. 如申請專利範圍第1項所述之封裝結構，其中該元件設有一重佈線層以及一絕緣層，該重佈線層設置於該絕緣層上，且該重佈線層具有複數個電性接墊，該些導電柱設置於該些電性接墊上。
  4. 如申請專利範圍第1項所述之封裝結構，其中該第一高度與該第二高度相差至少10微米。
  5. 如申請專利範圍第1項所述之封裝結構，其中該第一高度及該第二高度至少大於3微米。
  6. 如申請專利範圍第1項所述之封裝結構，其中該些導電柱的上表面切齊該介電結構的該上表面，且該些導電柱的下表面位於不同高度的水平上。
  7. 如申請專利範圍第1項所述之封裝結構，其中該些導電柱具有一第一側邊以及一第二側邊，該第一側邊的長度係不等於該第二側邊的長度。
  8. 如申請專利範圍第1項所述之封裝結構，其中該些導電柱各 別具有一中心線，該些中心線相對於垂直線具有一第一傾斜角以及一第二傾斜角，該第一傾斜角不等於該第二傾斜角。
  9. 如申請專利範圍第1項所述之封裝結構，其中該些導電柱中之至少一者具有一側表面直接接觸該介電結構。
  10. 如申請專利範圍第1項所述之封裝結構，其中該些導電柱中之至少一者具有一致的一寬度在平行於該介電結構之該上表面的一方向上測得。
  11. 一種內埋元件封裝結構，包括：一介電結構；以及一元件，內埋於該介電結構中，其中該元件設有複數個導電柱，該些導電柱各別具有一中心線，該些中心線相對於垂直線具有一第一傾斜角以及一第二傾斜角，該第一傾斜角不等於該第二傾斜角。
  12. 如申請專利範圍第11項所述之封裝結構，其中該元件具有一翹曲量介於10至25微米之間。
  13. 如申請專利範圍第11項所述之封裝結構，其中該元件設有一重佈線層以及一絕緣層，該重佈線層設置於該絕緣層上，且該重佈線層具有複數個電性接墊，該些導電柱設置於該些電性接墊上。
  14. 如申請專利範圍第11項所述之封裝結構，其中該些導電柱的上表面切齊該介電結構的一上表面，且該些導電柱的下表面位於不同高度的水平上。
  15. 如申請專利範圍第14項所述之封裝結構，其中該些導電柱係自該介電結構的該上表面露出且該等導電柱各分別具有一第一高度及一第二高度，該第一高度不等於該第二高度。
  16. 如申請專利範圍第15項所述之封裝結構，其中該第一高度與該第二高度相差至少10微米。
  17. 如申請專利範圍第15項所述之封裝結構，其中該第一高度及該第二高度至少大於3微米。
  18. 如申請專利範圍第11項所述之封裝結構，其中該些導電柱具有一第一側邊以及一第二側邊，該第一側邊的長度係不等於該第二側邊的長度。
  19. 如申請專利範圍第11項所述之封裝結構，更包括一導電層，覆蓋該介電結構，並與該些導電柱電性連接。
  20. 一種內埋元件封裝結構，包括：一介電結構；以及一元件，內埋於該介電結構中，其中該元件設有複數個導電柱，該些導電柱係自該介電結構的一上表面露出且該些導電柱各分別具有一第一高度及一第二高度，該第一高度不等於該第二高度，其中該些導電柱中之至少一者具有一側表面直接接觸該介電結構。
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