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TWI781017B - Test system and test circuit thereof - Google Patents

Test system and test circuit thereof Download PDF

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TWI781017B
TWI781017B TW110147398A TW110147398A TWI781017B TW I781017 B TWI781017 B TW I781017B TW 110147398 A TW110147398 A TW 110147398A TW 110147398 A TW110147398 A TW 110147398A TW I781017 B TWI781017 B TW I781017B
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test
delay
circuit
command
signal
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TW110147398A
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TW202326744A (en
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石原政廣
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力晶積成電子製造股份有限公司
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Priority to CN202210004695.5A priority patent/CN116266471A/en
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    • GPHYSICS
    • G11INFORMATION STORAGE
    • G11CSTATIC STORES
    • G11C29/00Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
    • G11C29/04Detection or location of defective memory elements, e.g. cell constructio details, timing of test signals
    • G11C29/08Functional testing, e.g. testing during refresh, power-on self testing [POST] or distributed testing
    • G11C29/12Built-in arrangements for testing, e.g. built-in self testing [BIST] or interconnection details
    • G11C29/12015Built-in arrangements for testing, e.g. built-in self testing [BIST] or interconnection details comprising clock generation or timing circuitry
    • GPHYSICS
    • G11INFORMATION STORAGE
    • G11CSTATIC STORES
    • G11C29/00Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
    • G11C29/04Detection or location of defective memory elements, e.g. cell constructio details, timing of test signals
    • G11C29/08Functional testing, e.g. testing during refresh, power-on self testing [POST] or distributed testing
    • G11C29/10Test algorithms, e.g. memory scan [MScan] algorithms; Test patterns, e.g. checkerboard patterns 

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  • Pharmaceuticals Containing Other Organic And Inorganic Compounds (AREA)

Abstract

The present invention provides a test system and test circuit thereof. The test circuit includes a command decoder, a trigger signal generator, a delay control signal generator, a delay circuit and a test data generator. The command decoder generates an adjustment signal by decoding a test command. The trigger signal generator generates a trigger signal according to a clock signal. The delay control signal generator generates a delay control signal according to the adjustment signal. The delay circuit generates a unit delay according to the delay control signal and delays the trigger signal based on the unit delay to generate a plurality of sampling clocks. The test data generator samples a preset data according to the sampling clock to obtain a test output signal. The test data generator has obtained a test output signal by sampling test data according to the sampling clocks.

Description

測試系統以及其測試電路Test system and its test circuit

本發明是有關於一種測試系統以及其測試電路,且特別是有關於一種記憶體測試系統以及記憶體測試電路。The present invention relates to a test system and its test circuit, and in particular to a memory test system and a memory test circuit.

現今動態隨機存取記憶體(Dynamic Random Access Memory,DRAM)之主流輸入/輸出架構為雙倍資料率(Double Data Rate,DDR)架構。由於DDR架構於匯流排時脈的上升緣及下降緣各傳輸一次資料,因此其資料傳輸頻率為匯流排時脈頻率的兩倍。以現今第四代雙倍資料率(DDR4)的規格為例,於一般使用情況下,其匯流排時脈頻率可高達約1.6GHz,因此DDR4的資料傳輸頻率可高達3.2GHz。The current mainstream I/O architecture of Dynamic Random Access Memory (DRAM) is Double Data Rate (DDR) architecture. Since the DDR architecture transmits data on the rising and falling edges of the bus clock, its data transmission frequency is twice the bus clock frequency. Taking the current fourth-generation double data rate (DDR4) specification as an example, under normal usage conditions, the bus clock frequency can be as high as about 1.6GHz, so the data transmission frequency of DDR4 can be as high as 3.2GHz.

然而,於記憶體晶片的產品測試應用中,尤其在晶圓級的測試條件下,難以提供記憶體高達一般使用情況下的所需頻率(例如:1.6GHz)。於晶圓級的高速測試機,通常所能提供的測試頻率最高僅能達到約100MHz,遠低於DDR記憶體於一般使用情況下的所需頻率。更由於高速測試機造價昂貴,若要更大幅提高其測試頻率,於現今條件下幾乎難以達成。因此現今的晶圓級的記憶體測試,將受限於測試機的測試頻率,使得測試時所提供給記憶體的時脈頻率,遠低於一般使用情況下記憶體的所需時脈頻率,而使測試時間大幅拉長,進而拉高了記憶體晶片的製造成本。However, in the application of product testing of memory chips, especially under wafer-level test conditions, it is difficult to provide memory with a frequency as high as that required in general use (for example: 1.6 GHz). A high-speed testing machine at the wafer level can usually provide a test frequency up to about 100MHz, which is far lower than the required frequency of DDR memory in general use. Furthermore, due to the high cost of high-speed testing machines, it is almost impossible to achieve a greater increase in testing frequency under current conditions. Therefore, the current wafer-level memory test will be limited by the test frequency of the testing machine, so that the clock frequency provided to the memory during the test is much lower than the required clock frequency of the memory under normal use. As a result, the test time is greatly lengthened, thereby raising the manufacturing cost of the memory chip.

本發明提供一種測試電路,可透過具有較低頻率的時脈信號來完成記憶體內部的測試動作。The invention provides a test circuit, which can complete the test action inside the memory through the clock signal with a lower frequency.

本發明的測試電路包括命令解碼電路、觸發信號產生器、延遲控制信號產生器、延遲電路以及測試資料產生器。命令解碼電路根據解碼測試命令以產生調整信號。觸發信號產生器根據輸入時脈信號以產生觸發信號。延遲控制信號產生器耦接於命令解碼電路,並根據調整信號以產生延遲控制信號。延遲電路耦接於延遲控制信號產生器以及觸發信號產生器,以依據延遲控制信號產生單位延遲,並基於單位延遲對觸發信號進行延遲以產生多個取樣時脈。測試資料產生器依據多個取樣時脈取樣測試資料,以獲得測試輸出信號。The test circuit of the present invention includes a command decoding circuit, a trigger signal generator, a delay control signal generator, a delay circuit and a test data generator. The command decoding circuit generates an adjustment signal according to the decoded test command. The trigger signal generator generates a trigger signal according to the input clock signal. The delay control signal generator is coupled to the command decoding circuit and generates a delay control signal according to the adjustment signal. The delay circuit is coupled to the delay control signal generator and the trigger signal generator to generate a unit delay according to the delay control signal, and delay the trigger signal based on the unit delay to generate a plurality of sampling clocks. The test data generator samples test data according to a plurality of sampling clocks to obtain test output signals.

本發明的測試系統包括測試機以及測試電路。測試機耦接測試電路。測試電路包括命令解碼電路、觸發信號產生器、延遲控制信號產生器、延遲電路以及測試資料產生器。命令解碼電路根據解碼測試命令以產生調整信號。觸發信號產生器根據輸入時脈信號以產生觸發信號。延遲控制信號產生器耦接於命令解碼電路,並根據調整信號以產生延遲控制信號。延遲電路耦接於延遲控制信號產生器以及觸發信號產生器,以依據延遲控制信號產生單位延遲,並基於單位延遲對觸發信號進行延遲以產生多個取樣時脈。測試資料產生器依據多個取樣時脈取樣測試資料,以獲得測試輸出信號。其中測試機用以提供測試命令以及輸入時脈信號至測試電路,以及接收該測試輸出信號,並根據該測試輸出信號以產生測試結果。The testing system of the present invention includes a testing machine and a testing circuit. The testing machine is coupled to the testing circuit. The test circuit includes a command decoding circuit, a trigger signal generator, a delay control signal generator, a delay circuit and a test data generator. The command decoding circuit generates an adjustment signal according to the decoded test command. The trigger signal generator generates a trigger signal according to the input clock signal. The delay control signal generator is coupled to the command decoding circuit and generates a delay control signal according to the adjustment signal. The delay circuit is coupled to the delay control signal generator and the trigger signal generator to generate a unit delay according to the delay control signal, and delay the trigger signal based on the unit delay to generate a plurality of sampling clocks. The test data generator samples test data according to a plurality of sampling clocks to obtain test output signals. The test machine is used to provide test commands and input clock signals to the test circuit, receive the test output signals, and generate test results according to the test output signals.

基於上述,本發明的測試電路以及測試系統,可使用較低頻率的外部時脈信號輸入測試電路,得到較高的時脈信號頻率的測試輸出信號,以完成記憶體內部的測試動作。在不增加測試機硬體成本的前提下,測試電路可輸出相對外部輸入時脈信號較高頻的輸出信號以縮短測試時間。另外本發明的技術方案,除了不增加測試機硬體成本外,亦不須使用於測試電路的時脈輸入端耦接倍頻器的技術,例如使用鎖相迴路(Phase Locked Loop,PLL)等技術方案,因此不會提高測試系統的成本以及複雜度。Based on the above, the test circuit and test system of the present invention can use a lower frequency external clock signal to input the test circuit to obtain a test output signal with a higher clock signal frequency to complete the internal test operation of the memory. On the premise of not increasing the hardware cost of the tester, the test circuit can output an output signal with a higher frequency than the external input clock signal to shorten the test time. In addition, the technical solution of the present invention, in addition to not increasing the hardware cost of the testing machine, also does not need to use the technology of coupling the clock pulse input end of the testing circuit to the frequency multiplier, such as using a phase locked loop (Phase Locked Loop, PLL), etc. Therefore, the cost and complexity of the test system will not be increased.

請參照圖1,圖1為本發明一實施例的測試電路的示意圖。測試電路100包括命令解碼器110、觸發信號產生器120、延遲控制信號產生器130、延遲電路140以及測試資料產生器150。其中延遲控制信號產生器130耦接命令解碼器110以及延遲電路140,延遲電路140還耦接觸發信號產生器120以及測試資料產生器150。Please refer to FIG. 1 , which is a schematic diagram of a test circuit according to an embodiment of the present invention. The test circuit 100 includes a command decoder 110 , a trigger signal generator 120 , a delay control signal generator 130 , a delay circuit 140 and a test data generator 150 . The delay control signal generator 130 is coupled to the command decoder 110 and the delay circuit 140 , and the delay circuit 140 is also coupled to the trigger signal generator 120 and the test data generator 150 .

命令解碼器110接收並解碼來自外部例如測試機所提供的測試命令CMD。觸發信號產生器120接收來自外部例如測試機所提供的時脈信號CLK,時脈信號CLK可以為一週期性時脈信號,觸發信號產生器120依據時脈信號CLK以產生一觸發信號TG。觸發信號產生器120可依據時脈信號CLK的轉態緣來產生觸發信號TG,其中轉態緣可以為上升緣及/或下降緣。測試資料產生器150則用以輸出測試輸出信號DOUT。The command decoder 110 receives and decodes a test command CMD from an external source such as a test machine. The trigger signal generator 120 receives a clock signal CLK from an external source such as a testing machine. The clock signal CLK may be a periodic clock signal. The trigger signal generator 120 generates a trigger signal TG according to the clock signal CLK. The trigger signal generator 120 can generate the trigger signal TG according to a transition edge of the clock signal CLK, wherein the transition edge can be a rising edge and/or a falling edge. The test data generator 150 is used to output the test output signal DOUT.

命令解碼器110針對測試命令CMD進行解碼,並產生調整信號TCODE。命令解碼器110並提供調整信號TCODE至延遲控制信號產生器130。延遲控制信號產生器130依據調整信號TCODE來產生延遲控制信號Dctrl。延遲電路140可依據延遲控制信號Dctrl來設定單位延遲,並基於所設定的單位延遲,延遲觸發信號TG一次至多次,以依序產生多個取樣時脈SCK1~SCKn。值得注意的是,由於觸發信號TG是依據時脈信號CLK的波形的觸發所產生,並且延遲電路140依據所述單位延遲,將觸發信號TG多次延遲而產生取樣時脈SCK1~SCKn;亦即,時脈信號CLK的每個週期將產生取樣時脈SCK1~SCKn。此意味著取樣時脈SCK1~SCKn的頻率將高於時脈信號CLK的頻率,且取樣時脈SCK1~SCKn的頻率可以由所述單位延遲的時間決定。The command decoder 110 decodes the test command CMD and generates an adjustment signal TCODE. The command decoder 110 provides the adjustment signal TCODE to the delay control signal generator 130 . The delay control signal generator 130 generates the delay control signal Dctrl according to the adjustment signal TCODE. The delay circuit 140 can set a unit delay according to the delay control signal Dctrl, and delay the trigger signal TG one or more times based on the set unit delay, so as to sequentially generate a plurality of sampling clocks SCK1˜SCKn. It should be noted that the trigger signal TG is generated according to the triggering of the waveform of the clock signal CLK, and the delay circuit 140 delays the trigger signal TG multiple times according to the unit delay to generate the sampling clocks SCK1˜SCKn; that is, , each period of the clock signal CLK will generate sampling clocks SCK1˜SCKn. This means that the frequency of the sampling clocks SCK1-SCKn will be higher than the frequency of the clock signal CLK, and the frequency of the sampling clocks SCK1-SCKn can be determined by the time of the unit delay.

測試資料產生器150依據取樣時脈SCK1~SCKn,以分別取樣多個測試資料PD1~PDn,以產生測試輸出信號DOUT。其中測試資料PD1~PDn可以為預先被寫入至測試電路100的暫存器(圖1未示出)的預設測試資料,或為由積體電路根據測試動作所產生的測試資料(例如記憶體的讀出資料)。測試資料產生器150可以為一並列轉序列轉換器(parrel to serial converter),用以依據取樣時脈SCK1~SCKn,將測試資料PD1~PDn轉換成一串列資料,並藉以產生測試輸出信號DOUT。The test data generator 150 respectively samples a plurality of test data PD1 ˜ PDn according to the sampling clocks SCK1 ˜ SCKn to generate the test output signal DOUT. The test data PD1˜PDn can be the preset test data written into the temporary register (not shown in FIG. 1 ) of the test circuit 100 in advance, or the test data (such as memory Body readout data). The test data generator 150 can be a parallel to serial converter (parrel to serial converter), used to convert the test data PD1 ˜ PDn into serial data according to the sampling clocks SCK1 ˜ SCKn, and thereby generate the test output signal DOUT.

本實施例的測試電路100,可以內嵌在待測記憶體晶片中。依據上述實施方式,本實施例的測試電路100,可依據所輸入的測試命令CMD以及時脈信號CLK,輸出測試輸出信號DOUT,以完成記憶體內部的測試動作。且測試電路100的特徵在於,測試輸出信號DOUT的頻率較時脈信號CLK的頻率高。The test circuit 100 of this embodiment may be embedded in a memory chip to be tested. According to the above-mentioned implementation, the test circuit 100 of this embodiment can output the test output signal DOUT according to the input test command CMD and the clock signal CLK, so as to complete the internal test operation of the memory. And the test circuit 100 is characterized in that the frequency of the test output signal DOUT is higher than the frequency of the clock signal CLK.

請參照圖2,圖2為本發明另一實施例的測試電路的示意圖。測試電路200包括命令解碼器210、觸發信號產生器220、延遲控制信號產生器230、延遲電路240以及測試資料產生器250。其中延遲控制信號產生器230耦接命令解碼器210以及延遲電路240,延遲電路240還耦接觸發信號產生器220以及測試資料產生器250。其中命令解碼器210用以接收測試命令CMD,觸發信號產生器220用以接收時脈信號CLK,以及測試資料產生器250用以產生輸出測試信號DOUT。Please refer to FIG. 2 , which is a schematic diagram of a test circuit according to another embodiment of the present invention. The test circuit 200 includes a command decoder 210 , a trigger signal generator 220 , a delay control signal generator 230 , a delay circuit 240 and a test data generator 250 . The delay control signal generator 230 is coupled to the command decoder 210 and the delay circuit 240 , and the delay circuit 240 is also coupled to the trigger signal generator 220 and the test data generator 250 . The command decoder 210 is used to receive the test command CMD, the trigger signal generator 220 is used to receive the clock signal CLK, and the test data generator 250 is used to generate the output test signal DOUT.

測試電路200與圖1實施例的測試電路的不同處在於,延遲電路240包括依序串接的多個電壓控制延遲器VCD1~VCDn。如圖2所示,其中電壓控制延遲器VCD1的輸入端耦接至觸發信號產生器220,電壓控制延遲器VCD1的輸出端依序串接電壓控制延遲器VCD2~VCDn。其中電壓控制延遲器VCD1~VCDn共同耦接至延遲控制信號產生器230,且電壓控制延遲器VCD1~VCDn之輸出端分別耦接至測試資料產生器250。The difference between the test circuit 200 and the test circuit of the embodiment in FIG. 1 is that the delay circuit 240 includes a plurality of voltage-controlled delays VCD1 -VCDn connected in series. As shown in FIG. 2 , the input terminal of the voltage-controlled delay VCD1 is coupled to the trigger signal generator 220 , and the output terminal of the voltage-controlled delay VCD1 is sequentially connected to the voltage-controlled delays VCD2˜VCDn. The voltage-controlled delays VCD1 -VCDn are commonly coupled to the delay control signal generator 230 , and the output terminals of the voltage-controlled delays VCD1 -VCDn are respectively coupled to the test data generator 250 .

延遲控制信號產生器230依據來自命令解碼器210解碼測試命令CMD所產生的調整信號TCODE,以產生延遲控制信號Dctrl。其中延遲控制信號Dctrl可具有一電壓值,電壓控制延遲器VCD1~VCDn的每一者可依據延遲控制信號Dctrl的電壓值來產生單位延遲,並依序延遲觸發信號TG來產生多個取樣時脈SCK1~SCKn。在本實施例中,單位延遲的時間長度可由延遲控制信號Dctrl的電壓值決定。其中,單位延遲的時間長度可以與延遲控制信號Dctrl的電壓值正相關或負相關,沒有一定的限制。The delay control signal generator 230 generates the delay control signal Dctrl according to the adjustment signal TCODE generated by decoding the test command CMD from the command decoder 210 . The delay control signal Dctrl can have a voltage value, and each of the voltage-controlled delays VCD1˜VCDn can generate a unit delay according to the voltage value of the delay control signal Dctrl, and sequentially delay the trigger signal TG to generate a plurality of sampling clocks SCK1~SCKn. In this embodiment, the time length of the unit delay can be determined by the voltage value of the delay control signal Dctrl. Wherein, the time length of the unit delay may be positively or negatively correlated with the voltage value of the delay control signal Dctrl, and there is no certain limitation.

請參照圖3,圖3為本發明另一實施例的測試電路的示意圖。測試電路300包括命令解碼器310、觸發信號產生器320、延遲控制信號產生器330、延遲電路340以及測試資料產生器350。其中延遲控制信號產生器330耦接命令解碼器310以及延遲電路340,延遲電路340還耦接觸發信號產生器320以及測試資料產生器350。其中命令解碼器310用以接收測試命令CMD,觸發信號產生器320用以接收時脈信號CLK,以及測試資料產生器350用以產生輸出測試信號DOUT。Please refer to FIG. 3 , which is a schematic diagram of a test circuit according to another embodiment of the present invention. The test circuit 300 includes a command decoder 310 , a trigger signal generator 320 , a delay control signal generator 330 , a delay circuit 340 and a test data generator 350 . The delay control signal generator 330 is coupled to the command decoder 310 and the delay circuit 340 , and the delay circuit 340 is also coupled to the trigger signal generator 320 and the test data generator 350 . The command decoder 310 is used to receive the test command CMD, the trigger signal generator 320 is used to receive the clock signal CLK, and the test data generator 350 is used to generate the output test signal DOUT.

測試電路300與圖1實施例的測試電路的不同處在於,延遲電路340包括延遲線341以及選擇電路342,其中延遲線341可包括多個依序串接的延遲器D1~Dn。如圖3所示,其中延遲器D1的輸入端耦接至觸發信號產生器320,延遲器D1的輸出端依序串接延遲器D2~Dn。且其中延遲器D1~Dn之輸出端分別耦接至選擇電路342。選擇電路342耦接延遲控制信號產生器330與測試資料產生器350,並且選擇電路342將延遲器D1~Dn的輸出端的多個輸出訊號選擇性的提供至測試資料產生器350。The difference between the test circuit 300 and the test circuit in the embodiment shown in FIG. 1 is that the delay circuit 340 includes a delay line 341 and a selection circuit 342 , wherein the delay line 341 may include a plurality of delayers D1 -Dn connected in series. As shown in FIG. 3 , the input end of the delayer D1 is coupled to the trigger signal generator 320 , and the output end of the delayer D1 is sequentially connected to the delayers D2˜Dn. And the output terminals of the delays D1 ˜ Dn are respectively coupled to the selection circuit 342 . The selection circuit 342 is coupled to the delay control signal generator 330 and the test data generator 350 , and the selection circuit 342 selectively provides a plurality of output signals of the output terminals of the delayers D1 ˜Dn to the test data generator 350 .

其中延遲器D1~Dn中的每一者,可產生單位解析延遲,並依序延遲觸發訊號TG且輸出至選擇電路342。延遲控制信號產生器330依據調整信號TCODE來產生一延遲控制信號Dctrl,選擇電路342則可依據延遲控制信號Dctrl來選擇延遲器D1~Dn中的部份的輸出,來產生多個取樣時脈SCK1~SCKn,其中相位相近的二取樣時脈中具有一單位延遲。舉例而言,所設定的單位延遲的長度若為單位解析延遲長度的3倍,則延遲控制信號產生器330將延遲控制信號Dctrl提供給選擇電路342,選擇電路342將選擇延遲器D3、D6、D9…所產生的延遲訊號,提供給測試資料產生器350,以產生多個取樣時脈SCK1~SCKn。Each of the delays D1 ˜Dn can generate a unit resolution delay, and sequentially delay the trigger signal TG and output it to the selection circuit 342 . The delay control signal generator 330 generates a delay control signal Dctrl according to the adjustment signal TCODE, and the selection circuit 342 can select some outputs of the delayers D1~Dn according to the delay control signal Dctrl to generate a plurality of sampling clocks SCK1 ~SCKn, where there is a unit delay in two sampling clocks with similar phases. For example, if the length of the set unit delay is 3 times of the unit analysis delay length, the delay control signal generator 330 will provide the delay control signal Dctrl to the selection circuit 342, and the selection circuit 342 will select the delay devices D3, D6, The delay signal generated by D9 . . . is provided to the test data generator 350 to generate a plurality of sampling clocks SCK1˜SCKn.

請參照圖4A~4D,圖4A~4D例示圖3實施例的延遲線341的多個實施方式。在圖4A中,延遲線341包括依序串接的多個緩衝器BUF1~BUFn。另外在圖4B中,延遲線341另包括多個電阻電容網路,其中的每一個電阻電容網路可分別耦接至對應的緩衝器BUF1~BUFn的輸入端或輸出端,並用以提升上述的單位解析延遲的長度。在圖4B中,以電阻電容網路RCN為例,電阻電容網路RCN耦接緩衝器BUF1的輸出端。其中電阻R的一端耦接至緩衝器BUF1的輸出端,電阻R的另一端耦接電容C的一端,電容C的另一端則可耦接至參考接地端。Please refer to FIGS. 4A˜4D , which illustrate multiple implementations of the delay line 341 of the embodiment shown in FIG. 3 . In FIG. 4A , the delay line 341 includes a plurality of buffers BUF1 -BUFn connected in series. In addition, in FIG. 4B, the delay line 341 further includes a plurality of resistor-capacitor networks, each of which can be respectively coupled to the input or output terminals of the corresponding buffers BUF1~BUFn, and used to improve the above-mentioned The length of the parsing delay in units. In FIG. 4B , taking the resistor-capacitor network RCN as an example, the resistor-capacitor network RCN is coupled to the output terminal of the buffer BUF1 . One end of the resistor R is coupled to the output end of the buffer BUF1 , the other end of the resistor R is coupled to one end of the capacitor C, and the other end of the capacitor C can be coupled to the reference ground.

在圖4C中,延遲線341包括相互串接的多個反相器INV1~INVn。而在圖4D中,延遲線341還包括多個電阻電容網路。電阻電容網路可耦接於反相器INV1~INVn的每一個的輸入端或輸出端,並用以提升上述的單位解析延遲的長度。In FIG. 4C , the delay line 341 includes a plurality of inverters INV1 - INVn connected in series. In FIG. 4D , the delay line 341 further includes a plurality of resistor-capacitor networks. The resistor-capacitor network can be coupled to the input terminal or the output terminal of each of the inverters INV1˜INVn, and used to increase the length of the above-mentioned unit resolution delay.

請參照圖5,為本發明一實施例的測試系統示意圖。測試系統500包括測試電路510以及測試機520。測試機520連接至測試電路510以執行測試。其中測試機520用以提供測試命令CMD以及時脈信號CLK至測試電路510,並且接收來自測試電路510的測試輸出信號DOUT。在本實施例中,測試機520還可以提供測試選擇信號SEL至測試電路510,以致能測試電路510執行測試。Please refer to FIG. 5 , which is a schematic diagram of a test system according to an embodiment of the present invention. The testing system 500 includes a testing circuit 510 and a testing machine 520 . The testing machine 520 is connected to the testing circuit 510 to perform testing. The test machine 520 is used to provide the test command CMD and the clock signal CLK to the test circuit 510 and receive the test output signal DOUT from the test circuit 510 . In this embodiment, the testing machine 520 can also provide a test selection signal SEL to the testing circuit 510 to enable the testing circuit 510 to perform testing.

其中,如圖5所示,測試電路510包括命令解碼器511、觸發信號產生器512、延遲控制信號產生器513、延遲電路514、測試資料產生器515、輸出驅動器516、以及測試接收器517。其中命令解碼器511耦接至觸發信號產生器512、延遲控制信號產生器513以及測試接收器517。觸發信號產生器512還耦接至延遲電路514以及輸出驅動器516。延遲控制信號產生器513還耦接至延遲電路514。延遲電路514還耦接至測試資料產生器515。測試資料產生器515還耦接輸出驅動器516。其中命令解碼器511耦接至測試機520以接收測試命令CMD。觸發信號產生器512耦接至測試機520以接收時脈信號CLK。測試接收器517則耦接至測試機520以接收測試選擇信號SEL。輸出驅動器516耦接至測試機520,並用以輸出測試輸出信號DOUT以完成測試。Wherein, as shown in FIG. 5 , the test circuit 510 includes a command decoder 511 , a trigger signal generator 512 , a delay control signal generator 513 , a delay circuit 514 , a test data generator 515 , an output driver 516 , and a test receiver 517 . The command decoder 511 is coupled to the trigger signal generator 512 , the delay control signal generator 513 and the test receiver 517 . The trigger signal generator 512 is also coupled to a delay circuit 514 and an output driver 516 . The delay control signal generator 513 is also coupled to the delay circuit 514 . The delay circuit 514 is also coupled to the test data generator 515 . The test data generator 515 is also coupled to the output driver 516 . The command decoder 511 is coupled to the testing machine 520 to receive the testing command CMD. The trigger signal generator 512 is coupled to the testing machine 520 to receive the clock signal CLK. The test receiver 517 is coupled to the test machine 520 to receive the test selection signal SEL. The output driver 516 is coupled to the testing machine 520 and used for outputting the test output signal DOUT to complete the test.

在本實施例中的測試電路510,與圖1的測試電路不同處在於,命令解碼器511可解碼測試命令CMD以提供潛時控制信號LTctrl至觸發信號產生器512。觸發信號產生器512並可依據潛時控制信號LTctrl來設定一潛伏時間(Latency)。觸發信號產生器512可根據潛伏時間來調整產生觸發信號TG的時間點。The test circuit 510 in this embodiment is different from the test circuit in FIG. 1 in that the command decoder 511 can decode the test command CMD to provide the latent control signal LTctrl to the trigger signal generator 512 . The trigger signal generator 512 can also set a latency according to the latency control signal LTctrl. The trigger signal generator 512 can adjust the time point of generating the trigger signal TG according to the latency.

此外,在本實施例中的測試電路510,測試資料產生器515依據多個取樣時脈SCK1~SCKn取樣測試資料PD1~PDn,以產生串列資料SDA並提供至輸出驅動器516,且輸出驅動器516還接收來自觸發信號產生器512產生的觸發信號TG。輸出驅動器516依據觸發信號TG以及串列資料SDA以產生測試輸出信號DOUT。其中,測試輸出信號DOUT可包括前置(Preamble)信號部分以及一測試資料信號部分。前置信號部分可為輸出驅動器516依據觸發信號TG來對應產生,而測試資料信號部分為輸出驅動器516依據串列資料SDA所對應產生。In addition, in the test circuit 510 in this embodiment, the test data generator 515 samples the test data PD1-PDn according to a plurality of sampling clocks SCK1-SCKn to generate the serial data SDA and provide it to the output driver 516, and the output driver 516 The trigger signal TG generated from the trigger signal generator 512 is also received. The output driver 516 generates the test output signal DOUT according to the trigger signal TG and the serial data SDA. Wherein, the test output signal DOUT may include a preamble signal part and a test data signal part. The pre-signal part can be correspondingly generated by the output driver 516 according to the trigger signal TG, and the test data signal part can be correspondingly generated by the output driver 516 according to the serial data SDA.

在本實施例中的測試電路510還透過測試接收器517以接收來自測試機520的測試選擇信號SEL。在當測試電路510對應的積體電路為被測試元件(device under test, DUT)時,測試電路510可依據選擇信號SEL來產生致能訊號EN,並提供致能訊號EN給命令解碼器511,以致能命令解碼器511可執行測試命令CMD的解碼動作,並進以執行後續的測試動作。The testing circuit 510 in this embodiment also receives the testing selection signal SEL from the testing machine 520 through the testing receiver 517 . When the integrated circuit corresponding to the test circuit 510 is a device under test (DUT), the test circuit 510 can generate the enable signal EN according to the selection signal SEL, and provide the enable signal EN to the command decoder 511, So that the enable command decoder 511 can execute the decoding action of the test command CMD, and further execute subsequent test actions.

以下請參照圖5及圖6,圖6例示如同圖5測試系統的實施例中,輸入時脈信號以及測試輸出信號的波形圖。其中,在圖6中,測試輸出信號DOUT具有前置信號部分PB以及所述測試資料信號部分,例如圖6所示測試資料信號d1~d9 …。前置信號部分PB為依據觸發信號產生器512提供的觸發信號TG所產生,因此相對於時脈信號CLK的上升緣觸發時間點,具有潛伏時間LT_T的延遲。在本實施例中,時脈信號CLK的一個週期,可對應八筆的測試資料信號(例如測試資料信號d1~d8)。Please refer to FIG. 5 and FIG. 6 below. FIG. 6 illustrates waveform diagrams of the input clock signal and the test output signal in the embodiment of the test system as in FIG. 5 . Wherein, in FIG. 6 , the test output signal DOUT has a preamble signal part PB and the test data signal part, such as the test data signals d1~d9 . . . shown in FIG. 6 . The preamble signal part PB is generated according to the trigger signal TG provided by the trigger signal generator 512 , so relative to the rising edge trigger time point of the clock signal CLK, there is a delay of the latency LT_T. In this embodiment, one period of the clock signal CLK may correspond to eight test data signals (eg, test data signals d1 - d8 ).

值得一提的是觸發信號產生器512可依據時脈信號CLK的多個上升緣,來週期性的產生觸發信號TG。It is worth mentioning that the trigger signal generator 512 can periodically generate the trigger signal TG according to multiple rising edges of the clock signal CLK.

以下請同步參照圖5以及圖7,圖7為本發明實施例的測試系統的潛伏時間調校模式的測試動作的波形圖。本發明實施例的測試系統可依據多次的測試結果,來進行潛伏時間的設定動作。在圖7中,測試系統500的命令解碼器511可透過產生不同的潛時控制信號LTctrl來分別執行測試動作T1~T4。其中,測試動作T1~T4的潛伏時間可分別為不相同的第一至第四潛伏時間。對應不同的潛伏時間,輸出驅動器516在測試動作T1~T4可分別產生前置信號部分出現時間不同的測試輸出信號DOUT。於本實施例中,測試輸出信號DOUT前置信號部分可為邏輯0。測試機520則可依據所設定的取樣點S0來對測試輸出信號DOUT進行取樣。因此,在潛伏時間調校模式中,測試機520可依據上述的取樣結果來與邏輯0進行比較,就可以得知測試輸出信號的DOUT的前置信號部分出現時間是否正確。Please refer to FIG. 5 and FIG. 7 synchronously below. FIG. 7 is a waveform diagram of a test operation in the latency adjustment mode of the test system according to an embodiment of the present invention. The test system of the embodiment of the present invention can perform the setting action of the latency time according to the test results of multiple times. In FIG. 7 , the command decoder 511 of the test system 500 can respectively execute test actions T1 - T4 by generating different latency control signals LTctrl. Wherein, the latency times of the test actions T1-T4 may be different first to fourth latency times respectively. Corresponding to different latency times, the output driver 516 can respectively generate test output signals DOUT with different occurrence times of the pre-signal parts during the test actions T1 - T4 . In this embodiment, the pre-signal portion of the test output signal DOUT may be logic 0. The testing machine 520 can sample the test output signal DOUT according to the set sampling point S0. Therefore, in the latency adjustment mode, the tester 520 can compare the above sampling result with logic 0, and then know whether the occurrence time of the preamble part of the test output signal DOUT is correct.

在圖7中,在測試動作T1以及T4中,測試機520可判斷出測試輸出信號DOUT的前置信號出現時間是不正確的,而在測試動作T2以及T3中,測試機520可判斷出測試輸出信號DOUT的前置信號出現時間是正確的。據此,測試機520可進一步將測試動作T2及T3所對應的第二潛伏時間及第三單位潛伏時間兩者平均,以產生設定潛伏時間。In FIG. 7 , in the test actions T1 and T4, the testing machine 520 can determine that the time at which the leading signal of the test output signal DOUT appears is incorrect, and in the testing actions T2 and T3, the testing machine 520 can determine that the test output signal DOUT is incorrect. The leading signal occurrence time of the output signal DOUT is correct. Accordingly, the testing machine 520 can further average the second latency and the third unit latency corresponding to the testing actions T2 and T3 to generate a set latency.

以下請同步參照圖5以及圖8,圖8為本發明實施例的測試系統的單位延遲調校模式的測試動作的波形圖。本發明實施例的測試系統可依據多次的測試結果,來進行單位延遲的設定動作。在圖8中,測試系統500中的延遲控制信號產生器513可透過產生不同的延遲控制信號Dctrl來分別執行測試動作T1’~T4’。其中,測試動作T1’~T4’的單位延遲可分別為不相同的第一至第四單位延遲。對應不同的單位延遲,輸出驅動器516在測試動作T1’~T4’可分別產生不同相位的測試輸出信號DOUT。測試機520則可依據所設定的取樣點S1~S8來對測試輸出信號DOUT進行取樣。在單位延遲調校模式中,測試輸出信號DOUT是依據預先設定好的測試資料PD1~PDn來產生。因此,測試機520可依據上述的取樣結果來與測試資料PD1~PDn進行比較,就可以得知測試輸出信號DOUT是否正確。Please refer to FIG. 5 and FIG. 8 synchronously below. FIG. 8 is a waveform diagram of a test operation in the unit delay adjustment mode of the test system according to an embodiment of the present invention. The test system of the embodiment of the present invention can perform the setting action of the unit delay according to multiple test results. In FIG. 8, the delay control signal generator 513 in the test system 500 can respectively execute test actions T1'~T4' by generating different delay control signals Dctrl. Wherein, the unit delays of the test actions T1'~T4' may be different first to fourth unit delays respectively. Corresponding to different unit delays, the output driver 516 can respectively generate test output signals DOUT with different phases during the test operations T1'˜T4'. The testing machine 520 can sample the test output signal DOUT according to the set sampling points S1 - S8 . In the unit delay adjustment mode, the test output signal DOUT is generated according to the preset test data PD1˜PDn. Therefore, the testing machine 520 can compare the above sampling results with the test data PD1 ˜ PDn to know whether the test output signal DOUT is correct.

在圖8中,在測試動作T1’以及T4’中,測試機520可判斷出測試輸出信號DOUT是不正確的,而在測試動作T2’以及T3’中,測試機520可判斷出測試輸出信號DOUT是正確的。據此,測試機520可進一步將測試動作T2’及T3’所對應的第二單位延遲及第三單位延遲兩者平均,以產生設定單位延遲。In FIG. 8, in the test actions T1' and T4', the tester 520 can determine that the test output signal DOUT is incorrect, and in the test actions T2' and T3', the tester 520 can determine that the test output signal DOUT is incorrect. DOUT is correct. Accordingly, the testing machine 520 can further average the second unit delay and the third unit delay corresponding to the test actions T2' and T3' to generate a set unit delay.

在本發明實施例中,當潛伏時間以及單位延遲設定完成後,測試資料產生器510可變更以接收積體電路內部的資料,例如記憶體的讀出資料。測試機520則可依據所設定的取樣點,取樣測試輸出信號DOUT,以得到記憶體的讀出資料的輸出資料,來完成記憶體內部的測試。In the embodiment of the present invention, after the setting of the latency and the unit delay is completed, the test data generator 510 can be changed to receive data inside the integrated circuit, such as the read data of the memory. The testing machine 520 can sample and test the output signal DOUT according to the set sampling points to obtain the output data of the read data of the memory to complete the internal test of the memory.

綜上所述,本發明所揭露的測試系統以及其測試電路,可依據輸入至測試電路的時脈信號來產生相對高頻的取樣信號,並透過取樣信號來產生輸出測試信號,以完成記憶體內部的測試動作,進以縮短測試時間。如此一來,在不需要設置鎖相迴路(Phase Locked Loop,PLL)的前題下,本發明所揭示的測試系統以及其測試電路可執行相對高頻率的測試動作,在不使用高階測試機的條件下,有效提升測試速率,並降低測試成本。In summary, the test system and its test circuit disclosed in the present invention can generate a relatively high-frequency sampling signal according to the clock signal input to the test circuit, and generate an output test signal through the sampling signal to complete the memory Part of the test action to shorten the test time. In this way, under the premise that no phase-locked loop (Phase Locked Loop, PLL) is required, the test system and its test circuit disclosed in the present invention can perform relatively high-frequency test actions without using a high-end test machine. Under certain conditions, the test rate can be effectively increased and the test cost can be reduced.

100、200、300、510:測試電路 110、210、310、511:命令解碼器 120、220、320、512:觸發信號產生器 130、230、330、513:延遲控制信號產生器 140、240、340、514:延遲電路 150、250、350、515:測試資料產生器 341:延遲線 342:選擇電路 500:測試系統 516:輸出驅動器 517:測試接收器 520:測試機 BUF1~BUFn:緩衝器 C:電容 CLK:時脈信號 CMD:測試命令 d1~d9:測試資料信號 D1~Dn:延遲器 Dctrl:延遲控制信號 DOUT:測試輸出信號 EN:致能信號 INV1~INVn:反相器 LT_T:潛伏時間 LTctrl:潛時控制信號 PB:前置信號部分 PD1~PDn:測試資料 R:電阻 RCN:電阻電容網路 S0、S1~S8:取樣點 SCK1~SCKn:取樣時脈 SDA:串列資料 SEL:測試選擇信號 T1、T2、T3、T4、T1’、T2’、T3’、T4’:測試動作 TCODE:調整信號 TG:觸發信號 VCD1~VCDn:電壓控制延遲器100, 200, 300, 510: test circuit 110, 210, 310, 511: command decoder 120, 220, 320, 512: trigger signal generator 130, 230, 330, 513: delay control signal generator 140, 240, 340, 514: delay circuit 150, 250, 350, 515: test data generator 341: delay line 342: Select circuit 500: test system 516: output driver 517:Test Receiver 520: Test machine BUF1~BUFn: buffer C: Capacitance CLK: clock signal CMD: test command d1~d9: test data signal D1~Dn: delayer Dctrl: delay control signal DOUT: Test output signal EN: enable signal INV1~INVn: Inverter LT_T: Latency time LTctrl: Latency control signal PB: front signal part PD1~PDn: test data R: resistance RCN: Resistor Capacitor Network S0, S1~S8: Sampling points SCK1~SCKn: sampling clock SDA: Serial Data SEL: test selection signal T1, T2, T3, T4, T1', T2', T3', T4': test action TCODE: adjust the signal TG: trigger signal VCD1~VCDn: voltage controlled delay

圖1繪示本發明一實施例的測試電路的示意圖。 圖2繪示本發明另一實施例的測試電路的示意圖。 圖3繪示本發明另一實施例的測試電路的示意圖。 圖4A至圖4D繪示本發明圖3實施例中的延遲線的實施方式示意圖。 圖5繪示本發明一實施例的示意圖。 圖6繪示本發明圖5測試系統實施例的輸入時脈信號以及測試輸出信號的波形圖。 圖7繪示本發明測試系統的潛伏時間調校模式的測試動作的波形圖。 圖8繪示本發明測試系統的單位延遲調校模式的測試動作的波形圖。 FIG. 1 is a schematic diagram of a test circuit according to an embodiment of the present invention. FIG. 2 is a schematic diagram of a test circuit according to another embodiment of the present invention. FIG. 3 is a schematic diagram of a test circuit according to another embodiment of the present invention. FIG. 4A to FIG. 4D are schematic diagrams illustrating the implementation of the delay line in the embodiment of FIG. 3 of the present invention. FIG. 5 is a schematic diagram of an embodiment of the present invention. FIG. 6 is a waveform diagram of an input clock signal and a test output signal of the embodiment of the test system shown in FIG. 5 of the present invention. FIG. 7 is a waveform diagram of a test action in the latency adjustment mode of the test system of the present invention. FIG. 8 is a waveform diagram of a test operation in the unit delay adjustment mode of the test system of the present invention.

100:測試電路 100: Test circuit

110:命令解碼器 110: command decoder

120:觸發信號產生器 120: Trigger signal generator

130:延遲控制信號產生器 130: delay control signal generator

140:延遲電路 140: delay circuit

150:測試資料產生器 150: Test data generator

CMD:測試命令 CMD: test command

CLK:時脈信號 CLK: clock signal

DOUT:測試輸出信號 DOUT: Test output signal

TCODE:調整信號 TCODE: adjust the signal

Dctrl:延遲控制信號 Dctrl: delay control signal

TG:觸發信號 TG: trigger signal

SCK1~SCKn:取樣時脈 SCK1~SCKn: sampling clock

PD1~PDn:測試資料 PD1~PDn: test data

Claims (18)

一種測試電路,接收一測試命令以及一輸入時脈信號以產生一測試輸出信號,包括: 一命令解碼器,根據解碼該測試命令以產生一調整信號; 一觸發信號產生器,根據該輸入時脈信號以產生一觸發信號; 一延遲控制信號產生器,耦接於該命令解碼器,根據該調整信號以產生一延遲控制信號; 一延遲電路,耦接於該延遲控制信號產生器以及該觸發信號產生器,以依據該延遲控制信號以產生一單位延遲,基於該單位延遲對該觸發信號進行延遲以產生多個取樣時脈;以及 一測試資料產生器,依據該些取樣時脈取樣複數個測試資料,以轉換為一串列資料。 A test circuit receives a test command and an input clock signal to generate a test output signal, including: a command decoder for generating an adjustment signal according to decoding the test command; a trigger signal generator, which generates a trigger signal according to the input clock signal; a delay control signal generator, coupled to the command decoder, to generate a delay control signal according to the adjustment signal; a delay circuit, coupled to the delay control signal generator and the trigger signal generator, to generate a unit delay according to the delay control signal, and delay the trigger signal based on the unit delay to generate a plurality of sampling clocks; as well as A test data generator samples a plurality of test data according to the sampling clocks and converts them into a series of data. 如請求項1所述的測試電路,其中該延遲電路包括多個電壓控制延遲器,該些電壓控制延遲器依序串接,其中各該電壓控制延遲器依據該延遲控制信號以提供該單位延遲,該些電壓控制延遲器依序對該觸發信號延遲以分別產生該些取樣時脈。The test circuit as claimed in claim 1, wherein the delay circuit includes a plurality of voltage-controlled delayers, and the voltage-controlled delayers are connected in series, wherein each voltage-controlled delayer provides the unit delay according to the delay control signal , the voltage-controlled delays sequentially delay the trigger signal to respectively generate the sampling clocks. 如請求項1所述的測試電路,其中該延遲電路包括: 多個延遲器,其中該些延遲器依序串接;以及 一選擇電路, 其中該些延遲器依序對該觸發信號延遲以產生多個延遲信號,該選擇電路根據該延遲控制信號選擇部分的該些延遲信號以產生該些取樣時脈。 The test circuit as claimed in item 1, wherein the delay circuit comprises: a plurality of delayers, wherein the delayers are connected in series; and One selects the circuit, The delayers delay the trigger signal in sequence to generate a plurality of delayed signals, and the selection circuit selects part of the delayed signals according to the delay control signal to generate the sampling clocks. 如請求項3所述的測試電路,其中各該延遲器為一緩衝器。The test circuit as claimed in claim 3, wherein each of the delays is a buffer. 如請求項4所述的測試電路,其中各該緩衝器更包含一電阻電容網路,該電阻電容網路耦接在該緩衝器的輸入端或輸出端。The test circuit as claimed in claim 4, wherein each of the buffers further includes a resistor-capacitor network, and the resistor-capacitor network is coupled to the input terminal or the output terminal of the buffer. 如請求項3所述的測試電路,其中各該延遲器為一反相器。The test circuit as claimed in claim 3, wherein each of the delayers is an inverter. 如請求項6所述的測試電路,其中各該反相器更包含一電阻電容網路,該電阻電容網路耦接在該反相器的輸入端或輸出端。The test circuit as claimed in claim 6, wherein each of the inverters further includes a resistor-capacitor network, and the resistor-capacitor network is coupled to the input terminal or the output terminal of the inverter. 如請求項1所述的測試電路,其中該命令解碼器更耦接該觸發信號產生器,該命令解碼器根據該測試命令產生一潛時控制信號,該觸發信號產生器根據該潛時控制信號,使該觸發信號的起始時間點延後一潛伏時間。The test circuit as described in claim 1, wherein the command decoder is further coupled to the trigger signal generator, the command decoder generates a latency control signal according to the test command, and the trigger signal generator generates a latency control signal according to the latency control signal , to delay the start time point of the trigger signal by a latency time. 如請求項8所述的測試電路,還包括: 一輸出驅動器,耦接該測試資料產生器,以依據該串列資料輸出該測試輸出信號。 The test circuit as described in claim 8, further comprising: An output driver, coupled to the test data generator, outputs the test output signal according to the serial data. 如請求項9所述的測試電路,其中該輸出驅動器還耦接該觸發信號產生器,以依據該觸發信號以及該串列資料輸出該測試輸出信號。The test circuit as claimed in claim 9, wherein the output driver is further coupled to the trigger signal generator to output the test output signal according to the trigger signal and the serial data. 如請求項1所述的測試電路,其中該測試資料產生器更依據該串列資料產生該測試輸出信號。The test circuit as claimed in claim 1, wherein the test data generator further generates the test output signal according to the serial data. 一種測試系統,包括: 一測試機;以及 如請求項1所述的測試電路,該測試機耦接該測試電路,其中該測試機用以: 提供該測試命令以及該輸入時脈信號至該測試電路,以及 接收該測試輸出信號,並根據該測試輸出信號以產生一測試結果。 A test system comprising: a testing machine; and The testing circuit as described in claim 1, the testing machine is coupled to the testing circuit, wherein the testing machine is used for: providing the test command and the input clock signal to the test circuit, and The test output signal is received, and a test result is generated according to the test output signal. 如請求項12所述的測試系統,其中該測試機透過該測試命令以調整該單位延遲,並根據對應的該測試結果以產生一設定單位延遲。The testing system according to claim 12, wherein the testing machine adjusts the unit delay through the test command, and generates a set unit delay according to the corresponding test result. 如請求項13所述的測試系統,其中該測試機透過一第一測試命令以產生一第一單位延遲,透過一第二測試命令以產生一第二單位延遲,當對應該第一測試命令以及該第二測試命令的一第一測試結果以及一第二測試結果均為通過時,該測試機計算該第一單位延遲以及該第二單位延遲的平均值來產生該設定單位延遲,其中該第一單位延遲與該第二單位延遲不相同。The test system as described in claim 13, wherein the testing machine generates a first unit delay through a first test command, and generates a second unit delay through a second test command, when corresponding to the first test command and When a first test result and a second test result of the second test command are both passed, the tester calculates the average value of the first unit delay and the second unit delay to generate the set unit delay, wherein the first unit delay A unit of delay is different from the second unit of delay. 如請求項12所述的測試系統,其中該命令解碼器更耦接該觸發信號產生器,該命令解碼器根據該測試命令產生一潛時控制信號,該觸發信號產生器根據該潛時控制信號,使該觸發信號的起始時間點延後一潛伏時間。The test system as described in claim 12, wherein the command decoder is further coupled to the trigger signal generator, the command decoder generates a latency control signal according to the test command, and the trigger signal generator generates a latency control signal according to the latency control signal , to delay the start time point of the trigger signal by a latency time. 如請求項15所述的測試系統,其中該測試機透過該測試命令以調整該潛伏時間,並根據對應的該測試結果以產生一設定潛伏時間。The test system as claimed in claim 15, wherein the testing machine adjusts the latency time through the test command, and generates a set latency time according to the corresponding test result. 如請求項16所述的測試系統,其中該測試機透過一第一測試命令以產生一第一潛伏時間,透過一第二測試命令以產生一第二潛伏時間,當對應該第一測試命令以及該第二測試命令的一第一測試結果以及一第二測試結果均為通過時,該測試機計算該第一潛伏時間以及該第二潛伏時間的平均值來產生該設定潛伏時間,其中該第一潛伏時間與該第二潛伏時間不相同。The test system as described in claim 16, wherein the testing machine generates a first latency through a first test command, and generates a second latency through a second test command, when corresponding to the first test command and When a first test result and a second test result of the second test command are both passed, the testing machine calculates the average value of the first latency and the second latency to generate the set latency, wherein the first latency A latency is different from the second latency. 如請求項12所述的測試系統,其中該測試電路還包括一測試接受器,耦接於該命令解碼器,該測試接受器經配置以接收該測試機提供之一測試選擇信號,並根據該測試選擇信號致能該命令解碼器。The test system as described in claim 12, wherein the test circuit further includes a test receiver coupled to the command decoder, the test receiver is configured to receive a test selection signal provided by the test machine, and according to the The test select signal enables the command decoder.
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