CN116266471A

CN116266471A - Test system and test circuit thereof

Info

Publication number: CN116266471A
Application number: CN202210004695.5A
Authority: CN
Inventors: 石原政广
Original assignee: Powerchip Technology Corp
Current assignee: Powerchip Technology Corp
Priority date: 2021-12-17
Filing date: 2022-01-05
Publication date: 2023-06-20
Also published as: TWI781017B; TW202326744A

Abstract

The invention provides a test system and a test circuit thereof. The test circuit includes a command decoder, a trigger signal generator, a delay control signal generator, a delay circuit, and a test data generator. The command decoder generates an adjustment signal according to the decoded test command. The trigger signal generator generates a trigger signal according to the clock signal. The delay control signal generator generates a delay control signal according to the adjustment signal. The delay circuit generates a unit delay according to the delay control signal and delays the trigger signal based on the unit delay to generate a plurality of sampling clocks. The test data generator samples test data according to the sampling clock to obtain a test output signal.

Description

Test system and test circuit thereof

Technical Field

The present invention relates to a test system and a test circuit thereof, and more particularly, to a memory test system and a memory test circuit.

Background

The mainstream input/output architecture of the current dynamic random access memory (Dynamic Random Access Memory, DRAM) is a Double Data Rate (DDR) architecture. Since the DDR architecture transfers data once on both the rising and falling edges of the bus clock, its data transfer frequency is twice the bus clock frequency. Taking the fourth generation double data rate (DDR 4) specification as an example, in a typical usage scenario, the bus clock frequency can be up to about 1.6GHz, so that the data transmission frequency of DDR4 can be up to 3.2GHz.

However, in product testing applications of memory chips, particularly under wafer level testing conditions, it is difficult to provide memory up to the desired frequency (e.g., 1.6 GHz) under typical use conditions. High-speed testers at the wafer level can typically provide test frequencies up to only about 100MHz, much lower than what is required for DDR memory in typical usage. Further, since the high-speed testing machine is expensive, it is hardly achievable under the present conditions if the testing frequency is greatly increased. Therefore, the current testing of the wafer level memory is limited by the testing frequency of the tester, so that the clock frequency provided for the memory during testing is far lower than the clock frequency required by the memory under the general use condition, the testing time is greatly prolonged, and the manufacturing cost of the memory chip is further increased.

Disclosure of Invention

The invention provides a test circuit which can complete the test action inside a memory through a clock signal with lower frequency.

The test circuit of the invention comprises a command decoding circuit, a trigger signal generator, a delay control signal generator, a delay circuit and a test data generator. The command decoding circuit generates an adjustment signal according to the decoded test command. The trigger signal generator generates a trigger signal according to an input clock signal. The delay control signal generator is coupled to the command decoding circuit and generates a delay control signal according to the adjustment signal. The delay circuit is coupled to the delay control signal generator and the trigger signal generator to generate a unit delay according to the delay control signal, and delays the trigger signal based on the unit delay to generate a plurality of sampling clocks. The test data generator samples test data according to a plurality of sampling clocks to obtain a test output signal.

The test system comprises a tester and a test circuit. The testing machine is coupled with the testing circuit. The test circuit includes a command decoding circuit, a trigger signal generator, a delay control signal generator, a delay circuit, and a test data generator. The command decoding circuit generates an adjustment signal according to the decoded test command. The trigger signal generator generates a trigger signal according to an input clock signal. The delay control signal generator is coupled to the command decoding circuit and generates a delay control signal according to the adjustment signal. The delay circuit is coupled to the delay control signal generator and the trigger signal generator to generate a unit delay according to the delay control signal, and delays the trigger signal based on the unit delay to generate a plurality of sampling clocks. The test data generator samples test data according to a plurality of sampling clocks to obtain a test output signal. The tester is used for providing a test command and an input clock signal to the test circuit, receiving the test output signal and generating a test result according to the test output signal.

Based on the above, the test circuit and the test system of the invention can use the external clock signal with lower frequency to input the test circuit to obtain the test output signal with higher clock signal frequency so as to complete the test action in the memory. On the premise of not increasing the hardware cost of the tester, the test circuit can output an output signal with higher frequency than an external input clock signal so as to shorten the test time. In addition, the technical scheme of the invention does not need to use the technology of coupling the clock input end of the test circuit with the frequency multiplier besides increasing the hardware cost of the test machine, such as the technical scheme of using a phase-locked loop (Phase Locked Loop, PLL) and the like, so the cost and the complexity of the test system are not increased.

Drawings

FIG. 1 is a schematic diagram of a test circuit according to an embodiment of the invention.

FIG. 2 is a schematic diagram of a test circuit according to another embodiment of the invention.

FIG. 3 is a schematic diagram of a test circuit according to another embodiment of the invention.

Fig. 4A to 4D are schematic diagrams illustrating a delay line according to the embodiment of fig. 3.

FIG. 5 is a schematic diagram of an embodiment of the present invention.

FIG. 6 is a waveform diagram of an input clock signal and a test output signal of the embodiment of the test system of FIG. 5.

FIG. 7 is a waveform diagram showing the test operation of the latency adjustment mode of the test system according to the present invention.

FIG. 8 is a waveform diagram showing the unit delay calibration mode of the test system according to the present invention.

[ symbolic description ]

100. 200, 300, 510:

test circuits

110, 210, 310, 511:

command decoders

120, 220, 320, 512:

trigger signal generator

130, 230, 330, 513: delay

control signal generator

140, 240, 340, 514:

delay circuits

150, 250, 350, 515: test data generator 341: delay line

342: selection circuit

500: test system

516: output driver

517: test receiver

520: test machine

BUF1 to BUFn: buffer device

C: capacitance device

CLK: clock signal

CMD: test command

d1 to d9: test data signal

D1-Dn: delay device

Dctrl: delay control signal

DOUT: test output signal

EN: enable signal

INV1 to INVn: inverter with a high-speed circuit

Lt_t: latency time

LTctrl: control signal for diving

PB: preamble signal section

PD 1-PDn: test data

R: resistor

RCN: resistor-capacitor network

S0, S1-S8: sampling point

SCK1 to SCKn: sampling clock

SDA (serial digital access card): serial data

SEL: test selection signal

T1, T2, T3, T4, T1', T2', T3', T4': test action

TCODE: adjusting signals

TG: trigger signal

VCD1 to VCDn: voltage control delayer

Detailed Description

Referring to fig. 1, fig. 1 is a schematic diagram of a test circuit according to an embodiment of the invention. The test circuit 100 includes a command decoder 110, a trigger signal generator 120, a delay control signal generator 130, a delay circuit 140, and a test data generator 150. Wherein the delay control signal generator 130 is coupled to the command decoder 110 and the delay circuit 140, and the delay circuit 140 is further coupled to the touch signal generator 120 and the test data generator 150.

The command decoder 110 receives and decodes a test command CMD provided from an external, e.g., tester. The trigger signal generator 120 receives a clock signal CLK provided from an external device, such as a tester, and the clock signal CLK may be a periodic clock signal, and the trigger signal generator 120 generates a trigger signal TG according to the clock signal CLK. The trigger signal generator 120 may generate the trigger signal TG according to a transition edge of the clock signal CLK, wherein the transition edge may be a rising edge and/or a falling edge. The test data generator 150 is used for outputting a test output signal DOUT.

The command decoder 110 decodes the test command CMD and generates an adjustment signal TCODE. The command decoder 110 provides an adjustment signal TCODE to the delay control signal generator 130. The delay control signal generator 130 generates the delay control signal Dctrl according to the adjustment signal TCODE. The delay circuit 140 may set a unit delay according to the delay control signal Dctrl, and delay the trigger signal TG one to more times based on the set unit delay, so as to sequentially generate a plurality of sampling clocks SCK1 to SCKn. It should be noted that, since the trigger signal TG is generated according to the triggering of the waveform of the clock signal CLK, and the delay circuit 140 delays the trigger signal TG multiple times according to the unit delay to generate the sampling clocks SCK1 to SCKn; that is, sampling clocks SCK1 to SCKn are generated every cycle of the clock signal CLK. This means that the frequency of the sampling clocks SCK1 to SCKn will be higher than the frequency of the clock signal CLK, and the frequency of the sampling clocks SCK1 to SCKn can be determined by the time of the unit delay.

The test data generator 150 samples a plurality of test data PD 1-PDn according to the sampling clocks SCK 1-SCKn to generate a test output signal DOUT. The test data PD1 to PDn may be preset test data written in a register (not shown in fig. 1) of the test circuit 100 in advance, or test data (e.g., read data of a memory) generated by the integrated circuit according to a test action. The test data generator 150 may be a parallel-to-serial converter (parrel to serial converter) for converting the test data PD 1-PDn into serial data according to the sampling clocks SCK 1-SCKn, and generating the test output signal DOUT.

The test circuit 100 of the present embodiment may be embedded in a memory chip to be tested. According to the above embodiment, the test circuit 100 of the present embodiment can output the test output signal DOUT according to the input test command CMD and the clock signal CLK to complete the test operation in the memory. And the test circuit 100 is characterized in that the frequency of the test output signal DOUT is higher than the frequency of the clock signal CLK.

Referring to fig. 2, fig. 2 is a schematic diagram of a test circuit according to another embodiment of the invention. The test circuit 200 includes a command decoder 210, a trigger signal generator 220, a delay control signal generator 230, a delay circuit 240, and a test data generator 250. Wherein the delay control signal generator 230 is coupled to the command decoder 210 and the delay circuit 240, and the delay circuit 240 is further coupled to the touch signal generator 220 and the test data generator 250. The command decoder 210 is configured to receive a test command CMD, the trigger signal generator 220 is configured to receive a clock signal CLK, and the test data generator 250 is configured to generate an output test signal DOUT.

The test circuit 200 differs from the test circuit of the embodiment of fig. 1 in that the delay circuit 240 includes a plurality of voltage controlled delays VCD 1-VCDn connected in series. As shown in fig. 2, the input end of the VCD1 is coupled to the trigger signal generator 220, and the output end of the VCD1 is serially connected with VCD2 to VCDn. Wherein the voltage control delays VCD1 to VCDn are commonly coupled to the delay control signal generator 230, and the output terminals of the voltage control delays VCD1 to VCDn are respectively coupled to the test data generator 250.

The delay control signal generator 230 generates the delay control signal Dctrl according to the adjustment signal TCODE generated by decoding the test command CMD from the command decoder 210. The delay control signal Dctrl may have a voltage value, and each of the voltage control delays VCD1 to VCDn may generate a unit delay according to the voltage value of the delay control signal Dctrl, and sequentially delay the trigger signal TG to generate a plurality of sampling clocks SCK1 to SCKn. In the present embodiment, the time length of the unit delay is determined by the voltage value of the delay control signal Dctrl. The time length of the unit delay may be positively or negatively related to the voltage value of the delay control signal Dctrl, without any limitation.

Referring to fig. 3, fig. 3 is a schematic diagram of a test circuit according to another embodiment of the invention. The test circuit 300 includes a command decoder 310, a trigger signal generator 320, a delay control signal generator 330, a delay circuit 340, and a test data generator 350. Wherein the delay control signal generator 330 is coupled to the command decoder 310 and the delay circuit 340, the delay circuit 340 is further coupled to the touch signal generator 320 and the test data generator 350. The command decoder 310 is configured to receive a test command CMD, the trigger signal generator 320 is configured to receive a clock signal CLK, and the test data generator 350 is configured to generate an output test signal DOUT.

The test circuit 300 is different from the test circuit of the embodiment of fig. 1 in that the delay circuit 340 includes a delay line 341 and a selection circuit 342, wherein the delay line 341 may include a plurality of delays D1-Dn connected in series. As shown in fig. 3, the input end of the delay D1 is coupled to the trigger signal generator 320, and the output end of the delay D1 is serially connected with the delays D2-Dn in sequence. And wherein the output terminals of the delays D1-Dn are respectively coupled to the selection circuit 342. The selection circuit 342 is coupled to the delay control signal generator 330 and the test data generator 350, and the selection circuit 342 selectively provides the plurality of output signals of the output terminals of the delays D1-Dn to the test data generator 350.

Each of the delays D1 to Dn may generate a unit resolution delay, and sequentially delay the trigger signal TG and output to the selection circuit 342. The delay control signal generator 330 generates a delay control signal Dctrl according to the adjustment signal TCODE, and the selection circuit 342 selects the output of a portion of the delays D1-Dn according to the delay control signal Dctrl to generate a plurality of sampling clocks SCK 1-SCKn, wherein two sampling clocks with similar phases have a unit delay. For example, if the set unit delay length is 3 times the unit resolution delay length, the delay control signal generator 330 provides the delay control signal Dctrl to the selection circuit 342, and the selection circuit 342 provides the delay signals generated by the selection delays D3, D6, D9 … to the test data generator 350 to generate the plurality of sampling clocks SCK1 to SCKn.

Referring to fig. 4A-4D, fig. 4A-4D illustrate various implementations of the delay line 341 of the embodiment of fig. 3. In fig. 4A, the delay line 341 includes a plurality of buffers BUF1 to BUFn connected in series in sequence. In fig. 4B, the delay line 341 further includes a plurality of rc networks, each of which is coupled to the input or output of the corresponding buffer BUF 1-BUFn, respectively, and is used to increase the length of the unit resolution delay. In fig. 4B, a resistor-capacitor network RCN is taken as an example, and the resistor-capacitor network RCN is coupled to the output terminal of the buffer BUF 1. One end of the resistor R is coupled to the output end of the buffer BUF1, the other end of the resistor R is coupled to one end of the capacitor C, and the other end of the capacitor C is coupled to the reference ground.

In fig. 4C, the delay line 341 includes a plurality of inverters INV1 to INVn connected in series with each other. While in fig. 4D, the delay line 341 further includes a plurality of resistor-capacitor networks. The RC network may be coupled to an input or an output of each of the inverters INV 1-INVn, and is used to increase the length of the unit resolution delay.

Fig. 5 is a schematic diagram of a test system according to an embodiment of the invention. Test system 500 includes test circuitry 510 and test machine 520. The tester 520 is connected to the test circuit 510 to perform the test. The tester 520 is configured to provide a test command CMD and a clock signal CLK to the test circuit 510, and receive a test output signal DOUT from the test circuit 510. In this embodiment, the tester 520 may also provide a test selection signal SEL to the test circuit 510 to enable the test circuit 510 to perform a test.

As shown in fig. 5, the test circuit 510 includes a command decoder 511, a trigger signal generator 512, a delay control signal generator 513, a delay circuit 514, a test data generator 515, an output driver 516, and a test receiver 517. The command decoder 511 is coupled to the trigger signal generator 512, the delay control signal generator 513, and the test receiver 517. The trigger signal generator 512 is also coupled to the delay circuit 514 and the output driver 516. The delay control signal generator 513 is also coupled to a delay circuit 514. Delay circuit 514 is also coupled to test data generator 515. The test data generator 515 is also coupled to the output driver 516. Wherein the command decoder 511 is coupled to the tester 520 to receive the test command CMD. The trigger signal generator 512 is coupled to the tester 520 for receiving the clock signal CLK. The test receiver 517 is coupled to the tester 520 for receiving the test selection signal SEL. The output driver 516 is coupled to the tester 520 and is used for outputting a test output signal DOUT to complete the test.

The test circuit 510 in this embodiment is different from the test circuit of fig. 1 in that the command decoder 511 can decode the test command CMD to provide the latent control signal LTctrl to the trigger signal generator 512. The trigger signal generator 512 may also set a Latency (Latency) according to the Latency control signal LTctrl. The trigger signal generator 512 may adjust the point of time of generating the trigger signal TG according to the latency.

In addition, in the test circuit 510 of the present embodiment, the test data generator 515 samples the test data PD1 to PDn according to the plurality of sampling clocks SCK1 to SCKn to generate serial data SDA and provide the serial data SDA to the output driver 516, and the output driver 516 also receives the trigger signal TG generated from the trigger signal generator 512. The output driver 516 generates the test output signal DOUT according to the trigger signal TG and the serial data SDA. The test output signal DOUT may include a Preamble (Preamble) signal portion and a test data signal portion. The preamble signal portion may be correspondingly generated by the output driver 516 according to the trigger signal TG, and the test data signal portion may be correspondingly generated by the output driver 516 according to the serial data SDA.

The test circuit 510 in the present embodiment also receives a test selection signal SEL from the tester 520 through the test receiver 517. When the integrated circuit corresponding to the test circuit 510 is a device under test (device under test, DUT), the test circuit 510 can generate the enable signal EN according to the selection signal SEL and provide the enable signal EN to the command decoder 511, so that the command decoder 511 can perform the decoding operation of the test command CMD and further perform the subsequent testing operation.

Referring now to fig. 5 and 6, fig. 6 illustrates waveforms of an input clock signal and a test output signal in an embodiment of the test system of fig. 5. In fig. 6, the test output signal DOUT has a preamble signal portion PB and the test data signal portions, for example, the test data signals d1 to d9 … shown in fig. 6. The preamble portion PB is generated based on the trigger signal TG supplied from the trigger signal generator 512, and thus has a delay of the latency lt_t with respect to the rising edge trigger time point of the clock signal CLK. In the present embodiment, one period of the clock signal CLK may correspond to eight test data signals (e.g., the test data signals d1 to d 8).

It should be noted that the trigger signal generator 512 can periodically generate the trigger signal TG according to a plurality of rising edges of the clock signal CLK.

Referring to fig. 5 and fig. 7 in synchronization, fig. 7 is a waveform diagram of a test operation of a latency adjustment mode of the test system according to an embodiment of the invention. The test system of the embodiment of the invention can set the latency time according to the test results of a plurality of times. In fig. 7, the command decoder 511 of the test system 500 may perform test actions T1-T4, respectively, by generating different latency control signals LTctrl. The latency of the test actions T1 to T4 may be different first to fourth latencies, respectively. The output driver 516 may generate test output signals DOUT with different occurrence times of the preamble signal portions during the test actions T1-T4, respectively, corresponding to different latency times. In this embodiment, the test output signal DOUT preamble signal portion may be logic 0. The tester 520 can sample the test output signal DOUT according to the set sampling point S0. Thus, in the latency adjustment mode, the tester 520 can compare with logic 0 according to the sampling result, so as to determine whether the pre-signal portion of the DOUT of the test output signal appears correctly.

In fig. 7, in test actions T1 and T4, the tester 520 may determine that the pre-signal occurrence time of the test output signal DOUT is incorrect, and in test actions T2 and T3, the tester 520 may determine that the pre-signal occurrence time of the test output signal DOUT is correct. Accordingly, the tester 520 may further average both the second latency and the third unit latency corresponding to the test actions T2 and T3 to generate the set latency.

Referring to fig. 5 and fig. 8 in synchronization, fig. 8 is a waveform diagram of a test operation of a unit delay calibration mode of the test system according to an embodiment of the invention. The test system of the embodiment of the invention can perform the setting action of unit delay according to the test results of a plurality of times. In fig. 8, the delay control signal generator 513 in the test system 500 can respectively execute the test actions T1 'to T4' by generating different delay control signals Dctrl. The unit delays of the test actions T1 'to T4' may be different first to fourth unit delays, respectively. The output driver 516 generates the test output signals DOUT with different phases in the test operations T1 'to T4', respectively, corresponding to different unit delays. The tester 520 can sample the test output signal DOUT according to the set sampling points S1 to S8. In the unit delay calibration mode, the test output signal DOUT is generated based on predetermined test data PD 1-PDn. Therefore, the tester 520 can compare the test data PD1 to PDn according to the above-mentioned sampling result, so as to determine whether the test output signal DOUT is correct.

In fig. 8, in test actions T1 'and T4', the tester 520 may determine that the test output signal DOUT is incorrect, and in test actions T2 'and T3', the tester 520 may determine that the test output signal DOUT is correct. Accordingly, the tester 520 may further average both the second unit delay and the third unit delay corresponding to the test actions T2 'and T3', so as to generate the set unit delay.

In the embodiment of the present invention, after the latency and unit delay are set, the test data generator 510 may be changed to receive data inside the integrated circuit, such as read data of the memory. The tester 520 can sample the test output signal DOUT according to the set sampling point to obtain the output data of the read data of the memory, so as to complete the test inside the memory.

In summary, the test system and the test circuit thereof disclosed in the present invention can generate a relatively high frequency sampling signal according to a clock signal input to the test circuit, and generate an output test signal according to the sampling signal, so as to complete the test operation in the memory, thereby shortening the test time. Therefore, under the premise that a phase-locked loop (Phase Locked Loop, PLL) is not required, the test system and the test circuit thereof disclosed by the invention can execute relatively high-frequency test action, effectively improve the test speed and reduce the test cost under the condition that a high-order tester is not used.

Claims

1. A test circuit that receives a test command and an input clock signal to generate a test output signal, comprising:

a command decoder for generating an adjustment signal according to the decoded test command;

a trigger signal generator for generating a trigger signal according to the input clock signal;

a delay control signal generator coupled to the command decoder for generating a delay control signal according to the adjustment signal;

the delay circuit is coupled with the delay control signal generator and the trigger signal generator to generate unit delay according to the delay control signal, and delays the trigger signal based on the unit delay to generate a plurality of sampling clocks; and

the test data generator samples a plurality of test data according to the sampling clocks to convert the test data into serial data.

2. The test circuit of claim 1, wherein the delay circuit comprises a plurality of voltage controlled delays serially connected in sequence, wherein each voltage controlled delay provides the unit delay according to the delay control signal, and the voltage controlled delays sequentially delay the trigger signal to generate the sampling clocks respectively.

3. The test circuit of claim 1, wherein the delay circuit comprises:

a plurality of retarders, wherein the retarders are serially connected in sequence; and

the selection circuit is used to select the selection signal,

the delay devices delay the trigger signal in sequence to generate a plurality of delay signals, and the selection circuit selects part of the delay signals according to the delay control signal to generate the sampling clocks.

4. A test circuit as claimed in claim 3, wherein each of the delays is a buffer.

5. The test circuit of claim 4, wherein each of the buffers further comprises a resistor-capacitor network coupled to an input or an output of the buffer.

6. A test circuit as claimed in claim 3, wherein each of the delays is an inverter.

7. The test circuit of claim 6, wherein each of the inverters further comprises a resistor-capacitor network coupled to an input or an output of the inverter.

8. The test circuit of claim 1, wherein the command decoder is further coupled to the trigger signal generator, the command decoder generates a latency control signal according to the test command, the trigger signal generator delays a start time point of the trigger signal by a latency time according to the latency control signal.

9. The test circuit of claim 8, further comprising:

the output driver is coupled to the test data generator for outputting the test output signal according to the serial data.

10. The test circuit of claim 9, wherein the output driver is further coupled to the trigger signal generator to output the test output signal according to the trigger signal and the serial data.

11. The test circuit of claim 1, wherein the test data generator further generates the test output signal according to the serial data.

12. A test system, comprising:

a testing machine; and

the test circuit of claim 1, the tester coupled to the test circuit, wherein the tester is configured to:

providing the test command and the input clock signal to the test circuit, an

The test output signal is received, and a test result is generated according to the test output signal.

13. The test system of claim 12, wherein the tester adjusts the unit delay according to the test command and generates a set unit delay according to the corresponding test result.

14. The test system of claim 13, wherein the tester generates a first unit delay by a first test command and generates a second unit delay by a second test command, and calculates an average of the first unit delay and the second unit delay to generate the set unit delay when both the first test result and the second test result corresponding to the first test command and the second test command are passed, wherein the first unit delay is different from the second unit delay.

15. The test system of claim 12, wherein the command decoder is further coupled to the trigger signal generator, the command decoder generating a latency control signal according to the test command, the trigger signal generator delaying a start time point of the trigger signal by a latency time according to the latency control signal.

16. The test system of claim 15, wherein the tester adjusts the latency by the test command and generates a set latency according to the corresponding test result.

17. The test system of claim 16, wherein the tester generates a first latency by a first test command and generates a second latency by a second test command, and calculates an average of the first latency and the second latency to generate the set latency when both the first test result and the second test result corresponding to the first test command and the second test command are passed, wherein the first latency is different from the second latency.

18. The test system of claim 12, wherein the test circuit further comprises a test receiver coupled to the command decoder, the test receiver configured to receive a test selection signal provided by the tester and enable the command decoder according to the test selection signal.