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TWI820783B - Frequency detection device for clock signal and detection method thereof - Google Patents

Frequency detection device for clock signal and detection method thereof Download PDF

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TWI820783B
TWI820783B TW111124985A TW111124985A TWI820783B TW I820783 B TWI820783 B TW I820783B TW 111124985 A TW111124985 A TW 111124985A TW 111124985 A TW111124985 A TW 111124985A TW I820783 B TWI820783 B TW I820783B
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signal
frequency
sampling
detection device
command signal
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TW111124985A
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TW202404261A (en
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劉興羽
賴俊宇
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華邦電子股份有限公司
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Abstract

A frequency detection device for a clock signal and a detection method thereof are provided. The frequency detection device includes a pulse signal generator, a sample signal generator, a delay circuit and a sampling circuit. The pulse signal generator detects a plurality of transition edges of the clock signal to generate the pulse signal. The sample signal generator generates, based on a command signal, a sample signal according to pluses of the pulse signal. The delay circuit delays the command signal to generate a delayed command signal. The sampling circuit samples the delayed command signal by the sample signal to generate a detection result.

Description

時脈信號的頻率偵測裝置及其偵測方法Frequency detection device for clock signal and detection method thereof

本發明是有關於一種時脈信號的頻率偵測裝置及其偵測方法,且特別是有關於一種不需要參考時脈信號的時脈信號的頻率偵測裝置及其偵測方法發明名稱。The present invention relates to a frequency detection device for a clock signal and a detection method thereof, and in particular, to a frequency detection device for a clock signal that does not require a reference clock signal and a detection method thereof.

在記憶體電路中,使用者可針對記憶體電路進行不同頻率的讀取動作。而在高頻的讀取動作中,記憶體電路須提高感測放大器以及電荷泵電路的操作電流,來因應高速的讀取動作。然而,在低頻的讀取動作中,若維持感測放大器以及電荷泵電路的高操作電流,則會產生電流上的浪費。In the memory circuit, the user can perform read operations at different frequencies on the memory circuit. In high-frequency read operations, the memory circuit must increase the operating current of the sense amplifier and charge pump circuit to cope with the high-speed read operations. However, in low-frequency reading operations, if the operating current of the sense amplifier and charge pump circuit is maintained high, a waste of current will occur.

本發明提供一種時脈信號的頻率偵測裝置及其偵測方法,可不需要額外的參考時脈信號,有效的偵測出時脈信號的頻率。The present invention provides a clock signal frequency detection device and a detection method thereof, which can effectively detect the frequency of the clock signal without requiring an additional reference clock signal.

本發明的時脈信號的頻率偵測裝置包括脈波信號產生器、取樣信號產生器、延遲器以及取樣電路。脈波信號產生器偵測時脈信號的多個轉態緣,並根據時脈信號的轉態緣來產生脈波信號。取樣信號產生器基於命令信號,根據脈波信號上的脈衝中的多個來產生取樣信號。延遲器延遲命令信號以產生延遲命令信號。取樣電路根據取樣信號來取樣延遲命令信號以產生偵測結果。The frequency detection device of the clock signal of the present invention includes a pulse signal generator, a sampling signal generator, a delayer and a sampling circuit. The pulse signal generator detects multiple transition edges of the clock signal and generates a pulse signal according to the transition edges of the clock signal. The sampling signal generator generates a sampling signal based on a plurality of pulses on the pulse wave signal based on the command signal. The delayer delays the command signal to produce a delayed command signal. The sampling circuit samples the delayed command signal according to the sampling signal to generate a detection result.

本發明的時脈信號的頻率偵測方法包括:偵測時脈信號的多個轉態緣,並根據時脈信號的轉態緣來產生脈波信號;基於命令信號,根據脈波信號上的脈衝中的多個來產生取樣信號;延遲命令信號以產生延遲命令信號;以及,根據取樣信號來取樣延遲命令信號以產生偵測結果。The frequency detection method of the clock signal of the present invention includes: detecting multiple transition edges of the clock signal, and generating a pulse wave signal based on the transition edges of the clock signal; based on the command signal, based on the pulse signal A plurality of pulses are used to generate a sampling signal; a command signal is delayed to generate a delayed command signal; and the delayed command signal is sampled according to the sampling signal to generate a detection result.

基於上述,本發明透過延遲器來延遲命令信號,透過取樣信號產生器以根據基於時脈信號的轉態緣所產生的脈波信號來產生取樣信號,並透過取樣信號來針對延遲命令信號進行取樣,可以有效獲知時脈信號的頻率是否過慢。本發明的頻率偵測裝置不需要額外接收參考時脈信號,可降低因參考時脈信號的轉態緣所產生的功率消耗,並可降低所需的電路面積。並且,對應時脈信號的頻率偵測結果,後續的電路(例如記憶體電路)可對應調整例如電荷泵電路的工作時脈,以及位址解碼器的工作偏壓,可有效減低電路整體的功率消耗。Based on the above, the present invention uses a delayer to delay the command signal, uses a sampling signal generator to generate a sampling signal according to the pulse signal generated based on the transition edge of the clock signal, and uses the sampling signal to sample the delayed command signal. , can effectively know whether the frequency of the clock signal is too slow. The frequency detection device of the present invention does not need to receive an additional reference clock signal, can reduce power consumption caused by the transition edge of the reference clock signal, and can reduce the required circuit area. Moreover, according to the frequency detection result of the clock signal, subsequent circuits (such as memory circuits) can correspondingly adjust the operating clock of the charge pump circuit and the operating bias of the address decoder, which can effectively reduce the overall power of the circuit. consumption.

請參照圖1,頻率偵測裝置100包括脈波信號產生器110、取樣信號產生器120、延遲器130以及取樣電路140。脈波信號產生器110接收時脈信號CLK。脈波信號產生器110用以偵測時脈信號CLK的多個轉態緣,並根據時脈信號CLK的轉態緣來產生脈波信號CKIN。其中,時脈信號CLK可以是使用者由外部進行輸入,並作為針對頻率偵測裝置100後的核心電路(例如記憶體電路)進行存取動作的工作時脈。Referring to FIG. 1 , the frequency detection device 100 includes a pulse signal generator 110 , a sampling signal generator 120 , a delay 130 and a sampling circuit 140 . The pulse signal generator 110 receives the clock signal CLK. The pulse signal generator 110 is used to detect multiple transition edges of the clock signal CLK and generate the pulse signal CKIN according to the transition edges of the clock signal CLK. The clock signal CLK may be externally input by the user and used as a working clock for accessing core circuits (such as memory circuits) behind the frequency detection device 100 .

在本實施例中,脈波信號產生器110可針對時脈信號CLK的多個上升緣,或者偵測時脈信號CLK的多個下降緣。並對應時脈信號CLK的上升緣(或下降緣),來在脈波信號CKIN中產生多個脈衝。具體說明,脈波信號產生器110可以是一個單擊電路(one shot circuit),並針對時脈信號CLK以及時脈信號CLK的反向信號來進行邏輯運算,可產生脈波信號CKIN。In this embodiment, the pulse signal generator 110 can detect multiple rising edges of the clock signal CLK or detect multiple falling edges of the clock signal CLK. And corresponding to the rising edge (or falling edge) of the clock signal CLK, multiple pulses are generated in the pulse signal CKIN. Specifically, the pulse signal generator 110 may be a one shot circuit, and performs logical operations on the clock signal CLK and the inverse signal of the clock signal CLK to generate the pulse signal CKIN.

細節上,當脈波信號產生器110針對時脈信號CLK以及時脈信號CLK的反向信號來進行及(AND)邏輯運算時,脈波信號產生器110可對應時脈信號CLK的多個上升緣,來在脈波信號CKIN上產生多個脈衝。另外,當脈波信號產生器110針對時脈信號CLK以及時脈信號CLK的反向信號來進行反或(NOR)邏輯運算時,脈波信號產生器110可對應時脈信號CLK的多個下降緣,來在脈波信號CKIN上產生多個脈衝。In detail, when the pulse signal generator 110 performs an AND logic operation on the clock signal CLK and the inverse signal of the clock signal CLK, the pulse signal generator 110 can correspond to multiple rising edges of the clock signal CLK. edge to generate multiple pulses on the pulse signal CKIN. In addition, when the pulse signal generator 110 performs an inverse OR (NOR) logic operation on the clock signal CLK and the inverse signal of the clock signal CLK, the pulse signal generator 110 can correspond to multiple drops of the clock signal CLK. edge to generate multiple pulses on the pulse signal CKIN.

在另一方面,取樣信號產生器120耦接至脈波信號產生器110。取樣信號產生器120可接收命令信號READS以及脈波信號產生器110所產生的脈波信號CKIN。在執行頻率偵測動作中的一設定時間區間中,命令信號READS可被設定為一第一邏輯值,取樣信號產生器120則可基於命令信號READS,根據脈波信號CKIN上的脈衝中的多個來產生取樣信號SS。On the other hand, the sampling signal generator 120 is coupled to the pulse signal generator 110 . The sampling signal generator 120 can receive the command signal READS and the pulse signal CKIN generated by the pulse signal generator 110 . During a set time interval during the execution of the frequency detection operation, the command signal READS may be set to a first logic value, and the sampling signal generator 120 may, based on the command signal READS, determine the number of pulses in the pulse signal CKIN based on the command signal READS. to generate the sampling signal SS.

具體說明,在當命令信號READS被設定為第一邏輯值後,取樣信號產生器120可對應脈波信號CKIN的第M個脈衝,來產生被致能的取樣信號SS。其中,上述的M可以是大於1的任意正整數,並可由設計者依據實際需求來進行設定。Specifically, after the command signal READS is set to the first logic value, the sampling signal generator 120 can generate the enabled sampling signal SS corresponding to the M-th pulse of the pulse signal CKIN. Wherein, the above-mentioned M can be any positive integer greater than 1, and can be set by the designer according to actual needs.

延遲器130耦接至取樣信號產生器120。延遲器130可接收命令信號READS,並透過對命令信號READS進行延遲來產生延遲命令信號DS。取樣電路140則耦接至延遲器130以及取樣信號產生器120。取樣電路140接收延遲命令信號DS以及取樣信號SS。取樣電路140並透過取樣信號SS來對延遲命令信號DS進行取樣,以產生偵測結果SLOWCLK。其中,延遲器130可根據一個預設的延遲時間來針對命令信號READS進行延遲,並可使延遲命令信號DS的轉態時間點被推遲。The delayer 130 is coupled to the sampling signal generator 120 . The delayer 130 can receive the command signal READS and generate the delayed command signal DS by delaying the command signal READS. The sampling circuit 140 is coupled to the delay 130 and the sampling signal generator 120 . The sampling circuit 140 receives the delayed command signal DS and the sampling signal SS. The sampling circuit 140 samples the delayed command signal DS through the sampling signal SS to generate the detection result SLOWCLK. Among them, the delayer 130 can delay the command signal READS according to a preset delay time, and can delay the transition time point of the delayed command signal DS.

在本實施例中,若時脈信號CLK過慢時,根據時脈信號CLK的轉態緣所產生的脈波信號CKIN的頻率同樣也會過慢。因此,根據脈波信號CKIN的特定脈衝所產生的取樣信號SS的取樣時間點可落於延遲命令信號DS的轉態時間點的後面。如此一來,取樣電路140可產生等於第一邏輯值的偵測結果SLOWCLK,並表示使用者輸入的時脈信號CLK的頻率過慢。In this embodiment, if the clock signal CLK is too slow, the frequency of the pulse signal CKIN generated according to the transition edge of the clock signal CLK will also be too slow. Therefore, the sampling time point of the sampling signal SS generated according to the specific pulse of the pulse wave signal CKIN may fall behind the transition time point of the delayed command signal DS. In this way, the sampling circuit 140 can generate the detection result SLOWCLK which is equal to the first logic value and indicates that the frequency of the clock signal CLK input by the user is too slow.

在上述的說明中,第一邏輯值可以為邏輯值1,第二邏輯值則可以為邏輯值0。或者,在其他實施例中,第一邏輯值可以為邏輯值0,第二邏輯值則可以為邏輯值1。In the above description, the first logical value may be a logical value 1, and the second logical value may be a logical value 0. Or, in other embodiments, the first logic value may be a logic value 0, and the second logic value may be a logic value 1.

相對的,若時脈信號CLK未過慢時,根據脈波信號CKIN的特定脈衝所產生的取樣信號SS的取樣時間點可落於延遲命令信號DS的轉態時間點的前面。如此一來,取樣電路140可產生不等於第一邏輯值(例如等於第二邏輯值)的偵測結果SLOWCLK,並表示使用者輸入的時脈信號CLK的頻率未過慢。In contrast, if the clock signal CLK is not too slow, the sampling time point of the sampling signal SS generated according to the specific pulse of the pulse signal CKIN can fall before the transition time point of the delayed command signal DS. In this way, the sampling circuit 140 can generate a detection result SLOWCLK that is not equal to the first logic value (for example, equal to the second logic value), and indicates that the frequency of the clock signal CLK input by the user is not too slow.

也就是說,當偵測結果SLOWCLK等於第一邏輯值時的時脈信號CLK的第一偵測頻率可高於當偵測結果SLOWCLK等於第二邏輯值時的時脈信號CLK的第二偵測頻率。That is to say, the first detection frequency of the clock signal CLK when the detection result SLOWCLK is equal to the first logic value may be higher than the second detection frequency of the clock signal CLK when the detection result SLOWCLK is equal to the second logic value. frequency.

以下請參照圖2,頻率偵測裝置200包括脈波信號產生器210、取樣信號產生器220、延遲器230以及取樣電路240。脈波信號產生器210透過及閘AD1以接收時脈信號CLK。其中,及閘AD1另接收致能信號EN,並在當致能信號EN為邏輯值0時,遮斷使脈波信號產生器210無法接收到時脈信號CLK,此時脈波信號產生器210不執行動作。在當致能信號EN為邏輯值1時,脈波信號產生器210可接收到時脈信號CLK,並根據時脈信號CLK的轉態緣來產生脈波信號CKIN。Please refer to FIG. 2 below. The frequency detection device 200 includes a pulse signal generator 210, a sampling signal generator 220, a delay 230 and a sampling circuit 240. The pulse signal generator 210 receives the clock signal CLK through the AND gate AD1. Among them, the AND gate AD1 also receives the enable signal EN, and when the enable signal EN is a logic value 0, it is blocked so that the pulse signal generator 210 cannot receive the clock signal CLK. At this time, the pulse signal generator 210 No action is performed. When the enable signal EN is a logic value 1, the pulse signal generator 210 can receive the clock signal CLK and generate the pulse signal CKIN according to the transition edge of the clock signal CLK.

取樣信號產生器220包括多個正反器DFF1~DFF3。各個正反器DFF1~DFF3具有資料端D、時脈端CK、輸出端Q以及反向輸出端QB。其中,第一級的正反器DFF1的資料端D接收命令信號READS;正反器DFF1~DFF3的時脈端CK均接收脈波信號CKIN;正反器DFF1的輸出端Q耦接至次級的正反器DFF2的資料端D;正反器DFF2的輸出端Q耦接至次級的正反器DFF3的資料端D;正反器DFF1的反向輸出端QB則產生信號dRB;正反器DFF2的輸出端Q則產生取樣信號SS。其中,信號dRB可以為命令信號READS的反向並加上一個時間延遲。正反器DFF1可以執行命令信號READS對應脈波信號CKIN上的脈衝的同步動作。The sampling signal generator 220 includes a plurality of flip-flops DFF1 to DFF3. Each flip-flop DFF1 ~ DFF3 has a data terminal D, a clock terminal CK, an output terminal Q and an inversion output terminal QB. Among them, the data terminal D of the first-stage flip-flop DFF1 receives the command signal READS; the clock terminals CK of the flip-flops DFF1 to DFF3 all receive the pulse signal CKIN; the output terminal Q of the flip-flop DFF1 is coupled to the secondary The data terminal D of the flip-flop DFF2; the output terminal Q of the flip-flop DFF2 is coupled to the data terminal D of the secondary flip-flop DFF3; the reverse output terminal QB of the flip-flop DFF1 generates the signal dRB; the flip-flop DFF2 generates the signal dRB; The output terminal Q of the device DFF2 generates the sampling signal SS. Among them, the signal dRB can be the reverse direction of the command signal READS plus a time delay. The flip-flop DFF1 can perform a synchronization action corresponding to the pulse on the pulse signal CKIN of the command signal READS.

在本實施例中,正反器DFF2可在命令信號READS轉態為第一邏輯值後,對應脈波信號CKIN上的第二個脈衝使取樣信號SS被致能(轉態為第一邏輯值)。In this embodiment, the flip-flop DFF2 can enable the sampling signal SS (transition to the first logic value) corresponding to the second pulse on the pulse signal CKIN after the command signal READS transitions to the first logic value. ).

延遲器230接收信號dRB以及致能信號EN,在當致能信號EN為邏輯值0時,延遲器230不被啟動;相對的,在當致能信號EN為邏輯值1時,延遲器230可被啟動。延遲器230可針對信號dRB進行延遲,並產生延遲命令信號DS。The delayer 230 receives the signal dRB and the enable signal EN. When the enable signal EN is a logic value 0, the delayer 230 is not activated; on the contrary, when the enable signal EN is a logic value 1, the delayer 230 can is activated. The delayer 230 may delay the signal dRB and generate a delayed command signal DS.

取樣電路240由正反器DFF4來建構,正反器DFF4的資料端D接收延遲命令信號DS,正反器DFF4的時脈端CK接收取樣信號SS。如此一來,正反器DFF4可透過取樣信號SS來對延遲命令信號DS進行取樣,以產生偵測結果SLOWCLK。The sampling circuit 240 is constructed by a flip-flop DFF4. The data terminal D of the flip-flop DFF4 receives the delayed command signal DS, and the clock terminal CK of the flip-flop DFF4 receives the sampling signal SS. In this way, the flip-flop DFF4 can sample the delayed command signal DS through the sampling signal SS to generate the detection result SLOWCLK.

附帶一提的,在本實施例中,正反器DFF4可透過反向輸出端QB以及反向器IV2來產生偵測結果SLOWCLK。在其他實施例中,正反器DFF4也可透過反向輸出端QB來直接產生偵測結果SLOWCLK。Incidentally, in this embodiment, the flip-flop DFF4 can generate the detection result SLOWCLK through the inverter output QB and the inverter IV2. In other embodiments, the flip-flop DFF4 can also directly generate the detection result SLOWCLK through the inverting output terminal QB.

在此可以發現,本發明的頻率偵測裝置200透過使取樣電路240以針對取樣信號SS來對延遲命令信號DS進行取樣,可快速的產生偵測結果SLOWCLK,對應於使用者所提供的時脈信號CLK的頻率變化,可達到快速反應的效果。It can be found here that the frequency detection device 200 of the present invention can quickly generate the detection result SLOWCLK by causing the sampling circuit 240 to sample the delayed command signal DS for the sampling signal SS, corresponding to the clock provided by the user. The frequency change of the signal CLK can achieve a rapid response effect.

此外,頻率偵測裝置200另包括反或閘NO1以及反向器IV1。反向器IV1接收信號DET,反或閘NO1則接收反向器IV1的輸出信號以及晶片選擇信號CSB。其中,當晶片選擇信號CSB以及反向器IV1的輸出信號的其中之一為邏輯值1時,反或閘NO1可產生輸出信號CSBb以使取樣信號產生器220以及取樣電路240被重置。其中,當反向器IV1的輸出信號為邏輯值0時,輸出信號CSBb可以為反向晶片選擇信號。In addition, the frequency detection device 200 further includes an inverter NO1 and an inverter IV1. The inverter IV1 receives the signal DET, and the inverter NO1 receives the output signal of the inverter IV1 and the chip selection signal CSB. When one of the chip selection signal CSB and the output signal of the inverter IV1 is a logic value 1, the inverse OR gate NO1 can generate the output signal CSBb to reset the sampling signal generator 220 and the sampling circuit 240 . Wherein, when the output signal of the inverter IV1 is a logic value 0, the output signal CSBb may be an inverted chip selection signal.

頻率偵測裝置200還包括反或閘NO2。反或閘NO2接收正反器DFF3輸出端Q的輸出信號以及晶片選擇信號CSB,並產生致能信號EN。The frequency detection device 200 also includes an NOR gate NO2. The inverter NO2 receives the output signal from the output terminal Q of the flip-flop DFF3 and the chip selection signal CSB, and generates the enable signal EN.

以下請同步參照圖2、圖3A以及圖3B,圖3A為時脈信號CLK未發生過慢現象的頻率偵測動作的波形圖,其中,在當命令信號READS在設定時間區間TS1中被設定為一第一邏輯值(例如為邏輯值1)時,脈波信號產生器210根據時脈信號CLK的上升緣以產生具有多個脈衝的脈波信號CKIN。脈波信號CKIN的第一個脈衝可使正反器DFF1的輸出端Q產生為邏輯值1的信號Q1,正反器DFF2並根據脈波信號CKIN的第二個脈衝以在輸出端Q產生取樣信號SS。另一方面,延遲器230根據延遲正反器DFF1的反向輸出端QB所提供的信號dRB以產生延遲命令信號DS,其中延遲命令信號DS與信號Q1的上升緣間距有延遲時間dT。Please refer to Figure 2, Figure 3A and Figure 3B simultaneously below. Figure 3A is a waveform diagram of the frequency detection operation when the clock signal CLK does not occur too slowly. Among them, when the command signal READS is set to 0 in the set time interval TS1 When a first logic value (for example, logic value 1) is reached, the pulse signal generator 210 generates a pulse signal CKIN having a plurality of pulses according to the rising edge of the clock signal CLK. The first pulse of the pulse signal CKIN can cause the output terminal Q of the flip-flop DFF1 to generate a signal Q1 with a logic value of 1, and the flip-flop DFF2 can generate a sample at the output terminal Q according to the second pulse of the pulse signal CKIN. Signal SS. On the other hand, the delayer 230 generates a delayed command signal DS according to the signal dRB provided by the inverting output terminal QB of the delayed flip-flop DFF1, where there is a delay time dT between the rising edge of the delayed command signal DS and the signal Q1.

並且,取樣電路240根據取樣信號SS來對延遲命令信號DS進行取樣。在圖3A中,取樣電路240根據取樣信號SS來取樣延遲命令信號DS可產生等於邏輯值0的偵測結果SLOWCLK,並表示時脈信號CLK的頻率非為過慢的現象。Furthermore, the sampling circuit 240 samples the delayed command signal DS based on the sampling signal SS. In FIG. 3A , the sampling circuit 240 samples the delayed command signal DS according to the sampling signal SS to produce a detection result SLOWCLK equal to a logic value 0, indicating that the frequency of the clock signal CLK is not too slow.

附帶一提的,在重置時間期間RSTT1中,晶片選擇信號CSB可被拉高,並使取樣信號產生器220以及取樣電路240被重置。並在晶片選擇信號CSB重新被拉低後,頻率偵測裝置200可執行下一次的頻率偵測動作。Incidentally, during the reset time period RSTT1, the chip selection signal CSB may be pulled high, causing the sampling signal generator 220 and the sampling circuit 240 to be reset. And after the chip selection signal CSB is pulled low again, the frequency detection device 200 can perform the next frequency detection operation.

在此請注意,延遲時間dT可根據所要判斷的時脈信號CLK的頻率是為過的容許值來進行設定。其中,若可容許的時脈信號CLK的頻率為過慢的容許值較高時,延遲器230可提相對大的延遲時間dT;相對的,若可容許的時脈信號CLK的頻率為過慢的容許值較低時,延遲器230可提相對小的延遲時間dT。Please note here that the delay time dT can be set according to whether the frequency of the clock signal CLK to be determined is too high. Among them, if the allowable frequency of the clock signal CLK is too slow and the allowable value is high, the delay device 230 can provide a relatively large delay time dT; conversely, if the allowable frequency of the clock signal CLK is too slow When the allowable value of is low, the delayer 230 can provide a relatively small delay time dT.

圖3B為時脈信號CLK發生過慢現象的頻率偵測動作的波形圖,其中,在當命令信號READS在設定時間區間TS2中被設定為一第一邏輯值(例如為邏輯值1)時,脈波信號產生器210根據時脈信號CLK的上升緣以產生具有多個脈衝的脈波信號CKIN。脈波信號CKIN的第一個脈衝可使正反器DFF1的輸出端Q產生為邏輯值1的信號Q1,正反器DFF2並根據脈波信號CKIN的第二個脈衝以在輸出端Q產生取樣信號SS。另一方面,延遲器230根據延遲正反器DFF1的反向輸出端QB所提供的信號dRB以產生延遲命令信號DS,其中延遲命令信號DS與信號Q1的上升緣間距有延遲時間dT。3B is a waveform diagram of the frequency detection operation when the clock signal CLK is too slow. When the command signal READS is set to a first logical value (for example, a logical value 1) in the set time interval TS2, The pulse signal generator 210 generates a pulse signal CKIN having a plurality of pulses according to the rising edge of the clock signal CLK. The first pulse of the pulse signal CKIN can cause the output terminal Q of the flip-flop DFF1 to generate a signal Q1 with a logic value of 1, and the flip-flop DFF2 can generate a sample at the output terminal Q according to the second pulse of the pulse signal CKIN. Signal SS. On the other hand, the delayer 230 generates a delayed command signal DS according to the signal dRB provided by the inverting output terminal QB of the delayed flip-flop DFF1, where there is a delay time dT between the rising edge of the delayed command signal DS and the signal Q1.

並且,取樣電路240根據取樣信號SS來對延遲命令信號DS進行取樣。在圖3B,取樣電路240根據取樣信號SS來取樣延遲命令信號DS可產生等於邏輯值1的偵測結果SLOWCLK,並表示時脈信號CLK的頻率為過慢的現象。Furthermore, the sampling circuit 240 samples the delayed command signal DS based on the sampling signal SS. In FIG. 3B , the sampling circuit 240 samples the delayed command signal DS according to the sampling signal SS to generate a detection result SLOWCLK equal to the logic value 1, and indicates that the frequency of the clock signal CLK is too slow.

同樣的,在重置時間期間RSTT2中,晶片選擇信號CSB可被拉高,並使取樣信號產生器220以及取樣電路240被重置。並在晶片選擇信號CSB重新被拉低後,頻率偵測裝置200可執行下一次的頻率偵測動作。Similarly, during the reset time period RSTT2, the chip selection signal CSB may be pulled high, causing the sampling signal generator 220 and the sampling circuit 240 to be reset. And after the chip selection signal CSB is pulled low again, the frequency detection device 200 can perform the next frequency detection operation.

以下請參照圖4,延遲器400包括比較電路410以及參考電壓產生器420。比較電路410包括差動對412、主動負載411以及電流源413。差動對412的第一端接收信號A1,第二端則接收參考電壓VR。延遲器400的輸入級可包括串接的反向器IV41、IV42以及電阻R1、R2。信號A1可以透過延遲信號dRB來產生,其中信號A1可以為命令信號的反向延遲信號。在差動對412的第一端上,並耦接電晶體M1以及電容C1。其中電晶體M1串接在差動對412的第一端與電源電壓VP1間,電容C1則串接在差動對412的第一端與電源電壓VSS間。電源電壓VP1可以為操作電源,電源VSS則可以為參考接地電源。Please refer to FIG. 4 below. The delayer 400 includes a comparison circuit 410 and a reference voltage generator 420. The comparison circuit 410 includes a differential pair 412, an active load 411 and a current source 413. The first terminal of the differential pair 412 receives the signal A1, and the second terminal receives the reference voltage VR. The input stage of the delayer 400 may include series-connected inverters IV41 and IV42 and resistors R1 and R2. The signal A1 can be generated by delaying the signal dRB, where the signal A1 can be a reverse delayed signal of the command signal. The first end of the differential pair 412 is coupled to the transistor M1 and the capacitor C1. The transistor M1 is connected in series between the first end of the differential pair 412 and the power supply voltage VP1, and the capacitor C1 is connected in series between the first end of the differential pair 412 and the power supply voltage VSS. The power supply voltage VP1 can be the operating power supply, and the power supply VSS can be the reference ground power supply.

電晶體M1的控制端接收為反向晶片選擇信號的輸出信號CSBb,並在當輸出信號CSBb等於邏輯值0時,可使延遲器400不動作。The control terminal of the transistor M1 receives the output signal CSBb which is the reverse chip selection signal, and when the output signal CSBb is equal to the logic value 0, the delay device 400 can be disabled.

另外,參考電壓產生器420包括電阻R3以及R4。電阻R3以及R4相互串接於電源電壓VP2以及電源電壓VSS間,並形成分壓電路。參考電壓產生器420透過分壓電源電壓VP2以產生參考電壓VR,其中電源電壓VP2可以等於或不等於電源電壓VP1,且參考電壓VR可以等於電源電壓VP2的一半。In addition, the reference voltage generator 420 includes resistors R3 and R4. The resistors R3 and R4 are connected in series between the power supply voltage VP2 and the power supply voltage VSS, and form a voltage dividing circuit. The reference voltage generator 420 generates the reference voltage VR by dividing the power supply voltage VP2, where the power supply voltage VP2 may be equal to or not equal to the power supply voltage VP1, and the reference voltage VR may be equal to half of the power supply voltage VP2.

在本實施例中,延遲器400透過使命令信號的反向延遲信號與參考電壓VR比較來產生延遲效果,來取代利用多個反向器來提供延遲效果。藉此,延遲器400中不會因多個反向器的頻繁的轉態動作而產生功率消耗,可達到節能減碳的目的。In this embodiment, the delayer 400 generates a delay effect by comparing the reverse delay signal of the command signal with the reference voltage VR, instead of using multiple inverters to provide the delay effect. Thereby, the retarder 400 will not consume power due to frequent switching operations of multiple inverters, thereby achieving the purpose of energy saving and carbon reduction.

附帶一提的,比較電路410的電流源413偏壓於電源電壓RVPP,可提供穩定的偏壓電流。Incidentally, the current source 413 of the comparison circuit 410 is biased to the power supply voltage RVPP, which can provide a stable bias current.

以下請參照圖5,頻率偵測裝置500包括脈波信號產生器510、取樣信號產生器520、延遲器530以及取樣電路540。本實施例的頻率偵測裝置500與前述的頻率偵測裝置200大致相同,相關的動作細節在此不多贅述。與頻率偵測裝置200不同的,在頻率偵測裝置500中,取樣信號產生器520可包括多個正反器(例如N個,N為正整數)DFF1~DFFN。其中,設計者可根據實際的應用需求來選擇正反器DFF2~DFFN-1中的任一個來產生取樣信號SS,沒有特定的限制。Please refer to FIG. 5 below. The frequency detection device 500 includes a pulse signal generator 510, a sampling signal generator 520, a delay 530 and a sampling circuit 540. The frequency detection device 500 of this embodiment is substantially the same as the frequency detection device 200 mentioned above, and the relevant operation details will not be described again here. Different from the frequency detection device 200 , in the frequency detection device 500 , the sampling signal generator 520 may include a plurality of flip-flops (for example, N, N is a positive integer) DFF1 to DFFN. Among them, the designer can choose any one of the flip-flops DFF2~DFFN-1 to generate the sampling signal SS according to the actual application requirements, without specific restrictions.

此外,在本實施例中,取樣電路540可利用正反器DFFN+1來建構。In addition, in this embodiment, the sampling circuit 540 can be constructed using the flip-flop DFFN+1.

附帶一提的,在本實施例中,頻率偵測裝置500可應用於記憶體電路中,並在執行讀取動作時,進行使用者輸入的時脈信號CLK的頻率偵測動作。因此,頻率偵測裝置500所根據的命令信號READS可以為針對記憶體電路所執行的資料讀取命令。當然,頻率偵測裝置500也可搭配其他種類的命令信號來執行頻率偵測動作,並沒有固定的限制。Incidentally, in this embodiment, the frequency detection device 500 can be applied in a memory circuit, and when performing a reading operation, performs a frequency detection operation on the clock signal CLK input by the user. Therefore, the command signal READS based on the frequency detection device 500 can be a data read command executed for the memory circuit. Of course, the frequency detection device 500 can also be used with other types of command signals to perform frequency detection operations, and there is no fixed limit.

在本實施例中,在當時脈信號的頻率被偵測出過慢時,後續的電路(例如記憶體電路)可對應調整例如電荷泵電路的工作時脈,以及位址解碼器的工作偏壓。如此一來可有效減低電路整體的功率消耗,並有效提升整體電路的工作效益。In this embodiment, when the frequency of the clock signal is detected to be too slow, subsequent circuits (such as memory circuits) can correspondingly adjust the working clock of the charge pump circuit and the working bias of the address decoder. . In this way, the overall power consumption of the circuit can be effectively reduced, and the working efficiency of the overall circuit can be effectively improved.

以下請參照圖6,在步驟S610中,針對時脈信號的多個轉態緣進行偵測,並根據時脈信號的轉態緣來產生脈波信號。步驟S620中,則基於命令信號,根據脈波信號上的脈衝中的多個來產生取樣信號。並且,在步驟S630中,延遲該命令信號以產生延遲命令信號。在步驟S640中,則根據取樣信號來取樣延遲命令信號以產生偵測結果。Please refer to FIG. 6 below. In step S610, multiple transition edges of the clock signal are detected, and a pulse wave signal is generated according to the transition edges of the clock signal. In step S620, based on the command signal, a sampling signal is generated according to a plurality of pulses on the pulse wave signal. And, in step S630, the command signal is delayed to generate a delayed command signal. In step S640, the delayed command signal is sampled according to the sampling signal to generate a detection result.

關於上述步驟的實施細節,在前述的多個實施例及實施方式已有詳細的說明,在此不多贅述。The implementation details of the above steps have been described in detail in the previous embodiments and implementations, and will not be described again here.

綜上所述,本發明的時脈信號的頻率偵測裝置根據時脈信號的轉態緣來產生脈波信號,並根據脈波信號來產生取樣信號。取樣信號用以針對延遲命令信號來進行取樣,並藉此獲知時脈信號的頻率是否過慢。本發明的頻率偵測裝置不需要參考時脈信號,可有效減低所需要的消耗功率,並降低電路面積。另外,本發明透過取樣電路根據取樣信號來對延遲命令信號來進行取樣,可快速的獲得時脈信號的頻率狀態,提升反應速率。To sum up, the frequency detection device of the clock signal of the present invention generates the pulse wave signal according to the transition edge of the clock signal, and generates the sampling signal according to the pulse wave signal. The sampling signal is used to sample the delay command signal and thereby learn whether the frequency of the clock signal is too slow. The frequency detection device of the present invention does not require a reference clock signal, which can effectively reduce the required power consumption and reduce the circuit area. In addition, the present invention uses the sampling circuit to sample the delayed command signal according to the sampling signal, so that the frequency state of the clock signal can be quickly obtained and the response rate can be improved.

100、200、500:頻率偵測裝置 110、210、510:脈波信號產生器 120、220、520:取樣信號產生器 130、230、400、530:延遲器 140、240、540:取樣電路 CKIN:脈波信號 CLK:時脈信號 DS:延遲命令信號 READS:命令信號 SLOWCLK:偵測結果 SS:取樣信號 AD1:及閘 EN:致能信號 DFF1~DFFN+1:正反器 D:資料端 Q:輸出端 CK:時脈端 QB:反向輸出端 dRB、DET、Q1:信號 CSB:晶片選擇信號 IV1~IV3:反向器 NO2:反或閘 dT:延遲時間 TS1、TS2:設定時間區間 NO2、NO1:反或閘 CSBb:輸出信號 410:比較電路 420:參考電壓產生器 412:差動對 411:主動負載 413:電流源 VR:參考電壓 M1:電晶體 R1~R4:電阻 C1:電容 VP1、VP2、VSS、RVPP:電源電壓 S610~S640:步驟 100, 200, 500: Frequency detection device 110, 210, 510: Pulse signal generator 120, 220, 520: Sampling signal generator 130, 230, 400, 530: Delay 140, 240, 540: Sampling circuit CKIN: pulse signal CLK: clock signal DS: delayed command signal READS: command signal SLOWCLK: detection result SS: sampling signal AD1: And gate EN: enable signal DFF1~DFFN+1: flip-flop D: data side Q:Output terminal CK: clock end QB: Reverse output terminal dRB, DET, Q1: signal CSB: chip select signal IV1~IV3: reverser NO2: reverse OR gate dT: delay time TS1, TS2: Set time interval NO2, NO1: reverse OR gate CSBb: output signal 410: Comparison circuit 420: Reference voltage generator 412: Differential pair 411:Active load 413:Current source VR: reference voltage M1: Transistor R1~R4: Resistor C1: Capacitor VP1, VP2, VSS, RVPP: power supply voltage S610~S640: steps

圖1繪示本發明一實施例的時脈信號的頻率偵測裝置的示意圖。 圖2繪示本發明另一實施例的時脈信號的頻率偵測裝置的電路圖。 圖3A以及圖3B繪示本發明實施例的頻率偵測裝置的頻率偵測動作的波形圖。 圖4繪示本發明實施例的頻率偵測裝置的延遲器的實施方式的示意圖。 圖5繪示本發明另一實施例的時脈信號的頻率偵測裝置的電路圖。 圖6繪示本發明一實施例的時脈信號的頻率偵測動作的流程圖。 FIG. 1 is a schematic diagram of a frequency detection device for a clock signal according to an embodiment of the present invention. FIG. 2 is a circuit diagram of a clock signal frequency detection device according to another embodiment of the present invention. 3A and 3B illustrate waveform diagrams of the frequency detection operation of the frequency detection device according to the embodiment of the present invention. FIG. 4 is a schematic diagram of an implementation of a delay device of a frequency detection device according to an embodiment of the present invention. FIG. 5 is a circuit diagram of a clock signal frequency detection device according to another embodiment of the present invention. FIG. 6 is a flowchart of a frequency detection operation of a clock signal according to an embodiment of the present invention.

100:頻率偵測裝置 100: Frequency detection device

110:脈波信號產生器 110: Pulse signal generator

120:取樣信號產生器 120: Sampling signal generator

130:延遲器 130:Delayer

140:取樣電路 140: Sampling circuit

CKIN:脈波信號 CKIN: pulse signal

CLK:時脈信號 CLK: clock signal

DS:延遲命令信號 DS: delayed command signal

READS:命令信號 READS: command signal

SLOWCLK:偵測結果 SLOWCLK: detection result

SS:取樣信號 SS: sampling signal

Claims (17)

一種時脈信號的頻率偵測裝置,包括:一脈波信號產生器,偵測該時脈信號的多個轉態緣,並根據該時脈信號的該些轉態緣來產生一脈波信號;一取樣信號產生器,基於一命令信號,根據該脈波信號上的多個脈衝中的多個來產生一取樣信號;一延遲器,延遲該命令信號以產生一延遲命令信號;以及一取樣電路,根據該取樣信號來取樣該延遲命令信號以產生一偵測結果。 A frequency detection device for a clock signal, including: a pulse signal generator that detects multiple transition edges of the clock signal and generates a pulse signal based on the transition edges of the clock signal ; A sampling signal generator, based on a command signal, generates a sampling signal according to a plurality of pulses on the pulse wave signal; a delayer, delays the command signal to generate a delayed command signal; and a sampling The circuit samples the delayed command signal according to the sampling signal to generate a detection result. 如請求項1所述的頻率偵測裝置,其中該脈波信號產生器為一單擊電路,根據該時脈信號的多個上升緣來產生該脈波信號上的該些脈衝。 The frequency detection device of claim 1, wherein the pulse signal generator is a single-click circuit that generates the pulses on the pulse signal according to multiple rising edges of the clock signal. 如請求項1所述的頻率偵測裝置,其中該取樣信號產生器包括多個正反器,該些正反器的多個時脈端接收該脈波信號,各該正反器的輸出端耦接至下一級的各該正反器的資料端,第一級的正反器的資料端接收該命令信號,最後一級的正反器的輸出端產生一致能信號。 The frequency detection device of claim 1, wherein the sampling signal generator includes a plurality of flip-flops, multiple clock terminals of the flip-flops receive the pulse signal, and the output terminals of each flip-flop Coupled to the data terminal of each flip-flop of the next stage, the data terminal of the flip-flop of the first stage receives the command signal, and the output terminal of the flip-flop of the last stage generates a coherent signal. 如請求項3所述的頻率偵測裝置,其中第二級至最後一級的正反器的其中之一者的輸出端產生該取樣信號。 The frequency detection device of claim 3, wherein the output end of one of the flip-flops from the second stage to the last stage generates the sampling signal. 如請求項3所述的頻率偵測裝置,其中該脈波信號產生器以及該延遲器根據該致能信號以被啟動。 The frequency detection device of claim 3, wherein the pulse signal generator and the delayer are activated according to the enable signal. 如請求項3所述的頻率偵測裝置,其中該第一級的正反器的輸出端並傳輸該命令信號的一反向延遲信號。 The frequency detection device of claim 3, wherein the output end of the flip-flop of the first stage transmits a reverse delayed signal of the command signal. 如請求項6所述的頻率偵測裝置,其中該延遲器包括:一比較電路,根據比較該命令信號的該反向延遲信號與一參考電壓來產生該延遲命令信號;以及一參考電壓產生器,用以產生該參考電壓。 The frequency detection device of claim 6, wherein the delayer includes: a comparison circuit that generates the delayed command signal based on comparing the reverse delay signal of the command signal with a reference voltage; and a reference voltage generator , used to generate the reference voltage. 如請求項7所述的頻率偵測裝置,其中該延遲器更包括:一電晶體,耦接在一第一電源電壓與該比較電路接收該命令信號的該反向延遲信號的端點間,受控於一反向晶片選擇信號;以及一電容,耦接在該比較電路接收該命令信號的該反向延遲信號的端點與一第二電源電壓間。 The frequency detection device of claim 7, wherein the delayer further includes: a transistor coupled between a first power supply voltage and an end point of the reverse delay signal of the comparison circuit receiving the command signal, controlled by a reverse chip selection signal; and a capacitor coupled between an end point of the reverse delay signal where the comparison circuit receives the command signal and a second power supply voltage. 如請求項7所述的頻率偵測裝置,其中該比較電路包括:一差動對,分別接收該命令信號的該反向延遲信號與該參考電壓;一主動負載,耦接在該差動對與一第一電源電壓間;以及一電流源,耦接在該差動對與一第二電源電壓間。 The frequency detection device of claim 7, wherein the comparison circuit includes: a differential pair that receives the reverse delay signal and the reference voltage of the command signal respectively; an active load coupled to the differential pair and a first power supply voltage; and a current source coupled between the differential pair and a second power supply voltage. 如請求項7所述的頻率偵測裝置,其中該參考電壓產生器包括: 一分壓電路,接收一第三電源電壓,分壓該第三電源電壓以產生該參考電壓。 The frequency detection device of claim 7, wherein the reference voltage generator includes: A voltage dividing circuit receives a third power supply voltage and divides the third power supply voltage to generate the reference voltage. 如請求項1所述的頻率偵測裝置,其中該取樣電路包括:一正反器,具有資料端以接收該延遲命令信號,該正反器的時脈端接收該取樣信號,該正反器的輸出端產生該偵測結果。 The frequency detection device of claim 1, wherein the sampling circuit includes: a flip-flop with a data terminal to receive the delayed command signal, a clock terminal of the flip-flop to receive the sampling signal, and the flip-flop The output terminal produces the detection result. 如請求項1所述的頻率偵測裝置,其中該取樣信號產生器以及該取樣電路根據一晶片選擇信號以執行重置動作。 The frequency detection device of claim 1, wherein the sampling signal generator and the sampling circuit perform a reset operation according to a chip selection signal. 如請求項12所述的頻率偵測裝置,其中當該樣信號產生器以及該取樣電路執行該重置動作時,該脈波信號產生器以及該延遲器停止動作。 The frequency detection device of claim 12, wherein when the sample signal generator and the sampling circuit perform the reset operation, the pulse signal generator and the delayer stop operating. 一種時脈信號的頻率偵測方法,包括:偵測該時脈信號的多個轉態緣,並根據該時脈信號的該些轉態緣來產生一脈波信號;基於一命令信號,根據該脈波信號上的多個脈衝中的多個來產生一取樣信號;延遲該命令信號以產生一延遲命令信號;以及根據該取樣信號來取樣該延遲命令信號以產生一偵測結果。 A frequency detection method of a clock signal, including: detecting multiple transition edges of the clock signal, and generating a pulse wave signal based on the transition edges of the clock signal; based on a command signal, according to A plurality of pulses on the pulse wave signal are used to generate a sampling signal; the command signal is delayed to generate a delayed command signal; and the delayed command signal is sampled according to the sampling signal to generate a detection result. 如請求項14所述的頻率偵測方法,其中根據該時脈信號的該些轉態緣來產生該脈波信號的步驟包括:根據該時脈信號的多個上升緣來產生該脈波信號上的該些脈衝。 The frequency detection method according to claim 14, wherein the step of generating the pulse wave signal according to the transition edges of the clock signal includes: generating the pulse wave signal according to a plurality of rising edges of the clock signal. the pulses on. 如請求項14所述的頻率偵測方法,根據該脈波信號上的該些脈衝中的多個來產生該取樣信號的步驟包括:根據該脈波信號上的該些脈衝中來依序延遲該命令信號以產生該取樣信號。 According to the frequency detection method of claim 14, the step of generating the sampling signal according to a plurality of the pulses on the pulse wave signal includes: sequentially delaying according to the plurality of pulses on the pulse wave signal. The command signal is used to generate the sampling signal. 如請求項14所述的頻率偵測方法,更包括:在一偵測動作中,在一設定時間區間中設定該命令信號為一第一邏輯值;當產生的該偵測結果等於一第一邏輯準位時,該偵測結果指示該時脈信號的頻率為一第一偵測頻率;以及當產生的該偵測結果等於該第二邏輯值時,該偵測結果指示該時脈信號的頻率為一第二偵測頻率,其中該第一偵測頻率高於該第二偵測頻率,該第一邏輯值為該第二邏輯值的反向。 The frequency detection method as described in claim 14 further includes: in a detection action, setting the command signal to a first logical value in a set time interval; when the generated detection result is equal to a first When the detection result is equal to the second logic level, the detection result indicates that the frequency of the clock signal is a first detection frequency; and when the detection result is equal to the second logic value, the detection result indicates that the frequency of the clock signal is a first detection frequency. The frequency is a second detection frequency, wherein the first detection frequency is higher than the second detection frequency, and the first logic value is the inverse of the second logic value.
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Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
TW200601701A (en) * 2004-06-30 2006-01-01 Chung Shan Inst Of Science Dual-edge pulse detecting circuit
TW200644437A (en) * 2005-06-10 2006-12-16 Samsung Electronics Co Ltd Frequency detector in phase locked loop circuit and frequency error detecting method
TW200826507A (en) * 2006-12-12 2008-06-16 Realtek Semiconductor Corp Sample circuit and sample method thereof
US20120313715A1 (en) * 2011-06-10 2012-12-13 Broadcom Corporation Reference-Less Frequency Detector
TW202040944A (en) * 2018-09-18 2020-11-01 南韓商三星顯示器有限公司 Circuit and method of frequency detection
US20220057449A1 (en) * 2020-08-20 2022-02-24 Changxin Memory Technologies, Inc. Detection circuit and detection method

Patent Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
TW200601701A (en) * 2004-06-30 2006-01-01 Chung Shan Inst Of Science Dual-edge pulse detecting circuit
TW200644437A (en) * 2005-06-10 2006-12-16 Samsung Electronics Co Ltd Frequency detector in phase locked loop circuit and frequency error detecting method
TW200826507A (en) * 2006-12-12 2008-06-16 Realtek Semiconductor Corp Sample circuit and sample method thereof
US20120313715A1 (en) * 2011-06-10 2012-12-13 Broadcom Corporation Reference-Less Frequency Detector
TW202040944A (en) * 2018-09-18 2020-11-01 南韓商三星顯示器有限公司 Circuit and method of frequency detection
US20220057449A1 (en) * 2020-08-20 2022-02-24 Changxin Memory Technologies, Inc. Detection circuit and detection method

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