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TWI533380B - 封裝結構及其製作方法 - Google Patents

封裝結構及其製作方法 Download PDF

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Publication number
TWI533380B
TWI533380B TW100115473A TW100115473A TWI533380B TW I533380 B TWI533380 B TW I533380B TW 100115473 A TW100115473 A TW 100115473A TW 100115473 A TW100115473 A TW 100115473A TW I533380 B TWI533380 B TW I533380B
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Taiwan
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layer
patterned
wafer
dry film
package structure
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TW100115473A
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English (en)
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TW201246411A (en
Inventor
孫世豪
陳昌甫
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旭德科技股份有限公司
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Application filed by 旭德科技股份有限公司 filed Critical 旭德科技股份有限公司
Priority to TW100115473A priority Critical patent/TWI533380B/zh
Priority to CN201110158589.4A priority patent/CN102768960B/zh
Priority to US13/162,547 priority patent/US8420951B2/en
Priority to JP2012003203A priority patent/JP5442777B2/ja
Publication of TW201246411A publication Critical patent/TW201246411A/zh
Priority to US13/692,971 priority patent/US8893379B2/en
Application granted granted Critical
Publication of TWI533380B publication Critical patent/TWI533380B/zh

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    • H—ELECTRICITY
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    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/48—Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the subgroups H01L21/06 - H01L21/326
    • H01L21/4814—Conductive parts
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    • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
    • H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
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  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Manufacturing & Machinery (AREA)
  • Manufacturing Of Printed Wiring (AREA)
  • Wire Bonding (AREA)

Description

封裝結構及其製作方法
本發明是有關於一種封裝結構及其製作方法，且特別是有關於一種具有較薄厚度之封裝結構及其製作方法。
晶片封裝的目的在於保護裸露的晶片、降低晶片接點的密度及提供晶片良好的散熱。常見的封裝方法是晶片透過打線接合(wire bonding)或覆晶接合(flip chip bonding)等方式而安裝至一封裝載板，以使晶片上的接點可電性連接至封裝載板。因此，晶片的接點分佈可藉由封裝載板重新配置，以符合下一層級的外部元件的接點分佈。
一般來說，封裝載板的製作通常是以核心(core)介電層作為蕊材，並利用全加成法(fully additive process)、半加成法(semi-additive process)、減成法(subtractive process)或其他方式，將圖案化線路層與圖案化介電層交錯堆疊於核心介電層上。如此一來，核心介電層在封裝載板的整體厚度上便會佔著相當大的比例。因此，若無法有效地縮減核心介電層的厚度，勢必會使封裝結構於厚度縮減上產生極大的障礙。
本發明提供一種封裝結構，具有較薄的封裝厚度。
本發明提供一種封裝結構的製作方法，用以製作上述之封裝結構。
本發明提出一種封裝結構的製作方法，其包括下述步驟。提供一金屬基板。金屬基板具有彼此相對的一第一表面、一第二表面以及一連接第一表面與第二表面的側表面，且金屬基板上已形成有一包覆第一表面、第二表面以及側表面的種子層。形成一圖案化線路層於位於金屬基板之第一表面上之種子層的一部分上。形成一第一圖案化乾膜層於位於金屬基板之第一表面上之種子層的另一部分上。以第一圖案化乾膜層為一電鍍罩幕，以電鍍一表面處理層於圖案化線路層上。移除第一圖案化乾膜層。進行一晶片接合製程，以電性連接一晶片至表面處理層上。形成一封裝膠體於金屬基板上。封裝膠體包覆晶片、表面處理層及圖案化線路層。移除金屬基板及種子層，以暴露出封裝膠體的一底面與圖案化線路層的一下表面。
在本發明之一實施例中，上述之形成圖案化線路層的的步驟，包括：以第一圖案化乾膜層為一電鍍罩幕，以電鍍圖案化線路層於第一圖案化乾膜層所暴露出之種子層的一部分上。
在本發明之一實施例中，上述之形成圖案化線路層的步驟，包括：形成一金屬層於種子層上，其中金屬層包覆種子層；形成一第二圖案化乾膜層於位於第一表面上之部分金屬層上；以第二圖案化乾膜層為一蝕刻罩幕，移除部分金屬層，以暴露出位於第一表面上之種子層的另一部分，並形成圖案化線路層；以及移除第二圖案化乾膜層。
在本發明之一實施例中，上述之表面處理層包括一鎳層、一金層、一銀層或一鎳鈀金層。
在本發明之一實施例中，上述之晶片接合製程包括一打線接合製程或一覆晶接合製程。
本發明提出一種封裝結構，其包括一圖案化線路層、一晶片以及一封裝膠體。晶片電性連接至圖案化線路層。封裝膠體包覆晶片及圖案化線路層，且暴露出圖案化線路層的一下表面。
在本發明之一實施例中，上述之封裝結構更包括一表面處理層，配置於圖案化線路層上。
在本發明之一實施例中，上述之表面處理層包括一鎳層、一金層、一銀層或一鎳鈀金層。
在本發明之一實施例中，上述之晶片透過打線接合或覆晶接合技術與圖案化線路層電性連接。
在本發明之一實施例中，上述之圖案化線路層的下表面與封裝膠體的一底面實質上齊平。
基於上述，由於本發明是先以金屬基板做為載體，藉由電鍍法(plating)或減成法來(subtractive process)形成圖案化線路層，且待晶片進行完封裝後，再將金屬基板及種子層移除。如此一來，相較於習知具有核心介電層的封裝結構而言，本發明之封裝結構因可具有較薄的封裝厚度。再者，由於晶片配置於圖案化線路層上，且封裝膠體暴露出圖案化線路層的下表面。因此，晶片所發出的熱可經由圖案化線路層而快速地傳遞至外界。故，本發明之封裝結構可具有較佳的散熱效果。
為讓本發明之上述特徵和優點能更明顯易懂，下文特舉實施例，並配合所附圖式作詳細說明如下。
圖1A至圖1E為本發明之一實施例之一種封裝結構的製作方法的剖面示意圖。請先參考圖1A，依照本實施例的封裝結構的製作方法，首先，提供一金屬基板110，其中金屬基板110上已形成有一種子層120。詳細來說，在本實施例中，金屬基板110具有彼此相對的一第一表面112與一第二表面114、一連接第一表面112與第二表面114的側表面116以及至少一貫穿第一表面112與第二表面114的定位孔118(tooling hole)。金屬基板110的材質包括具有高導熱性的金屬，例如是銅或鋁，合金，例如是銅合金或鋁合金，但不以此為限。種子層120例如是一化學銅層，其是透過電鍍法電鍍於金屬基板110的第一表面112、第二表面114、側表面116以及定位孔118的內壁上。
接著，請參考圖1B，形成一圖案化乾膜層130於種子層120上，其中圖案化乾膜層130暴露出部分種子層120。詳細來說，圖案化乾膜層130完全覆蓋位於金屬基板110之第二表面114上方的種子層120以及定位孔118的兩端，並暴露出位於金屬基板110之第一表面112上方之部分種子層120。
接著，請再參考圖1B，形成一圖案化線路層140於圖案化乾膜層130所暴露出的部分種子層120上。在本實施例中，例如是藉由圖案化乾膜層130來進行一電鍍製程，以電鍍圖案化線路層140於金屬基板110之第一表面112上方被圖案化乾膜層130所暴露出的種子層120上。其中，本實施例可透過圖案化乾膜層130來控制圖案化線路層140的線寬與厚度。於此，圖案化線路層140的線寬例如是小於30微米，因此相較於一般線路層之線寬而言，本實施例之圖案化線路層140可視為一微細線路層。
接著，請參考圖1C，形成一表面處理層150於圖案化線路層140上，其中表面處理層150例如是一鎳層、一金層、一銀層、一鎳鈀金層或其他適當的材料層，在此並不加以限制。接著，移除圖案化乾膜層130，以暴露出位於金屬基板110之第一表面112上、第二表面114上及定位孔118之內壁上的種子層120。
接著，請參考圖1D，進行一晶片接合製程，以電性連接一晶片160a至位於圖案化線路層140上方的表面處理層150，其中本實施例之晶片接合製程例如是一打線接合製程。詳細來說，圖案化線路層140包括一晶片墊142以及至少一接墊144，其中晶片160a配置於晶片墊142上，且晶片160a透過一銲線170電性連接至接墊144上。晶片160a例如是一發光二極體晶片、一雷射二極體晶片、一繪圖晶片、一記憶體晶片、一半導體晶片等單一晶片或是一晶片模組。
然後，請再參考圖1D，形成一封裝膠體180於金屬基板110上，其中封裝膠體180包覆晶片160a、銲線170、表面處理層150、圖案化線路層140以及種子層120。
最後，請同時參考圖1D與圖1E，進行一單體化製程，以沿著定位孔118切割金屬基板110。並且，移除金屬基板110及覆蓋於金屬基板110之第一表面112上、第二表面114上以及定位孔118之內壁上的種子層120，以暴露出封裝膠體180的一底面182與圖案化線路層140的一下表面146。至此，已完成封裝結構100a的製作。
在結構上，請再參考圖1E，本實施例之封裝結構100a包括圖案化線路層140、表面處理層150、晶片160a、銲線170以及封裝膠體180。圖案化線路層140包括晶片墊142以及接墊144。晶片160a配置於晶片墊142上且透過銲線170電性連接至圖案化線路層140。表面處理層150配置於圖案化線路層140上，且部分表面處理層150位於晶片160a與晶片墊142之間，而銲線170連接於晶片160a與接墊144上方之表面處理層150之間。表面處理層150例如是一鎳層、一金層、一銀層、一鎳鈀金層或其他適當的材料層。封裝膠體180包覆晶片160a、銲線170、表面處理層150及圖案化線路層140，且暴露出圖案化線路層140的下表面146。特別是，圖案化線路層140的下表面146與封裝膠體180的底面182實質上齊平。
由於本實施例之封裝結構100a的製作方法是進行完晶片160a的封裝後，意即形成封裝膠體180，再移除金屬基板110及覆蓋金屬基板110上的種子層120。如此一來，相較於習知具有核心介電層的封裝結構而言，本實施例之封裝結構100a因不具有金屬基板110，因而可具有較薄的封裝厚度。此外，移除後的金屬基板110亦可重複利用，相較於習知採用核心介電層的封裝結構而言，本實施例之封裝結構100a亦有降低材料成本的優勢。再者，由於晶片160a配置於圖案化線路層140上，且封裝膠體180暴露出圖案化線路層140的下表面146。因此，晶片160a所發出的熱可經由圖案化線路層140而快速地傳遞至外界。故，本實施例之封裝結構100a可具有較佳的散熱效果。此外，由於本實施例可透過圖案化乾膜層130來控制圖案化線路層140的線寬與厚度，因此可製作出所需之微細線路層。
值得一提的是，本發明並不限定晶片160a與圖案化線路層140的接合形態，雖然此處所提及的晶片160a具體化是透過打線接合而電性連接至接墊144(即圖案化線路層140)上方的表面處理層150上。不過，在另一實施例中，請參考圖1F之封裝結構100b，其中晶片160b亦可透過覆晶接合的方式而電性連接至位於圖案化線路層140b上方之表面處理層150上。由此可知，上述之晶片160a與圖案化線路層140的接合形態僅為舉例說明之用，並非用以限定本發明。
以下將再利用一實施例來說明封裝結構100c及其製作方法。在此必須說明的是，下述實施例沿用前述實施例的元件標號與部分內容，其中採用相同的標號來表示相同或近似的元件，並且省略了相同技術內容的說明。關於省略部分的說明可參考前述實施例，下述實施例不再重複贅述。
圖2A至圖2D為本發明之另一實施例之一種封裝結構的製作方法的剖面示意圖。請先參考圖2A，依照本實施例的封裝結構的製作方法，首先，首先，提供一金屬基板110，其中金屬基板110上已形成有一種子層120a，且種子層120a是由一電鍍種子層122以及一包覆電鍍種子層122的鎳層124所組成。於此，種子層120a包覆金屬基板110的第一表面112、第二表面114以及側表面116。
接著，請再參考圖2A，形成一金屬層140a於種子層120a的鎳層124上，其中金屬層140a包覆種子層120a，且金屬層140a的厚度大於種子層120a的厚度。
接著，請同時參考圖2A與2B，形成一圖案化乾膜層130c於位於金屬基板110之第一表面112上之部分金屬層140a上。並且，以圖案化乾膜層130c為一蝕刻罩幕，移除部分金屬層140a，以暴露出位於第一表面112上之種子層120a的一部分，並形成一圖案化線路層140c。意即，本實施例使採用減成法的方式來形成圖案化線路層140c。接著，移除圖案化乾膜層130c以暴露出圖案化線路層140c。
然後，請參考圖2C，形成一圖案化乾膜層130於圖案化線路層140c所暴露出位於第一表面112上之種子層120a的部分上，以及形成一乾膜層130d於位於第二表面114上的種子層120a上。其中，乾膜層130d完全覆蓋位於第二表面114上的種子層120a。並且，以圖案化乾膜層130為一電鍍罩幕，以電鍍一表面處理層150於圖案化線路層上140c。
最後，依據進行移除圖案化乾膜層130及乾膜層130d、進行一晶片接合製程(其例如是打線接合製程)，以電性連接一晶片160c至表面處理層150上、形成一封裝膠體180於金屬基板110上，以包覆晶片160c、表面處理層150以及圖案化線路層140c以及移除金屬基板110及種子層120a，以暴露出封裝膠體180的底面182與圖案化線路層140c的一下表面146c，而完成圖2D之封裝結構100c的製作。此時，圖案化線路層140c的下表面146c與封裝膠體180的底面182實質上齊平。
由於本實施例之封裝結構100c的製作方法是進行完晶片160c的封裝後，意即形成封裝膠體180，再移除金屬基板110及覆蓋金屬基板110上的種子層120a。如此一來，相較於習知具有核心介電層的封裝結構而言，本實施例之封裝結構100c因不具有金屬基板110，因而可具有較薄的封裝厚度。此外，移除後的金屬基板110亦可重複利用，相較於習知採用核心介電層的封裝結構而言，本實施例之封裝結構100c亦有降低材料成本的優勢。再者，由於晶片160c配置於圖案化線路層140c上，且封裝膠體180暴露出圖案化線路層140c的下表面146c。因此，晶片160c所發出的熱可經由圖案化線路層140c而快速地傳遞至外界。故，本實施例之封裝結構100c可具有較佳的散熱效果。
綜上所述，由於本發明是先以金屬基板做為載體，藉由電鍍法(plating)或減成法來(subtractive process)形成圖案化線路層，且待晶片進行完封裝後，再將金屬基板及種子層移除。如此一來，相較於習知具有核心介電層的封裝結構而言，本發明之封裝結構因不具有載體，因而可具有較薄的封裝厚度。再者，由於晶片配置於圖案化線路層上，且封裝膠體暴露出圖案化線路層的下表面。因此，晶片所發出的熱可經由圖案化線路層而快速地傳遞至外界。故，本發明之封裝結構可具有較佳的散熱效果。此外，本發明可透過圖案化乾膜層來控制圖案化線路層的線寬與厚度，以可製作出所需之微細線路層。
雖然本發明已以實施例揭露如上，然其並非用以限定本發明，任何所屬技術領域中具有通常知識者，在不脫離本發明之精神和範圍內，當可作些許之更動與潤飾，故本發明之保護範圍當視後附之申請專利範圍所界定者為準。
100a、100b、100c．．．封裝結構
110．．．金屬基板
112．．．第一表面
114．．．第二表面
116．．．側表面
118．．．定位孔
120、120a．．．種子層
130、130c．．．圖案化乾膜層
130d．．．乾膜層
140、140b、140c．．．圖案化線路層
140a．．．金屬層
142．．．晶片墊
144．．．接墊
146、146c．．．下表面
150．．．表面處理層
160a、160b、160b．．．晶片
170．．．銲線
180．．．封裝膠體
182．．．底面
圖1A至圖1E為本發明之一實施例之一種封裝結構的製作方法的剖面示意圖。
圖1F為本發明之另一實施例之一種封裝結構的剖面示意圖。
圖2A至圖2D為本發明之另一實施例之一種封裝結構的製作方法的剖面示意圖。
100a．．．封裝結構
140．．．圖案化線路層
142．．．晶片墊
144．．．接墊
146．．．下表面
150．．．表面處理層
160a．．．晶片
170．．．銲線
180．．．封裝膠體
182．．．底面

Claims (5)

  1. 一種封裝結構的製作方法，包括：提供一金屬基板，該金屬基板具有彼此相對的一第一表面、一第二表面、一連接該第一表面與該第二表面的側表面以及至少一貫穿該第一表面與該第二表面的定位孔，且該金屬基板上已形成有一包覆該第一表面、該第二表面、該側表面以及該至少一定位孔的種子層；形成一圖案化線路層於位於該金屬基板之該第一表面上之該種子層的一部分上；形成一第一圖案化乾膜層於該金屬基板之該第一表面上之該種子層的另一部分上；以該第一圖案化乾膜層為一電鍍罩幕，以電鍍一表面處理層於該圖案化線路層上；移除該第一圖案化乾膜層；進行一晶片接合製程，以電性連接一晶片至該表面處理層上，其中該晶片位於該圖案化線路層上方的該表面處理層上；形成一封裝膠體於該金屬基板上，該封裝膠體包覆該晶片、該表面處理層以及該圖案化線路層；以及移除該金屬基板及該種子層，以暴露出該封裝膠體的一底面與該圖案化線路層的一下表面，其中該晶片所產生的熱依序透過該表面處理層及該圖案化線路層而傳遞至外界。
  2. 如申請專利範圍第1項所述之封裝結構的製作方 法，其中形成該圖案化線路層的步驟，包括：以該第一圖案化乾膜層為一電鍍罩幕，以電鍍該圖案化線路層於該第一圖案化乾膜層所暴露出之該種子層的該一部分上。
  3. 如申請專利範圍第1項所述之封裝結構的製作方法，其中形成該圖案化線路層的步驟，包括：形成一金屬層於該種子層上，其中該金屬層包覆該種子層；形成一第二圖案化乾膜層於位於該第一表面上之部分該金屬層上；以該第二圖案化乾膜層為一蝕刻罩幕，移除部分該金屬層，以暴露出位於該第一表面上之該種子層的該另一部分，並形成該圖案化線路層；以及移除該第二圖案化乾膜層。
  4. 如申請專利範圍第1項所述之封裝結構的製作方法，其中該表面處理層包括一鎳層、一金層、一銀層或一鎳鈀金層。
  5. 如申請專利範圍第1項所述之封裝結構的製作方法，其中該晶片接合製程包括一打線接合製程或一覆晶接合製程。
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TWI533380B (zh) * 2011-05-03 2016-05-11 旭德科技股份有限公司 封裝結構及其製作方法
US9892952B2 (en) 2014-07-25 2018-02-13 Semiconductor Components Industries, Llc Wafer level flat no-lead semiconductor packages and methods of manufacture
DE102015114662A1 (de) * 2015-09-02 2017-03-02 Osram Opto Semiconductors Gmbh Verfahren zur Herstellung eines optoelektronischen Halbleiter-Bauteils, optoelektronisches Halbleiter-Bauteil, Temporärer Träger
CN110383437A (zh) * 2016-12-22 2019-10-25 深圳中科四合科技有限公司 一种二极管的封装方法及二极管
CN106783631B (zh) * 2016-12-22 2020-01-14 深圳中科四合科技有限公司 一种二极管的封装方法及二极管
CN106783632B (zh) * 2016-12-22 2019-08-30 深圳中科四合科技有限公司 一种三极管的封装方法及三极管
CN107146774A (zh) * 2017-04-19 2017-09-08 深圳市环基实业有限公司 一种ic封装用载板及其封装工艺
CN108807325A (zh) * 2017-05-04 2018-11-13 无锡天芯互联科技有限公司 一种新型的芯片封装结构及其制作方法
CN113973431B (zh) * 2020-07-23 2023-08-18 宏启胜精密电子(秦皇岛)有限公司 电路板及其制作方法

Family Cites Families (15)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH07231062A (ja) * 1994-02-18 1995-08-29 Dainippon Printing Co Ltd リードフレームの加工方法
JP3869849B2 (ja) * 2000-04-25 2007-01-17 九州日立マクセル株式会社 半導体装置の製造方法
JP4073294B2 (ja) * 2002-11-06 2008-04-09 三洋電機株式会社 回路装置の製造方法
JP4541763B2 (ja) * 2004-01-19 2010-09-08 新光電気工業株式会社 回路基板の製造方法
US7589407B2 (en) * 2005-04-11 2009-09-15 Stats Chippac Ltd. Semiconductor multipackage module including tape substrate land grid array package stacked over ball grid array package
JP2006303305A (ja) * 2005-04-22 2006-11-02 Aoi Electronics Co Ltd 半導体装置
CN100442465C (zh) * 2005-09-15 2008-12-10 南茂科技股份有限公司 不具核心介电层的芯片封装体制程
JP2007109914A (ja) * 2005-10-14 2007-04-26 Sony Corp 半導体装置の製造方法
US7875988B2 (en) * 2007-07-31 2011-01-25 Seiko Epson Corporation Substrate and manufacturing method of the same, and semiconductor device and manufacturing method of the same
US7928574B2 (en) * 2007-08-22 2011-04-19 Texas Instruments Incorporated Semiconductor package having buss-less substrate
TWI394248B (zh) * 2008-05-22 2013-04-21 Unimicron Technology Corp 封裝基板之製法
TWI371830B (en) * 2008-05-29 2012-09-01 Advanced Semiconductor Eng Circuit board process
US7919851B2 (en) * 2008-06-05 2011-04-05 Powertech Technology Inc. Laminate substrate and semiconductor package utilizing the substrate
US8288869B2 (en) * 2009-05-13 2012-10-16 Advanced Semiconductor Engineering, Inc. Semiconductor package with substrate having single metal layer and manufacturing methods thereof
TWI533380B (zh) * 2011-05-03 2016-05-11 旭德科技股份有限公司 封裝結構及其製作方法

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