JP5442777B2 - パッケージ構造およびその製造方法 - Google Patents
パッケージ構造およびその製造方法 Download PDFInfo
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- JP5442777B2 JP5442777B2 JP2012003203A JP2012003203A JP5442777B2 JP 5442777 B2 JP5442777 B2 JP 5442777B2 JP 2012003203 A JP2012003203 A JP 2012003203A JP 2012003203 A JP2012003203 A JP 2012003203A JP 5442777 B2 JP5442777 B2 JP 5442777B2
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- 238000004519 manufacturing process Methods 0.000 title claims description 30
- 239000010410 layer Substances 0.000 claims description 229
- 229910052751 metal Inorganic materials 0.000 claims description 59
- 239000002184 metal Substances 0.000 claims description 59
- 239000000758 substrate Substances 0.000 claims description 44
- 238000000034 method Methods 0.000 claims description 34
- 239000011241 protective layer Substances 0.000 claims description 21
- PXHVJJICTQNCMI-UHFFFAOYSA-N Nickel Chemical compound [Ni] PXHVJJICTQNCMI-UHFFFAOYSA-N 0.000 claims description 16
- 239000008393 encapsulating agent Substances 0.000 claims description 15
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 claims description 12
- 229910052737 gold Inorganic materials 0.000 claims description 12
- 239000010931 gold Substances 0.000 claims description 12
- 239000003566 sealing material Substances 0.000 claims description 12
- 229910052759 nickel Inorganic materials 0.000 claims description 8
- 238000009713 electroplating Methods 0.000 claims description 7
- BQCADISMDOOEFD-UHFFFAOYSA-N Silver Chemical compound [Ag] BQCADISMDOOEFD-UHFFFAOYSA-N 0.000 claims description 6
- BSIDXUHWUKTRQL-UHFFFAOYSA-N nickel palladium Chemical compound [Ni].[Pd] BSIDXUHWUKTRQL-UHFFFAOYSA-N 0.000 claims description 6
- 229910052709 silver Inorganic materials 0.000 claims description 6
- 239000004332 silver Substances 0.000 claims description 6
- 238000005530 etching Methods 0.000 claims description 4
- 229910045601 alloy Inorganic materials 0.000 claims description 3
- 239000000956 alloy Substances 0.000 claims description 3
- 239000000126 substance Substances 0.000 claims description 2
- 239000011162 core material Substances 0.000 description 11
- 239000000463 material Substances 0.000 description 7
- 230000017525 heat dissipation Effects 0.000 description 4
- 238000007747 plating Methods 0.000 description 3
- 239000000654 additive Substances 0.000 description 2
- 229910000838 Al alloy Inorganic materials 0.000 description 1
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 description 1
- 229910000881 Cu alloy Inorganic materials 0.000 description 1
- 230000000996 additive effect Effects 0.000 description 1
- 229910052782 aluminium Inorganic materials 0.000 description 1
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 1
- 229910052802 copper Inorganic materials 0.000 description 1
- 239000010949 copper Substances 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 230000000149 penetrating effect Effects 0.000 description 1
- 239000004065 semiconductor Substances 0.000 description 1
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- Engineering & Computer Science (AREA)
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- Computer Hardware Design (AREA)
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- Manufacturing Of Printed Wiring (AREA)
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Description
110:金属基板
112:第1表面
114:第2表面
116:側面
118:位置決め孔
120、120a:シード層
130、130c:パターンドライフィルム層
130d:ドライフィルム層
140、140b、140c:パターン回路層
140a:金属層
142:チップパッド
144:パッド
146、146c:下表面
150:表面保護層
160a、160b、160c:チップ
170:ボンディングワイヤー
180:封止材
182:底面
Claims (9)
- 互いに背向する第1表面及び第2表面、並びに当該第1表面及び当該第2表面を接続する側面を有し、前記第1表面、前記第2表面、及び前記側面を電気めっきされた化学合金層であるシード層が覆う金属基板を提供するステップと、
前記金属基板の前記第1表面に位置する前記シード層の他の部分に第1パターンドライフィルム層を形成するステップと、
前記第1パターンドライフィルム層を電気めっき遮蔽膜として用いて前記第1パターンドライフィルム層によって露出された前記シード層の一部にパターン回路層を形成した後、続いて前記パターン回路層に表面保護層を電気めっきするステップと、
前記第1パターンドライフィルム層を除去するステップと、
チップを前記表面保護層に電気的に接続するためにチップボンディングプロセスを実行するステップと、
前記金属基板に封止材を形成し、前記封止材が前記チップ、前記表面保護層、及びパターン回路層をカプセル化することと、
前記チップから発生した熱を前記表面保護層及び前記パターン回路層を通して外部環境に伝送させるために、前記金属基板及び前記シード層を除去することにより、前記封止材の底面及び前記パターン回路層の下表面を露出させるステップと、
を備え、
前記金属基板を提供するステップの後、且つ前記表面保護層を電気めっきするステップの前に、前記金属基板の前記第1表面に位置する前記シード層の一の部分に前記パターン回路層を形成するステップを更に備えるパッケージ構造の製造方法。 - 前記パターン回路層のステップが、
前記シード層に金属層を形成し、当該金属層が前記シード層を覆うここと、
前記第1表面に位置する前記金属層の一の部分に第2パターンドライフィルム層を形成することと、
前記第2パターンドライフィルム層をエッチング遮蔽膜として用いて前記金属層の他の部分を除去して、前記第1表面に位置する前記シード層の前記他の部分を露出すること、及び前記パターン回路層を形成することと、
前記第2パターンドライフィルム層を除去することと
を含む請求項1に記載のパッケージ構造の製造方法。 - 前記表面保護層がニッケル層、金層、銀層又はニッケルパラジウム金層を含む請求項1または2に記載のパッケージ構造の製造方法。
- 前記チップボンディングプロセスがワイヤボンディングプロセス、又はフリップチップボンディングプロセスを含む請求項1から3の何れか1項に記載のパッケージ構造の製造方法。
- 前記パターン回路層と、
前記パターン回路層に電気接続する前記チップと、
前記チップ及び前記パターン回路層をカプセル化し、前記パターン回路層の前記下表面を露出する前記封止材と
を含む請求項1に記載の製造方法を適用することによって形成されるパッケージ構造。 - 更に、前記パターン回路層に位置する前記表面保護層を含む請求項5に記載のパッケージ構造。
- 前記表面保護層がニッケル層、金層、銀層又はニッケルパラジウム金層を含む請求項5または6に記載のパッケージ構造。
- ワイヤーボンディング又はフリップチップボンディングによって前記パターン回路層に電気接続する前記チップを含む請求項5から7の何れか1項に記載のパッケージ構造。
- 前記パターン回路層の前記下表面及び前記封止材の前記底面は同一平面上にある請求項5から8の何れか1項に記載のパッケージ構造。
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US9892952B2 (en) | 2014-07-25 | 2018-02-13 | Semiconductor Components Industries, Llc | Wafer level flat no-lead semiconductor packages and methods of manufacture |
DE102015114662A1 (de) * | 2015-09-02 | 2017-03-02 | Osram Opto Semiconductors Gmbh | Verfahren zur Herstellung eines optoelektronischen Halbleiter-Bauteils, optoelektronisches Halbleiter-Bauteil, Temporärer Träger |
CN106783631B (zh) * | 2016-12-22 | 2020-01-14 | 深圳中科四合科技有限公司 | 一种二极管的封装方法及二极管 |
CN110383437A (zh) * | 2016-12-22 | 2019-10-25 | 深圳中科四合科技有限公司 | 一种二极管的封装方法及二极管 |
CN106783632B (zh) * | 2016-12-22 | 2019-08-30 | 深圳中科四合科技有限公司 | 一种三极管的封装方法及三极管 |
CN107146774A (zh) * | 2017-04-19 | 2017-09-08 | 深圳市环基实业有限公司 | 一种ic封装用载板及其封装工艺 |
CN108807325A (zh) * | 2017-05-04 | 2018-11-13 | 无锡天芯互联科技有限公司 | 一种新型的芯片封装结构及其制作方法 |
CN113973431B (zh) * | 2020-07-23 | 2023-08-18 | 宏启胜精密电子(秦皇岛)有限公司 | 电路板及其制作方法 |
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JP3869849B2 (ja) * | 2000-04-25 | 2007-01-17 | 九州日立マクセル株式会社 | 半導体装置の製造方法 |
JP4073294B2 (ja) * | 2002-11-06 | 2008-04-09 | 三洋電機株式会社 | 回路装置の製造方法 |
JP4541763B2 (ja) * | 2004-01-19 | 2010-09-08 | 新光電気工業株式会社 | 回路基板の製造方法 |
US7589407B2 (en) * | 2005-04-11 | 2009-09-15 | Stats Chippac Ltd. | Semiconductor multipackage module including tape substrate land grid array package stacked over ball grid array package |
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US7875988B2 (en) * | 2007-07-31 | 2011-01-25 | Seiko Epson Corporation | Substrate and manufacturing method of the same, and semiconductor device and manufacturing method of the same |
US7928574B2 (en) * | 2007-08-22 | 2011-04-19 | Texas Instruments Incorporated | Semiconductor package having buss-less substrate |
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US7919851B2 (en) * | 2008-06-05 | 2011-04-05 | Powertech Technology Inc. | Laminate substrate and semiconductor package utilizing the substrate |
US8288869B2 (en) * | 2009-05-13 | 2012-10-16 | Advanced Semiconductor Engineering, Inc. | Semiconductor package with substrate having single metal layer and manufacturing methods thereof |
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US20130095615A1 (en) | 2013-04-18 |
TWI533380B (zh) | 2016-05-11 |
US8420951B2 (en) | 2013-04-16 |
CN102768960B (zh) | 2014-12-31 |
CN102768960A (zh) | 2012-11-07 |
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