JPS59146266A - Coding and decoding device - Google Patents

Abstract

PURPOSE:To attain high speed processing by using plural combinations of SLIs exclusive for coding and decoding and small capacity of buffer memories and arranging small capacity of buffer memories to for an interface between a large capacity screen memory and an external device and controlling them. CONSTITUTION:A system control processor 1 includes a microprocessor, a direct memory access controller and circuits required for operating them. An exclusive LSI 17 is used for a coding and decoding processor 2. The LSI 17 has IF sections 12, 13, a memory 14, a processing circuit 15 and a code table storage memory 16. In figure, 20 and the like is a small capactiy buffer. The section A in figure is a timing transferring data from a system bus 11 to memories 20, 21. even if four sets of coding and decoding circuits have a slow transfer capability, when the bus 11 and the direct memory access controller have a high speed, four time data transfer capability is given as the four sets entirely. In a section B,the LSI 17 accesses freely the memories 20, 21 for processing coding. Thus, the produced code is arranged into a prescribed data width in the LSI according to the timing and transferred to the bus 11. In a section C, it shows the queue timing of each coding and decoding circuit.

Description

[Detailed Description of the Invention] [Field of Application of the Invention] The present invention relates to an encoding/decoding device for image data of equipment such as a facsimile that handles image data, and particularly relates to an ultra-high-speed and large-scale image data encoding/decoding device using a large-capacity screen memory. Suitable for capacitive image 7'-p processing' code ° decoding device 1 related:

1 [Prior art] Facsimile is based on C (G3 according to JTT Recommendation Il+.4).
It is common to apply standard encoding/decoding methods,
This is a small scale device. -! , high-performance encoding/decoding devices are used for image files, etc., but most of them are based on general-purpose computer software processing systems or facsimile circuits, and are directly related to the present invention. No encoding/decoding unification device is known.

[Purpose of the invention]

An object of the present invention is to relate to an encoding/decoding processing device having a large capacity screen memory and capable of high-speed processing.

Another object of the present invention is to relate to an encoding/decoding device that can handle large amounts of image data with a simple configuration.

Still another object of the present invention relates to an encoding/decoding device capable of transferring large amounts of image data at high speed.

Still another object of the present invention is to provide a dedicated circuit (LSI: l, large 5ca
The present invention is characterized in that it provides an encoding/decoding device with even higher performance using an integrated circuit (including an integrated circuit).

[Summary of the invention]

The present invention is a dedicated LSI for symbol/decoding that can operate independently.
is combined with a small-capacity buffer memory, multiple sets of these are used, and a small-capacity buffer memory is also placed between the large-capacity screen memory and the external interface, and these are controlled by a microprocessor and a direct memory access controller. It was designed to do so.

[Embodiment J of the Invention An embodiment of the present invention will be described below with reference to the drawings. 1st
- The figure is an overall configuration diagram of the encoding/decoding device of this embodiment. In FIG. 1, 1 is a /stem control processor,
Microprocessors, direct memory access controllers, and timing control circuits necessary for these to operate 1. Input control circuits, timers, read-only memory (R
OM).

Contains random access memory (RAM) and bus interface circuits. 2 is an encoding/decoding processor, which will be described in detail later. 3 is a reading device, 4 is a reading interface, 5 is a recording device, and 6 is a recording interface. Reference numeral 7 denotes a large-capacity screen memory, which uses a dynamic type IC memory, has a capacity of 4 Mbytes, and includes a refresh control circuit and a bus interface. 8 is a transmission interface having a small capacity buffer memory, and 9 is a transmission control processor having a panel 10 for implementing transmission control procedures and having an interface with a transmission line (LINE). There is.

11 is a system bus that connects these.

The image data read by the reading device 3 enters the screen memory 7 via the reading interface 4 under the control of the system control processor 1.

The image data in the screen memory 7 is stored in the recording interface 6.
It is possible to output the data directly to the recording device 5 and record it via the . The screen memory 7 can also store coded data that interfaces directly with the encoding/decoding processor 2, and the coded data in the screen memory 7 can also be transferred to the transmission interface 8 under the control of the system processor 1.
It can communicate with the transmission line via the transmission control processor 9 and the transmission control processor 9.

The encoding/decoding processor 2 includes an LS dedicated to encoding/decoding.
Use I. FIG. 2 is an internal configuration diagram of the dedicated LSI. In FIG. 2, 12 is an interface section with the system bus, 13 is an interface section with the memory bus,
14 is a memory for storing a microprogram, 15 is an encoding/decoding processing circuit, and 16 is a memory for storing a code table. These constitute 8 I 17.

The system bus interface 12 is connected to the system bus 11 in FIG. ) to exchange money. It is an interface. Memorino; Sinterface 13
interfaces with the memory node and exchanges data with line memory and other input/output circuits connected to the memory node. The memory 16 stores facsimile-specific codes (ME-
1MR code) and assists the processing circuit 15 in the code/reply operation. The memory 14 stores data and programs necessary for the processing circuit 15 to operate.

The details of this LSI are almost the same as those of the previously developed 1 and 8I (patent pending), so the explanation will be omitted.

Next, with reference to FIG. 3, the entire operation of this LSI will be briefly explained, and the encoding/decoding processor of the present invention will be explained. In FIG. 3, 11 is a system control bus, and 17 is an LSI for encoding/decoding.

18-I B/// are input/output circuits 20-20"21-21"' (manual-scale This memory constitutes the buffer memory. Image data is transferred to and from the system bus 1 at high speed using the input/output circuit 18 under the control of the die/cut memory access controller in the system control processor and the microcomputer. ) M A is transferred. The code data is transferred only between the LS 117 and the screen memory 7, and this is also controlled by the direct memory access controller. Each LSI
As mentioned above, 4. Configure the encoding/decoding circuit of ll,
These operate at the timing shown in FIG. In other words, in FIG.
It's time to transfer the evening. Even if the four encoding/decoding circuits have slow data transfer capabilities, the system bus 11
If the direct memory access controller 31 has a sufficiently fast data transfer capability (in this case, about 4 times that of the encoding/decoding circuit), the encoding/decoding circuit will also be able to transfer all four sets (~
4 times the data transfer capacity. Section B is each LSI1
This is the timing at which No. 7 operates. Each LS117
, the memory 20.21 is freely accessed via the memory bus 19 dedicated to the SI 17, and encoding processing is performed.

Therefore, the generated code is L depending on the generation timing.
The data is arranged in a predetermined data width within the SI and transferred to the system bus 1.1 under DMA control. The image data given to each set of memories 20 and 21 is passed in units of scanning lines,
The data is transferred from the screen memory in a serial format or in a story format.

In sequential form, each set has nth, n+1st, n4-2
This format is used when the screen memory is small and cannot store the entire image data of one screen. Next, in the batch format, when the screen memory is large enough to store the image data of the entire screen, in this case, each screen is divided into 4 parts, and each encoding/decoding circuit has a small scanning line, e.g. It is a format in which image data is given and encoded in units of one scanning line, and DMA activation control is not very easy.
The advantage is that the processing load on the microprocessor is light. In any case, each output code block needs to be concatenated and transmitted, so each LSI function is such that at processing path f, the blocks are aligned to a predetermined data width, and the last code is aligned to the data width. If this is not met, you may participate in the dummy hit. The next timing section C is for each code.
This is the waiting timing for the processing of the decoding circuit. In the case of sequential processing, in addition to inserting a fill (dummy bit: time fill according to CCITT Recommendation T.4) for each scanning line, a time fill for waiting in this section may be inserted. Among these processes, the process can be easily controlled by using the rotation mode of the direct memory access controller for data transfer to and from the screen memory. Note that the decryption process is performed by performing the reverse operation above, but
In this case, although not shown, the transmission interface detects a scanning line synchronization signal so that the code can be displayed on a scanning line basis. This can be easily achieved by providing a synchronization code detection function in the reception interface.

In other words, when the synchronization signal is detected, the last ODM of the scanning line is detected.
All you have to do is make it perform the Arj;h operation, then initialize the interface and take the damage. By this operation, parallel operation of each code/decoding circuit is possible in order to align data widths of codes for each scanning line.

FIG. 5 shows the concept of a timing control system for these data transfer operations. In FIG. 5, 30 is a microprocessor, 3] is a direct memory access controller, and 33 and 33'.

36 and 36' are alternating buffer memories for read and write interfaces, respectively, each having an interface with the DMA controlled system bus 11, 35,37. 381-j is a dynamic type R, AM that constitutes the screen memory, and therefore the refresh control circuit 39
is added. Data transfer between each coat is performed by DMA, but since a buffer memory is provided in the read and write interfaces, there is an advantage that burst 7-code DMA transfer is possible. Note that at the refresh 1 timing, the microprocessor 30 and the direct memory access controller 31 stand by for a - moment.

As shown in 2, according to this example, j1 alone operates ij
Using a high-performance LSI, it has become possible to quadruple the power and use it. In addition, the screen memory is managed by the microphone L1 processor and the direct memory access controller 1.
-o-ra and 1. dedicated to encoding and decoding. Sl
It has the advantage of greatly increasing screen management ability.

[Effect of the invention] The non-invention has the effect of being able to handle human welfare image data with a simple 11/4 structure. That is, since the screen memory t is managed by the microphone L1 processor and the direct memory access controller, a configuration similar to that of a normal computer is possible, and a special additional configuration is undesirable.

J) According to the present invention, each interface uses a buffered version of the short answer *, so it can be used in burst mode.
It is capable of MA operation and high-speed image data transfer.

Furthermore, the present invention is a small-scale LS for facsimile machines.
There is an advantage that image data of human figure H can be processed at high speed using I.

[Brief explanation of drawings]

Fig. 1 is a block diagram of the configuration of an embodiment of the present invention;
, an internal block diagram of the dedicated LSI, FIG. 3 is a block diagram showing the configuration of the encoding/decoding processing processor 2, FIG. 4 is a timing chart 1 of the encoding/decoding processing, and FIG. 5 is a data transfer FIG. 2 is a block diagram showing the concept of control. DESCRIPTION OF SYMBOLS 1... System control processor, 2... Bow/decoding processor, 3... Reading 9 device, 4... Reading interface, 5... Recording device, 6... Recording interface, 7...・・Screen memory, 8・Transmission interface, 9・Transmission control unit”?, 10・
...Panel, 11...System bus. -, Agent: Patent Attorney Meikai Takahashi, U\~''/Ii1llll'':'j'',':□Int'rl2poor゛history) Star l shi4 // 1 $2 Figure/ 2 /4 /J))'1 Bud 3 20 /7 Procedural amendment (method) ','i1X'l' li Naganobu Kazuo Wakasugi・I=,
f'l (ha table)
(Jn'l'1lli! No. 21323-,; invention ('')
name il'+, encoder/decoder equipment
': 9) Relationship '4"r rf'lout1('tt
,A. t, 11.151LH1+'1 formula i-ne 1. El
1.1. Ll 1 inside j1i1j ・Mito・・・Jl! -1111 is substituted, and -more than -387=

Claims (1)

[Claims] (1) An encoding/decoding device characterized in that a plurality of independently operable encoding/decoding LSIs are used and operated in parallel. 2. A code/decoding LSI with a function of arranging output code bits to a predetermined data width, which enables parallel operation. 3. An encoding/decoding device characterized in that a reading/recording interface, a large screen memory, an encoding/decoding circuit, and the transfer of image data and encoded data between these are controlled by a microprocessor and a direct memory access controller. conversion device. 4. The encoding/decoding device according to item 3, characterized in that a buffer memory is arranged at the interface of a portion where image data transfer is necessary. 5. The encoding/decoding device according to item 3, which has a function of detecting a synchronization signal from the received code and aligning the code bit string to a predetermined data width according to the synchronization signal.