JPS60191374A - Picture processor - Google Patents

Abstract

PURPOSE:To perform the picture processing at a high speed by providing a data processing circuit to a picture processor consisting of a picture input/output circuit, a picture memory circuit and a CPU to give an access to said picture input/output circuit and picture memory circuit respectively via a memory access bus. CONSTITUTION:The pictures obtained through a camera 1 are supplied to a picture input/output circuit 3 through a camera control system 2. The picture data is fetched to a picture memory 4 via an external bus and then read by a data processing circuit 20 via a memory access bus 21. The processed data is sent back to the memory 4 via the bus 21. In such a way, the processing can be individually turned into a hard form and delivered to an interface circuit 7 in addition to the soft processing carried out by a CPU5. This attains the picture processing at a high speed.

Description

Detailed Description of the Invention: fat Technical Field of the Invention The present invention relates to an image processing device, and for example, an image processing device attached to an automatic bonding device that automatically recognizes a bonding position and performs wire bonding when manufacturing a semiconductor device. Regarding.

(bl Background of technology) With the development of semiconductor devices, their manufacturing methods have also become more sophisticated, and manufacturing is carried out by incorporating automatic control methods using microcomputers, etc. into each process.The above-mentioned wire bonding Automatic bonding methods are also used in manufacturing and chip bonding processes, and image processing devices that automatically recognize the surface of semiconductor chips for this purpose have become widely used.

Although the present invention relates to such an image processing device, it is not necessarily limited thereto. This proposal is generally related to devices that perform image recognition processing using microcomputers and the like.

(01 Prior Art and Problems Figure 1 shows the configuration of such a conventional image processing device. An image captured by a camera 1 (for example, an image of a chip surface) is input and output through a camera control system 2. It is input to the circuit 3 and stored in the image memory circuit 4 (hereinafter abbreviated as image memory) dedicated to this image input/output circuit.
The stored binary memory data is sent to the CPU via a CPU bus 6 controlled by a CPU (central control unit) 5 in a timely manner.
The data is processed by the PU 5 and the processed data is output from the interface circuit 7. Next, the processed data is inputted to the interface circuit 9 of the external processing device controlled by another CPU 8, and processed through the CP (J The data is stored in the memory 11.The other external processing device controlled by the CPU 8 is, for example, a control system information processing device that controls the mechanical section of an automatic wire bonding device, and based on the processing data, the external processing device is The parts are movable.

By the way, the image processing apparatus shown in FIG.
The stored memory data is stored in the CPU Hassix 6.
The processed data is processed by the CPU 5 via software as appropriate, and the processed data is stored in the image memory 4 again, and this processed data is outputted from the interface circuit 7 via the CPU lot 6 again.

However, such a method using only software processing has the disadvantage that the processing itself is complicated and that data processing and data transfer take a lot of time.

+d+ Object of the Invention The present invention proposes an image processing device that eliminates such drawbacks and increases processing speed.

(el) Structure of the Invention The object of the invention is to newly provide a data processing circuit in an image recognition device having an image input/output circuit, an image memory circuit, and a control CPU, and to connect the data processing circuit, the image memory circuit, and the image input/output circuit to the image recognition device. An image characterized in that a memory access bus for hardware processing is provided to access the memory access bus, and processing functions similar to processing performed by software via a CPU bus are performed via the memory access bus. This is accomplished by a processing device.

ffl Embodiments of the Invention The present invention will be described in detail below.In other words, in addition to the conventional software processing by the control CPU, the present invention is capable of performing image input by making the arithmetic processing hardware and providing a separate data processing circuit. This is a system that allows direct access to an image memory independent of the output circuit, and for this purpose, the system is configured to include an external bus separate from the CPU bus 5.

FIG. 3 shows a configuration diagram of such an image processing apparatus according to the present invention, and 20 is a data processing circuit.

21 is a memory access bus (hereinafter referred to as external bus)
The other symbols are the same parts as in FIG. 1 and are given the same symbols. With this configuration, the image data obtained from the image input/output circuit 3 is first imported into the image memory 4 via the external bus, and the captured image data is transferred to the data processing circuit 2o via the external bus 21. The data can be read and sent back to the image memory 4 via the external bus 21. Therefore, the CPU 5 is able to perform the above processing and the processing speed can be increased.

FIG. 4 shows a more detailed data processing circuit 20 and image memory 4.
4I is a memory, 42 is a bus controller, 43 is an external bus buffer, and 44 is a CPU hash buffer. In this way, a read signal or a write signal is sent from the data processing circuit 20, an address is specified, and data is directly exchanged between the data processing circuit 20 and the image memory 4, whereas the conventional CPU bus This shows that the same process can be performed via .

In this way, a plurality of processing circuits having the same external bus 21 in FIG. 3 can be connected, and the processing capacity can be increased.

Furthermore, when transferring to an external processing device as shown in FIG. 5, there is an advantage that the image memory 4 can be shared by the external processing device by accessing the CPU 10 of the external processing device. .

(gl Effects of the Invention As can be seen from the above description, the present invention has a significant effect of increasing the processing speed because the software processing in the image processing apparatus is combined with the hardware processing.

[Brief explanation of drawings]

Fig. 1 is a block diagram of a conventional image processing device, Fig. 2 is a system diagram of its data transfer, Fig. 3 is a block diagram of an image processing device according to the present invention, and Fig. 4 is a detailed diagram of Fig. 3. FIG. 5 is a block diagram of a data processing circuit and an image memory, and is a system diagram of data transfer according to the present invention. In the figure, 1 is the camera, 2 is the camera control system, 3 is the image input/output circuit, 4 is the image memory (device), 5.8 is the CPU, 6
．． 10 is a CPU bus, 7 and 9 are interface circuits,
11 is a memory, 20 is a data processing circuit, and 21 is an external lot. Agent Patent Attorney Hiroshi Matsuoka 4th Department

Claims (1)

[Claims] Image input/output circuit 9 In an image processing apparatus having an image memory circuit and a control CPU, a data processing circuit is newly provided, and a hardware processing circuit for accessing the data processing circuit, the image memory circuit and the image input/output circuit is provided. An image processing apparatus characterized in that a memory access bus is provided, and processing functions similar to those performed by software via a CPU bus are performed via the memory access bus.