JPS61262870A - Bus controlling system - Google Patents

Abstract

PURPOSE:To increase a processing speed as a whole by providing a bus splitting device that splits plural units into plural groups on halfway of a bus used in common by plural units and making direction control and separation control of transferred information. CONSTITUTION:When an instruction processing unit 4 outputs a memory address to 1, a signal line 9 is set to 1 and a signal line 10 is set to 0, and the memory address is transmitted to a bus 2 and received by a cash memory unit 6 and a main memory unit 7. In the case of cash miss, the main memory unit 7 outputs read data to the bus 2. At this time, the signal line 9 is set to 0, and signal line 10 is set to 1, and the read data are transmitted to a bus 1 and received by an instruction processing unit 4. Then, both signal lines 9 and 10 are set to 0, and the bus 1 and bus 2 are cut off, and indication to take out instruction is fed from an instruction taking out unit 5 to the instruction processing unit 4 on the bus 1.

Description

[Detailed description of the invention]

[Industrial Field of Application] The present invention provides an interface for data transfer inside a data processing device, etc.
This relates to a control method for buses that cannot be used. [Prior Art] FIG. 4 shows an example of a data processing device using a conventional bus control method. In Fig. 4, a3, (1) is a data transfer hub, which in this example is composed of 32 signal lines, and 1
It is possible to transfer 32 bits (1 word) of data per transfer. Connected to this lotus (1) are instruction processing units 1 to (4), instruction retrieval unit (5), ↑ Yashiko memory 1 unit (6), and 1,000 memory unit 1 to (7). has been done. Each of these units uses a wired-off 7-way bus (
It is connected to the bus (1) and has a bidirectional data transfer function that allows it to send data to the bus (1) and receive data from the bus (1). In this case, the control when each unit sends or receives data to the bus (1) is controlled by the bus controller (8).

[Become.] In the operation when C゛, instruction processing] Nira h (4> reads memory data, a case where a cache: 1 hit is made is shown in Fig. 5, and a case where a 4-yash commision is made is shown in Fig. 6. Fig. 5 In, instruction processing 1 day 1-(4)
When a memory address is sent to bus (1) at time n, it is sent to cashico memory unit l (6) and main memory units 1 to (7) receive it, or cashico memory unit t is sent to bus (1). If data exists at the memory address specified at this time among the multiple memory addresses in ~(6) -C
If there is, that is, if the cache is the same, the cache memory R unit 1-(6) sends the data of 19-t' to the bus (1) at the next clock time n+1. This 19-code data 1. 'i is received by the instruction station Jfake1nit (4). At this point, the data about the cache hit is separately transmitted from the memory 1 to 6 (6) to the main memory 1 to 7, so the data is stored in the main memory 1 (7). However, in the case of a cache miss, the address of z2Z, that is, the cache specified by /l> (6) If there is no data at the specified address, the data at the specified address will be transferred from the main memory 1 unit (7) to the memory address at this time.
t7J1 word middle is read and cached memory 1. ] <i> are transferred and stored in files 1 to (6). Therefore, if a memory address is sent at a key check time n in the instruction processing 71 (1-(4)), as shown in FIG. If (n<m), either 4 words of data or 1 word from main memory 1st day I-(7) is read out automatically at time m+3 and stored in lotus (1). At this time, the first word is sent to the instruction processing unit I (4) and the instruction processing unit 7 [1]
It is taken up by both of the needles 1-(6). Instruction processing] To 1st l (4) has received data, so
The operation based on this data is immediately executed and moved to tJ3.Meanwhile, among the 4 words of data read from the main memory 1 t-(7), the remaining 3 sorted data (from the cache memory 1 t-(7) 6). By the way, at this time, whether the instruction processing (1 to (4)) or the received data is a simple instruction such as a
Instruction processing - 1 day l ~ (4) Axis r1 time m + 1
rThe execution of this instruction is not completed and the clock time m
From +2, it is possible to move on to execution of the next instruction. Therefore, since the execution of the next instruction starts from the clock time m+2, the clock time m+1 before that is 1.
Extract the instruction from Unit 1-(5) and process the instruction.
-(=1> must indicate that the next instruction should be fetched.
Instructions for fetching instructions to 4) are performed via the bus (1) in the same way as data transfer between other conits. However, at clock time m+1, bus 11 main memory]-nit (7) is transferred from the carriage yaw memory unit (
6) is currently in use for transferring data in and out. Therefore, the command retrieval instructions are shown in Figure 7 [1]
You will have to wait until time m+'4. [Problems to be solved by the invention] As mentioned above, the conventional bus control method'("lj,,
If there is a difference in data processing speed between 1 nits connected to the common bus (1), the following processing can be executed even though the speed is 4. However, there is a problem in that the processing speed as a whole is slowed down because it is necessary to wait for 41 bits until the slow 11-nit operation is completed. The present invention has been made to solve these problems, and its purpose is to provide a bus control method that can improve the overall processing speed. The present invention connects a plurality of 77 nits that handle digital information to a common bus, and assigns the use of this bus to each 21 nits in a time-sharing manner, thereby transmitting information between each 77 nits. In a bus control system that performs exchange, there is a bus dividing means for dividing the plurality of q-nilla 1 into a plurality of groups in the middle of the bus, and direction control of transfer information between the divided 1-nito groups. and disconnection control to exchange information between the above-mentioned -] knit groups and between each -] knit phase q. By setting the state in which data can be transferred from one bus to the other bus (or in the opposite direction), the same function as before can be achieved. Then, by setting the bus splitting means so that both buses are disconnected, the same group connected to Hull's bus can be set to , it is also possible to exchange data with other groups connected to the bus (Jru2Nitsu1~comrades). 4 is a diagram showing a certain bus control formula, in contrast to the conventional configuration shown in FIG.
-'Iu device (3) The signal lines (9) and (10) are connected in a row (;f hn. In this embodiment, the bus is divided into two, so the bus (1 ) and bus (2), the number is (=I C-J).
) is shown for one signal line of buses (1) and (2). In Figure 2, the signal lines (1k) and (2k) are the back 11 of the 32 signal lines of the divided buses (1) and (2), respectively.Signal lines (9) and (10) ) are used to set the status of the bus splitting device, and signals for these signal lines are output from the bus control device (ε3). (11)
and (12> is ANI') go 1~, and the bus controller (8) sets the signal line (9) to the value 1'' and also sets the signal line (10
) to the value of ``0'', the signal line (
1k) is now transmitted to the signal line (2k) of the bus (2). Conversely, the signal line (9) is set to '0'', and the signal line (10
) is set to “1”, the signal line (2k) of bus (2)
The information is now transmitted to the signal line (1k) of the bus (1). On the other hand, the bus control device (8) connects the signal line (9) and (10).
) are both set to 1101+, the signal lines (1k) and (2k) of buses (1>, (2) are completely disconnected. Therefore, in this disconnected state, the bus (1k) and (2k) are completely disconnected. > and bus (2) can be used independently for different data transfers. Figure 3 shows the operation of the bus in this embodiment in a time chart 1.
. . . , which corresponds to FIG. 7 used to explain the operation of the conventional system. 4r That is, instruction processing unit 1~(/l
) caused a cache miss when reading memory data, so a block load was performed, and the instruction processing command (4
) is the timer 1~ when the execution of the next instruction is started immediately after receiving the data. In FIG. 3, chips 1 to (4) that process instructions in one working time n output memory addresses to the bus (1). At this time, the signal line (9) is connected to 11111, (10) i,
Since it is set to “0”, the memory address sent to the bus (1) from the other instruction processing unit (4) is sent to the bus (1).
2) (Thus, = 1 = transfer memory 21 nits (6) and main memory l are received at (7). Since this is a case of a cache miss, 4 nits from clock time m [↑memory over 1 nit) The 21-nit (7) outputs the read data to the bus (2)-〇-.In this case, at clock time m, the bus controller (8) outputs the read data to the signal line (9) (also II OII). (10) is set to “1”. For this reason,
This successive data (the first word of block [-1-]) is also transmitted to bus (1) for instruction processing]
) is received (p.
Therefore, at clock time m+1, the instruction is fetched on the bus (1) from the bus (5). Processing 1 An instruction to fetch instructions is given to nodes 1 to (4).In other words, in the conventional timer X7-1 shown in FIG. In this embodiment, the instruction can be issued at the same time as the transfer of the block [1-] code data (or 1 transfer time m+1). , 3[-1] It is now possible to issue an instruction fetch instruction at a faster timing, and as a result, the instruction processing time is -1[-1].
It is possible to overturn the execution of the next command one step faster. For this reason, the processing speed of the entire data processing device! It is possible to improve to 8th stage. Note that the present invention is not limited to the 1-bus configuration as shown in the embodiments, but also applies to devices having a 1-bus configuration in which a common bus is commonly used by a plurality of 1-nits, and there is a competitive relationship when using the common bus. can be applied to all. Further, the number of divisions of the bus is not limited to two, but it is also possible to group one unit with the same operating speed if and divide it into three or more units corresponding to this group. ``Effects of the Invention'' The present invention described above provides bus dividing means for dividing the plurality of units i~ into a plurality of groups in the middle of a bus commonly used by a plurality of units i~. Direction control and separation control of transfer information between unit groups is performed, and information is exchanged between the E1-unit group and each unit group. . Therefore, the bus can be used more efficiently, and the processing speed of the processing device can be significantly improved, which is an excellent effect.

[Brief explanation of the drawing]

Fig. 1 is a block diagram showing a bus division system according to an embodiment of the present invention, Fig. 2 is a diagram showing the structure of a bus dividing device similar to Fig. Figure 4 is a configuration diagram showing an example of a device using the conventional bus control method, and Figures 5 to 7 show the operation of the embodiment shown in Figure 1. -1. (1), (2)...bus, (3)...bus division device, (4)...instruction processing unit, (5)...instruction fetching unit 1~ , (6)...-1=Year memory'
JInits]~, (7)...Main memory -1-nits, (
ε3)...Bus control unit, (9), (10
)...Ikichi line, (11), (12)...
AND game 1~. B1. In each figure, the same number indicates the same or equivalent part. Procedural amendment to - (voluntary) Shofu, 6), J month 13th

Claims (1)

[Claims] In a bus control method in which multiple units that handle digital information are connected to a common bus, and the right to use the bus is given to each unit in a time-sharing manner to exchange information between the units, the multiple units A bus dividing means is provided for dividing the units into a plurality of groups, and the direction control and separation control of transfer information is performed between the divided unit groups, and information is exchanged between the unit groups and each unit. A bus control method characterized by