JPH06301641A - Electronic computer - Google Patents

Abstract

PURPOSE:To provide an electronic computer capable of reducing the load of a CPU due to data transfer and efficiently utilizing the CPU. CONSTITUTION:In the case of transferring data of 64 bits from the CPU 2 to a memory 4, the 64-bit data are outputted from the CPU 2 in each 32 bits corresponding to each access through data buses 40, 42 and stored in respective data registers 10, 12. Respective 32-bit data are successively outputted to the memory 4 through a data bus 32 by two accesses. Since the CPU 2 having 64-bit I/O data width can complete data output processing to the memory 4 having 32-bit I/O data width by accessing a function attaining circuit 3 only once, the load of the CPU 2 due to data transfer processing can be reduced.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION In the present invention, since the CPU and the memory have different data widths that can be simultaneously input and output, the CP
The present invention relates to an electronic computer that can effectively prevent U from being exclusively used for memory access processing for a long time and can efficiently use a CPU.

[0002]

2. Description of the Related Art In a conventional electronic computer, a central processing unit (CPU) is connected to a memory via a bus. This bus is composed of, for example, a control bus for transferring control signals, an address bus for transferring address data, and a data bus for transferring data. When the CPU stores the calculation result in the memory,
The control signal indicating writing, the data, and the address data indicating the address of the memory for storing the data are output to the memory via the bus. The memory stores the data at the address indicated by the address data when the signal and the data are input from the CPU.

On the other hand, when reading the stored information from the memory, the CPU outputs a control signal indicating reading and address data indicating an address at which the memory is read to the memory via the bus. When the memory inputs the above-mentioned signal and address data from the CPU, the memory outputs the data stored at the address indicated by the address data to the CPU.
Usually, the CPU and memory, depending on their type,
The data width that can be input and output at the same time is specified. For example, if the data width of the CPU and the data width of the memory are the same, the data transfer between the CPU and the memory is completed by one access.

[0004]

However, the CP to be used
Depending on the standard of U and the memory, the data width of the CPU and the data width of the memory may be different. In this case, the data transfer between the CPU and the memory may not be completed by one access, and may require multiple accesses. For example, when the data width of the CPU is 32 bits and the data width of the memory is 16 bits, and the CPU outputs the 32-bit data to the memory via the data bus, the CPU outputs the 32-bit data in 16-bit units. Therefore, it is necessary to output the data to the memory in two steps, and the CPU accesses the memory twice in one data transfer.

As described above, when the data width of the CPU is wider than the data width of the memory, due to the hardware limitation on the memory side, the CPU executes a time-consuming memory access multiple times in one data transfer. Needing more time, which increases the time the CPU is used for the data transfer process. These are problematic from the viewpoint of efficient use of expensive CPUs.

On the other hand, when the data width of the CPU is narrower than the data width of the memory, the CPU must inevitably access the memory a plurality of times due to the hardware limitation on the CPU side. At this time, the memory accessed by the CPU is usually connected to the CPU via an interface circuit or the like, the communication path with the CPU is long, and the access speed is slow. Therefore, the CPU is used for a long time for data transfer processing, which is problematic from the viewpoint of efficient use of an expensive CPU. Also, CPU and CPU
CPU with a wide data width in data transfer between
However, there is a problem in that it is occupied for a long time in data transfer processing with a CPU having a narrow data width.

The present invention has been made in view of the above-mentioned problems of the prior art, and an object of the present invention is to provide an electronic computer capable of reducing the processing load of the CPU due to the data transfer and efficiently utilizing the CPU. .

[0008]

In order to solve the above problems and achieve the above objects, the computer of the present invention is
Data transfer between the arithmetic control means and the logic processing means having a data width different from that of the arithmetic control means is performed via the function realizing means for adjusting the data width.

In the electronic computer of the present invention, data having a data width corresponding to the data output width of the arithmetic control means and the logic processing means is input, and the input data is output as the data. It has a function realizing means for adjusting the data width so as to correspond to the data input width of the logic processing means and the arithmetic control means, and outputting the adjusted data to the logic processing means and the arithmetic control means. .

Further, the arithmetic control means of the electronic computer of the present invention has, for example, a data input / output width wider than that of the logic processing means, and the function realizing means is
Inputting / outputting data to / from the arithmetic control unit is performed by one access, and inputting / outputting data to / from the logical processing unit is performed by plural accesses according to the data input / output width of the logical processing unit.

Further, the arithmetic control means of the electronic computer of the present invention has, for example, a data input / output width narrower than the data input / output width of the logic processing means, and the function realizing means is the arithmetic control means. The data input / output is executed by a plurality of accesses according to the data input / output width of the arithmetic control means, and the data input / output by the logic processing means is executed by a single access.

Also, in the electronic computer of the present invention, after the data output processing from the arithmetic control means to the function realizing means is completed, the arithmetic processing in the arithmetic control means and the function realizing means to the storage circuit are completed. Performs data output processing in parallel.

The logical processing means of the electronic computer of the present invention is, for example, arithmetic control means.

The logical processing means of the electronic computer of the present invention is, for example, storage means.

Further, the electronic computer of the present invention has, for example, a plurality of the function realizing means, and while one function realizing means is executing the processing, the arithmetic control means does not execute the processing. Other function implementing means can be accessed.

[0016]

In the electronic computer of the present invention, for example, the data having the data width corresponding to the data output width is output from the arithmetic control means to the function realizing means. Then, the function realizing means adjusts the input data to data according to the data input width of the logic processing means to be output, and the adjusted data is output to the logic processing means. At this time, for example, when the data output width of the arithmetic control means is wider than the data input width of the logic processing means, the data from the arithmetic control means is output to the function realizing means by one access, and the input data is The data is divided into a plurality of data according to the data input width of the logic processing means, and the plurality of divided data are output to the logic processing means by a plurality of accesses.

[0017]

EXAMPLE A first example will be described. FIG. 1 shows a configuration diagram of a memory peripheral portion in the electronic computer of this embodiment.
As shown in FIG. 1, in the memory peripheral portion, the function realizing circuit 3 is arranged between the CPU 2 and the memory 4. The function realizing circuit 3 includes an address register 8, a data register 10,
12 and memory 6. The CPU 2 has a data width of 32 bits and can simultaneously input / output 32-bit data. The memory 4 has a data width of 64 bits and can simultaneously input / output 64-bit data.

The CPU 2 and the address register 8 are connected, for example, by a 16-bit address bus 20, and the address register 8 and the memory 4 are connected by a 16-bit address bus 22. Further, the CPU 2 is connected to the data register 10 and the data register 12 by a 32-bit data bus 24, and the data registers 10 and 12 and the memory 4 are connected by a 32-bit data bus 26 and 28. Further, the controller 6, the address register 8 and the data registers 10 and 12, the CPU 2 and the memory 4 are connected by control lines 30, 32 and 34.

The CPU 2, for example, performs arithmetic processing according to the contents of a program created in advance, and when using the data stored in the memory 4 in the arithmetic processing,
A control signal indicating reading is output to the controller 6 via the control line 32. Further, the CPU 2 outputs address data to the address register 8 via the address bus 20 at the same time, for example. After that, the CPU 2 sends the data register 1 from the controller 6 via the control line 32.
When the control signal indicating that the data reading into 0 and 12 is completed is input, the data stored in the data registers 10 and 12 are read.

When the CPU 2 stores the created data in the memory 4 as a result of the arithmetic processing, the control line 32
A control signal indicating writing is output to the controller 6 via. Further, the CPU 2 outputs, for example, address data indicating an address on the memory 4 for storing data simultaneously to the address register 8 via the address bus 20 and the data to the data registers 10 and 12 via the data bus 24. Output.

The controller 6 includes a CPU 2 and a control line 3
When a control signal indicating reading is input via 2, a control signal indicating outputting address data to the memory 4 is output to the address register 8 via the control line 30. At the same time, the controller 6 inputs a control signal indicating reading into the memory 4 via the control line 34. Then, the controller 6 outputs a control signal indicating the completion of writing to the CPU 2 via the control line 32 at the timing when the process of writing the predetermined data from the memory 4 into the data registers 10 and 12 is completed.

Further, when the control signal indicating the writing is input from the CPU 2 via the control signal 32, the controller 6 outputs the address data to the memory 4 at the timing according to the content indicated by the control signal. A control signal indicating that the control signal is output to the address register 8 and a control signal indicating that data is output to the memory 4 is output to the data registers 10 and 11.
Output to each. At the same time, controller 6
Outputs a control signal indicating writing to the memory 4 via the control line 34. For example, when the CPU 2 writes 64-bit data to the memory 4, the 64-bit data is output to the data bus 24 from the CPU 2 in two 32-bit units, and the 64-bit data is output to the data register 1 respectively.
It is stored in 0 and 12. At this time, when the CPU 2 writes data to the data registers 10 and 12 in one clock cycle, the controller 6 outputs the control signal to the address register 8 at the above timing.
2 clock cycles after the timing when the control signal is input from the CPU 2 via the control line 32.

As the memory 4, for example, a MOS type semiconductor memory is used.

Address register 8 and data register 1
As 0 and 12, for example, a bipolar semiconductor memory is used, which enables faster access than the memory 4. Further, if these registers and the CPU are manufactured as a single chip, it is possible to access at a higher speed. The address register 8 has a storage capacity of 16 bits, for example, and outputs address data to the memory 4 in response to a control signal from the controller 6.

The data registers 10 and 12 are, for example,
It has a storage capacity of 32 bits and outputs data to the CPU 2 or the memory 4 in response to a control signal from the controller 6.

The operation of writing 64-bit data from the CPU 2 to the memory 4 will be described below. From CPU2
A control signal indicating writing is output to the controller 6 via the control line 32. At the same time, from CPU2,
The address data is output to the address register 8 via the address bus 20. Moreover, at the same time, the CPU
From 2 to 64, the upper 32 bits of 64-bit data are output to the data register 10 via the data bus 24.

Thereafter, the CPU 2 outputs the lower 32 bits of the 64-bit data to the data register 12 via the data bus 24. Since the access speed from the CPU 2 to the data registers 10 and 12 is higher than the access speed to the memory 4,
The output time of data from the CPU 2 to the data registers 10 and 12 depends on the CPU in the electronic computer described in the prior art.
It is short compared with the output time of data from memory to memory. Therefore, the CPU 2 can release the data of the lower 32 bits of 64 bits to the data bus and then can be released from the data output processing and perform other processing, and the CPU can be efficiently used.

Data from the CPU 2 is the data register 1
When stored in 2, the control signal is output from the controller 6 to the address register 8 and the data registers 10 and 12 via the control line 30. At the same time, a control signal indicating writing is output from the controller 6 to the memory 4 via the control line 34.

Then, the address data is output from the address register 8 to the memory 4 via the address bus 22. Further, data is output from the data registers 10 and 12 to the memory 4 via the data bus.

Data (6 bits) composed of data (32-bit data) from the data registers 10 and 12
4-bit data) is stored in the address of the memory 4 designated by the address data from the address register 8.

The operation when the CPU 2 reads the 64-bit data stored in the memory 4 will be described below. CP
A control signal indicating reading is output from U2 to the controller 6 via the control line 32. At the same time, C
Address data is output from the PU 2 to the address register 8 via the address bus 20.

From the controller 6, a control signal indicating writing is output to the memory 4 via the control line 34, and a control signal is output to the address register 8 via the control line 30.

Then, the address data is output to the memory 4 via the address bus. When the control signal from the controller 6 and the address data from the address register 8 are input to the memory 4, for example, the upper 32 of the data (64-bit data) stored at the address indicated by the address data is input. Bit data is output to the data register 10 via the data bus 26, and lower 32 bits of data are output to the data register 12 via the data bus 28.

Then, a control signal indicating the completion of writing to the data registers 10 and 12 is sent to the CPU 2 via the control line 32.
Is output to. When this control signal is input to the CPU2, if other processing is being executed, the processing is interrupted, and, for example, the data (32-bit data) first stored in the data register 10 by the CPU2.
Are read in via the data bus 24.

Thereafter, the CPU 2 reads the data (32-bit data) stored in the data register 12 via the data bus 24.

At this time, as described above, since the CPU 2 accesses the data registers 10 and 12 at high speed, the time from the output of the read signal to the controller 6 to the acquisition of the data has been described in the prior art. It is shorter than that of the electronic computer, and the time spent for the data reading process of the CPU can be shortened.

The second embodiment will be described. FIG. 2 shows a configuration diagram of a memory peripheral portion in the electronic computer of this embodiment. In FIG. 2, the parts assigned the same numbers as in FIG. 1 are the same as the parts in FIG. In this embodiment, the data width of the CPU 2 is longer than that of the memory 4, the data width of the CPU 2 is 64 bits, and the data width of the memory 4 is 32 bits.

The case of writing 64-bit data from the CPU 2 to the memory 4 will be described. The upper 32 bits of the 64-bit data are output to the data register 10 via the data bus 40. At the same time,
Of the 64-bit data, the lower 32-bit data is output to the data register 12 via the data bus 42.

Then, based on the control signal from the controller 6, for example, the data first stored in the data register 10 is output to the memory 4 via the data bus 44.

Thereafter, the data stored in the data register 12 is output to the memory 4 via the data bus 44.

As described above, in the electronic computer of this embodiment,
Even when the data width of the memory 4 is shorter than the data width of the CPU 2, it is not necessary to divide the data into a plurality of times and output the data to the memory as in the electronic computer described in the prior art. The data transfer process can be ended by outputting the data twice, and then the process can be shifted to another process.

A case where the CPU 2 reads 64-bit data from the memory 4 will be described. A control signal indicating the reading of data is output from the CPU 2 to the controller 6.

Then, a control signal is output from the controller 6 to the memory 4 and the data registers 10 and 12, and among the 64-bit data stored in the memory 4, the upper 32-bit data is first transferred via the data bus 44 to the data bus 44. The data is output to the register 10 and then the lower 32 bits of data are output to the data register 12 via the data bus 44.

Then, the controller 6 outputs a control signal indicating completion of data transfer to the CPU 2. CP
When U2 receives a control signal indicating completion of data transfer from the controller 6, when U2 is executing another process,
The process is interrupted and the 32-bit data stored in the data registers 10 and 12 are read simultaneously.

At this time, as described in the first embodiment, C
Since the access to the data registers 10 and 12 of the PU 2 is faster than the access to the memory 4, the time spent for the data reading process of the CPU 2 is shortened as compared with the electronic computer described in the related art. can do.

The third embodiment will be described. FIG. 3 shows a block diagram of a memory peripheral portion in the electronic computer of this embodiment. As shown in FIG. 3, in the computer of this embodiment, C
The PU 2 is connected to the memory 4 via the function realizing circuits 3a and 3b arranged in parallel. Similar to the case of the second embodiment described above, the CPU 2 has an input / output data width of 64 bits, and the memory 4 has an input / output data width of 32 bits. The function realizing circuits 3a and 3b are the same as the function realizing circuit 3 described above, and share the 16-bit address bus 5
C via 2- and 32-bit data buses 58, 64
Address buses 56 and 3 which are connected to and share PU2
It is connected to the memory 4 via a 2-bit data bus 62.

By providing the two function realizing circuits 3a and 3b, for example, the CPU 2 outputs an access instruction such as a data reading instruction or a writing instruction to the memory 4 via the function realizing circuit 3a, and thereafter. Even if the data transfer processing between the function realizing circuit 3a and the memory 4 is not completed, it is possible to output the data access instruction to the memory 4 again via the function realizing circuit 3b.

That is, the memory 4 is usually an internal memory of a peripheral device and is connected to the function realizing circuits 3a and 3b via an interface circuit or the like, and the function realizing circuits 3a and 3b are connected.
The data transfer speed between the memory 4 and the memory 4 is slower than the data transfer speed between the CPU 2 and the function realizing circuits 3a and 3b.
Therefore, when the CPU 2 accesses the memory 4 again, there may be a case where the previous data transfer process between the function realizing circuits 3a and 3b and the memory 4 is not completed, but the two function realizing circuits 3a. , 3b, the C
PU2 does not wait for the end of the data transfer process being executed,
Function implementation circuits 3a and 3b that do not perform data transfer processing
Can be accessed, and the processing of the CPU 2 can be prevented from stopping.

As described above, in the electronic computer of this embodiment,
Even if the CPU 2 outputs the access instruction to the memory 4 last time and then outputs the access instruction again at a very short interval, it is not necessary to stop the processing of the CPU 2 and the expensive CPU 2 can be efficiently used. Can be achieved.

The electronic computer of the present invention is not limited to the above embodiment. The data width for inputting / outputting the CPU 2 and the memory 4 is arbitrary. For example, even when the data widths have the same length, the CPU 2 spends data writing processing by using the electronic computer of the present invention. The time can be shortened. Further, the data register 10 is a CPU
2 and the data width of the memory 4 can be changed.

Further, in the above-described embodiment, the controller 6 outputs the control signal to the CPU 2 and the memory 4 to transfer the data stored in the data registers 10 and 12 to the CPU 2 and the memory 4. However, the controller 6 may not be provided, and the data stored in the data registers 10 and 12 may be transferred to the CPU 2 and the memory 4 based on the control signal from the CPU 2. Further, instead of the memory 4, a CPU may be connected and data transfer between the CPU 2 and the CPU may be adjusted by the function realizing circuit. In addition, the above-mentioned third
Although a case has been described with the embodiment where two function realizing circuits are provided in parallel, a larger number of function realizing circuits may be provided in parallel.

[0052]

According to the electronic computer of the present invention, the arithmetic control means, when performing the data transfer processing with the logical processing means, regardless of the data input / output width of the logical processing means, the arithmetic control means itself has data. Data can be input / output within the input / output width, and the load on the arithmetic control unit associated with the data transfer processing can be reduced. Further, according to the electronic computer of the present invention, the arithmetic control means can execute the data transfer with the logical processing means by, for example, accessing the function realizing means capable of high-speed access. Can reduce the time spent for data transfer processing. Further, according to the electronic computer of the present invention, the arithmetic control unit can access another function realizing unit even when one function realizing unit is executing the data transfer process with the storage circuit. The calculation means is multiple times at short time intervals,
Even when accessing the memory circuit, the arithmetic control means can access the function realizing means without waiting time.

[Brief description of drawings]

FIG. 1 is a configuration diagram of an electronic computer according to a first embodiment.

FIG. 2 is a configuration diagram of an electronic computer according to a second embodiment.

FIG. 3 is a configuration diagram of an electronic computer according to a third embodiment.

[Explanation of symbols]

2 ... CPU 3, 3a, 3b ... Function realizing means 4 ... Memory 6 ... Controller 8 ... Address register 10, 12 ... Data register 20, 22, 52, 56 ... Address bus 24, 26, 28, 40, 42, 44 ... Data bus 58, 64, 62 ... Data bus 10, 30, 32, 32a, 32b, 34, 34a, 3
4b ... Control line

Claims (8)

[Claims] 1. An electronic computer for performing data transfer between operation control means and logic processing means having a data width different from that of the operation control means, wherein the data output from the operation control means and the logic processing means. Inputting data having a data width according to the width, adjusting the data width so that the input data corresponds to the data input width of the logic processing means and the arithmetic control means for outputting the data, and adjusting the data width. An electronic computer having a function realizing means for outputting the processed data to the logic processing means and the arithmetic control means. 2. The arithmetic control means has a data input / output width wider than the data input / output width of the logic processing means, and the function realizing means performs data input / output once with the arithmetic control means. 2. The electronic computer according to claim 1, wherein the computer is executed by access, and data input / output with the logical processing unit is executed by a plurality of accesses according to a data input / output width of the logical processing unit. 3. The arithmetic control means has a data input / output width narrower than the data input / output width of the logic processing means, and the function realizing means performs the data input / output with the arithmetic control means by the arithmetic operation. 2. The electronic computer according to claim 1, wherein the computer is executed by a plurality of accesses according to the data input / output width of the control means, and the data input / output with the logical processing means is executed by a single access. 4. After the data output processing from the arithmetic control means to the function realizing means is completed, the arithmetic processing in the arithmetic control means and the data output processing from the function realizing means to the memory circuit are performed in parallel. The electronic computer according to any one of claims 1 to 3, which is performed. 5. The electronic computer according to claim 1, wherein the logic processing means is arithmetic control means. 6. The electronic computer according to claim 1, wherein the logical processing means is a storage means. 7. A plurality of function implementing means are provided, and while one function implementing means is executing the processing, the arithmetic control means accesses another function implementing means not executing the processing. The electronic computer according to claim 1, which is possible. 8. A data transfer speed between the arithmetic control means and the function realizing means is higher than a data transfer speed between the function realizing means and the logic processing means.
The electronic calculator according to any one of to 7.