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JPS5625831A - Logic circuit - Google Patents

Logic circuit

Info

Publication number
JPS5625831A
JPS5625831A JP10195379A JP10195379A JPS5625831A JP S5625831 A JPS5625831 A JP S5625831A JP 10195379 A JP10195379 A JP 10195379A JP 10195379 A JP10195379 A JP 10195379A JP S5625831 A JPS5625831 A JP S5625831A
Authority
JP
Japan
Prior art keywords
output
fed
turn
low level
input terminal
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP10195379A
Other languages
Japanese (ja)
Inventor
Yoji Hirano
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Nippon Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp, Nippon Electric Co Ltd filed Critical NEC Corp
Priority to JP10195379A priority Critical patent/JPS5625831A/en
Publication of JPS5625831A publication Critical patent/JPS5625831A/en
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/02—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components
    • H03K19/08—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using semiconductor devices
    • H03K19/082—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using semiconductor devices using bipolar transistors
    • H03K19/091—Integrated injection logic or merged transistor logic
    • H03K19/0917—Multistate logic

Landscapes

  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Computing Systems (AREA)
  • General Engineering & Computer Science (AREA)
  • Mathematical Physics (AREA)
  • Logic Circuits (AREA)

Abstract

PURPOSE:To improve the turn-on characteristics by feeding back the output of the output circuit of totem pole type to the input of the said output circuit via the diode transistor. CONSTITUTION:When a high level is applied to the output state control input terminal 5 and low level is applied to either one of the input terminals 3 and 4, the transistor Q1 is on and Q2, Q6 are off. Accordingly, Q3 is off. When high level is applied to the input terminals 3, 4, since Q1 is off, Q2, Q6 are on. The emitter current of Q5 is fed to the base of Q3 through the diodes D5, Q6 until the base voltage of Q5 is lowered with a slight delay and Q5 is off, and the turn-on characteristics of Q3 is improved. With the control input terminal 5 fed with a low level, Q3, Q5 are off and the output of high impedance can be obtained.
JP10195379A 1979-08-10 1979-08-10 Logic circuit Pending JPS5625831A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP10195379A JPS5625831A (en) 1979-08-10 1979-08-10 Logic circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP10195379A JPS5625831A (en) 1979-08-10 1979-08-10 Logic circuit

Publications (1)

Publication Number Publication Date
JPS5625831A true JPS5625831A (en) 1981-03-12

Family

ID=14314242

Family Applications (1)

Application Number Title Priority Date Filing Date
JP10195379A Pending JPS5625831A (en) 1979-08-10 1979-08-10 Logic circuit

Country Status (1)

Country Link
JP (1) JPS5625831A (en)

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS58183918A (en) * 1982-04-16 1983-10-27 ジエルマン・サイエンシス・インコ−ポレ−テツド Disposable filter apparatus
WO1984001066A1 (en) * 1982-09-10 1984-03-15 Advanced Micro Devices Inc High-speed schottky ttl gate apparatus
US4486674A (en) * 1983-07-05 1984-12-04 Motorola, Inc. Three state gate having enhanced transition to an active low
US4661727A (en) * 1984-07-19 1987-04-28 Fairchild Semiconductor Corporation Multiple phase-splitter TTL output circuit with improved drive characteristics

Cited By (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS58183918A (en) * 1982-04-16 1983-10-27 ジエルマン・サイエンシス・インコ−ポレ−テツド Disposable filter apparatus
JPS6056525B2 (en) * 1982-04-16 1985-12-10 ジエルマン・サイエンシス・インコ−ポレ−テツド disposable filter device
WO1984001066A1 (en) * 1982-09-10 1984-03-15 Advanced Micro Devices Inc High-speed schottky ttl gate apparatus
US4521699A (en) * 1982-09-10 1985-06-04 Advanced Micro Devices, Inc. High-speed schottky TTL gate apparatus
US4486674A (en) * 1983-07-05 1984-12-04 Motorola, Inc. Three state gate having enhanced transition to an active low
US4661727A (en) * 1984-07-19 1987-04-28 Fairchild Semiconductor Corporation Multiple phase-splitter TTL output circuit with improved drive characteristics

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