JPH03263897A - Packaging of hybrid integrated circuit - Google Patents
Packaging of hybrid integrated circuitInfo
- Publication number
- JPH03263897A JPH03263897A JP6092090A JP6092090A JPH03263897A JP H03263897 A JPH03263897 A JP H03263897A JP 6092090 A JP6092090 A JP 6092090A JP 6092090 A JP6092090 A JP 6092090A JP H03263897 A JPH03263897 A JP H03263897A
- Authority
- JP
- Japan
- Prior art keywords
- integrated circuit
- hybrid integrated
- bonding wire
- signal terminal
- connection point
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 238000004806 packaging method and process Methods 0.000 title abstract 2
- 239000000758 substrate Substances 0.000 claims abstract description 14
- 239000002184 metal Substances 0.000 claims description 52
- 229910052751 metal Inorganic materials 0.000 claims description 52
- 229910000679 solder Inorganic materials 0.000 claims description 16
- 238000000034 method Methods 0.000 claims description 15
- 239000000463 material Substances 0.000 claims description 13
- 239000003990 capacitor Substances 0.000 claims description 6
- 238000003303 reheating Methods 0.000 claims description 3
- 238000010438 heat treatment Methods 0.000 claims description 2
- 230000005540 biological transmission Effects 0.000 abstract description 8
- 230000002542 deteriorative effect Effects 0.000 abstract 1
- 238000010586 diagram Methods 0.000 description 8
- 238000005452 bending Methods 0.000 description 6
- 238000007796 conventional method Methods 0.000 description 4
- 230000006866 deterioration Effects 0.000 description 4
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 description 3
- 229910052802 copper Inorganic materials 0.000 description 3
- 239000010949 copper Substances 0.000 description 3
- 238000005476 soldering Methods 0.000 description 3
- 239000011521 glass Substances 0.000 description 2
- 239000000565 sealant Substances 0.000 description 2
- PNEYBMLMFCGWSK-UHFFFAOYSA-N aluminium oxide Inorganic materials [O-2].[O-2].[O-2].[Al+3].[Al+3] PNEYBMLMFCGWSK-UHFFFAOYSA-N 0.000 description 1
- 239000004020 conductor Substances 0.000 description 1
- 238000006073 displacement reaction Methods 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 238000005457 optimization Methods 0.000 description 1
- 229910052709 silver Inorganic materials 0.000 description 1
- 239000004332 silver Substances 0.000 description 1
- 239000010409 thin film Substances 0.000 description 1
- 238000003466 welding Methods 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
- H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
Landscapes
- Mounting Of Printed Circuit Boards And The Like (AREA)
Abstract
Description
【発明の詳細な説明】
概要
混成集積回路の実装方法に関し、
実装に際してボンディングワイヤが断線する恐れがなく
、しかもワイヤボンディングによる伝送特性の劣化が少
ない混成集積回路の実装方法の提供を目的とし、
端子側マイクロストリップ線路が形成された誘電体ブロ
ックからなる信号端子が縁部に設けられた金属パッケー
ジ基台を加熱して、該金属パ・ソケージ基台の平坦面上
に、集積回路側マイクロストリップ線路が形成された誘
電体基板を備えた混成集積回路を半田材により固着する
第1の工程と、上記端子側マイクロス) +Jツブ線路
と上記集積回路側マイクロストリップ線路とをワイヤボ
ンディング接続する第2の工程と、上記金属パッケージ
基台を再加熱する第3の工程とをこの順に含んでなる混
成集積回路の実装方法において、上記第2の工程におけ
る上記信号端子側のボンディングワイヤ接続点が上記混
成集積回路側のボンディングワイヤ接続点よりも高い位
置にあるようにして構成する。[Detailed Description of the Invention] Summary Regarding a method for mounting a hybrid integrated circuit, the present invention aims to provide a method for mounting a hybrid integrated circuit in which there is no risk of bonding wires being disconnected during mounting, and in which transmission characteristics are less likely to deteriorate due to wire bonding. A metal package base having a signal terminal formed on the edge thereof, which is made of a dielectric block on which a side microstrip line is formed, is heated, and the integrated circuit side microstrip line is placed on the flat surface of the metal package base. A first step of fixing a hybrid integrated circuit having a dielectric substrate formed with a dielectric substrate with a solder material, and a second step of connecting the +J tube line and the microstrip line on the integrated circuit side by wire bonding. and a third step of reheating the metal package base in this order, wherein the bonding wire connection point on the signal terminal side in the second step is connected to the hybrid integrated circuit. It is configured to be located at a higher position than the bonding wire connection point on the integrated circuit side.
産業上の利用分野
本発明はマイクロ波、ミリ波周波数帯の無線装置に使用
される混成集積回路の実装方法に関する。INDUSTRIAL APPLICATION FIELD The present invention relates to a method for mounting a hybrid integrated circuit used in radio equipment in microwave and millimeter wave frequency bands.
近年、マイクロ波、ミリ波周波数帯の無線装置において
は、装置の小型化、汎用性の拡大、低価格化、高信頼性
化等の要望により、マイクロ波集積回路(MIC)が広
く使用されるようになっている。マイクロ波集積回路は
一般的に混成集積回路として提供される。ここで、混成
集積回路とは、能動及び/又は受動素子(受動素子には
導体パターンの形状により機能するようにされたものが
含まれる。)が誘電体基板上に一体的に設けられた回路
部品をいう。この種の混成集積回路を使用するに際して
、その実装方法の最適化が模索されている。In recent years, microwave integrated circuits (MICs) have been widely used in wireless devices in the microwave and millimeter wave frequency bands due to demands for smaller devices, greater versatility, lower prices, higher reliability, etc. It looks like this. Microwave integrated circuits are generally provided as hybrid integrated circuits. Here, a hybrid integrated circuit is a circuit in which active and/or passive elements (passive elements include those made to function by the shape of a conductor pattern) are integrally provided on a dielectric substrate. Refers to parts. When using this type of hybrid integrated circuit, optimization of its mounting method is being sought.
従来の技術及び発明が解決しようとする課題第6図によ
り混成集積回路の従来の実装方法及びこの方法における
問題点を説明する。まず、第6図(a)に示すように、
信号端子2が縁部に設けられた金属パッケージ基台4を
加熱して、この金属パッケージ基台4上に混成集積回路
6を半田材8により固着する。このとき、混成集積回路
6の端部と金属パッケージ基台4との間には、この図で
は図示しない枠部材を金属パッケージ基台4にろう付は
接合するときの温度履歴等によって、10〜30μm程
度の隙間S、が生じているのが通例である。次いで、金
属パッケージ基台4等が常温程度にまで冷却したならば
、第6図(b)に示すように、信号端子2上の端子側マ
イクロストリップ線路と混成集積回路6上の集積回路側
マイクロストリップ線路とをボンディングワイヤ10を
用いてワイヤボンディング接続する。金属パッケージ基
台4等が室温程度にまで冷却すると、半田材8が固化す
る温度と室温の差及び、混成集積回路60線熱膨張係数
と金属パッケージ基台4の線熱膨張係数の差に起因して
所謂バイメタル効果が現れ、混成集積回路6も金属パッ
ケージ基台4と同じ方向に湾曲し、その端部の湾曲前の
位置からの変形両はΔS(例えば20〜40μm)とな
る。このときの混成集積回路6の端部と金属パッケージ
基台4との間の隙間はSI と同程度の82 である
。PRIOR ART AND PROBLEMS TO BE SOLVED BY THE INVENTION A conventional method for mounting a hybrid integrated circuit and problems in this method will be explained with reference to FIG. First, as shown in Figure 6(a),
A metal package base 4 having signal terminals 2 provided at its edges is heated, and a hybrid integrated circuit 6 is fixed onto the metal package base 4 with a solder material 8. At this time, the gap between the end of the hybrid integrated circuit 6 and the metal package base 4 varies from 10 to Usually, a gap S of about 30 μm is created. Next, once the metal package base 4 and the like have been cooled to around room temperature, as shown in FIG. 6(b), the terminal side microstrip line on the signal terminal 2 and the integrated circuit side microstrip line on the hybrid integrated circuit 6 are A wire bonding connection is made between the strip line and the strip line using a bonding wire 10. When the metal package base 4 etc. is cooled to about room temperature, the solder material 8 solidifies due to the difference between the temperature at which it solidifies and the room temperature, and the difference between the coefficient of linear thermal expansion of the hybrid integrated circuit 60 and the coefficient of linear thermal expansion of the metal package base 4. As a result, a so-called bimetal effect appears, and the hybrid integrated circuit 6 also curves in the same direction as the metal package base 4, and the deformation of the end portion from the position before the curve becomes ΔS (for example, 20 to 40 μm). At this time, the gap between the end of the hybrid integrated circuit 6 and the metal package base 4 is 82, which is about the same as SI.
ところで、混成集積回路6の強度特性を決定している誘
電体基板は塑性変形し難い。これに対して、無酸素銅等
からなる金属パッケージ基台4は塑性変形し易い。この
ため、第6図(b)に示した状態における内部応力は経
時的に緩和される方向にある。しかしながら、この内部
応力は零にまではならないから、例えば、気密封止のだ
袷の蓋部材を金属パッケージ基台4に半田材により固着
するために金属パッケージ基台4を再加熱して半田材8
が再溶融すると、弾性変形していた混成集積回路6は元
の形状に復元するが、塑性変形及び弾性変形していた金
属パッケージ基台4は元の形状にまで復元しない。従っ
て、半田材8が再溶融すると、混成集積回路6の端部と
金属パッケージ基台4との間には、S2よりも大きい例
えば20〜60μm程度の隙間S3 が生じることにな
る。このように大きな隙間が生じると、ボンディングワ
イヤ10が伸びたり、最悪の場合第6図(C)に示すよ
うにボンディングワイヤ10が切断することになる。By the way, the dielectric substrate that determines the strength characteristics of the hybrid integrated circuit 6 is difficult to be plastically deformed. On the other hand, the metal package base 4 made of oxygen-free copper or the like is easily plastically deformed. Therefore, the internal stress in the state shown in FIG. 6(b) tends to be relaxed over time. However, since this internal stress does not reach zero, for example, in order to fix the lid member of the hermetically sealed sleeve to the metal package base 4 with solder, the metal package base 4 is reheated and the solder is applied. 8
When the metal package base 4 is remelted, the elastically deformed hybrid integrated circuit 6 is restored to its original shape, but the plastic and elastically deformed metal package base 4 is not restored to its original shape. Therefore, when the solder material 8 is remelted, a gap S3 of, for example, about 20 to 60 μm, which is larger than S2, will be created between the end of the hybrid integrated circuit 6 and the metal package base 4. If such a large gap occurs, the bonding wire 10 will stretch, or in the worst case, the bonding wire 10 will break as shown in FIG. 6(C).
このボンディングワイヤの伸び、断線を防止するために
、予めボンディングワイヤが長くなるようにワイヤボン
ディングすることが提案され得るが、こうすると伝送線
路の特性インピーダンスが変化して高周波特性等が劣化
することがある。In order to prevent the bonding wire from elongating and breaking, it may be proposed to perform wire bonding so that the bonding wire is long in advance, but this may change the characteristic impedance of the transmission line and cause deterioration of high frequency characteristics, etc. be.
本発明はこのような技術的課題に鑑みて創作されたもの
で、実装に際してボンディングワイヤが伸びたり断線す
る恐れがなく、しかもワイヤボンディングによる伝送特
性の劣化が少ない混成集積回路の実装方法の提供を目的
としている。The present invention was created in view of these technical problems, and an object of the present invention is to provide a method for mounting a hybrid integrated circuit in which there is no risk of bonding wires being stretched or disconnected during mounting, and in which transmission characteristics are less likely to deteriorate due to wire bonding. The purpose is
課題を解決するための手段
上述した技術的課題を解決するた必になされた本発明方
法は、端子側マイクロストリップ線路が形成された誘電
体ブロックからなる信号端子が縁部に設けられた金属パ
ッケージ基台を加熱して、該金属パッケージ基台の平坦
面上に、集積回路側マイクロストリップ線路が形成され
た誘電体基板を備えた混成集積回路を半田材により固着
する第1の工程と、上記端子側マイクロストリップ線路
と上記集積回路側マイクロストリップ線路とをワイヤボ
ンディング接続する第2の工程と、上記金属パッケージ
基台を再加熱する第3の工程とをこの順に含んでなる混
成集積回路の実装方法に適用するものである。Means for Solving the Problems The method of the present invention, which was made in order to solve the above-mentioned technical problems, is a metal package having a signal terminal provided at its edge, which is made of a dielectric block on which a terminal-side microstrip line is formed. a first step of heating the base and fixing the hybrid integrated circuit including the dielectric substrate on which the microstrip line on the integrated circuit side is formed on the flat surface of the metal package base with a solder material; Mounting of a hybrid integrated circuit comprising, in this order, a second step of connecting the terminal side microstrip line and the integrated circuit side microstrip line by wire bonding, and a third step of reheating the metal package base. It applies to methods.
そして、その特徴とするところは、上記第2の工程にお
ける上記信号端子側のボンディングワイヤ接続点が上記
混成集積回路側のボンディングワイヤ接続点よりも高い
位置にあるようにした点にある。The feature is that the bonding wire connection point on the signal terminal side in the second step is located at a higher position than the bonding wire connection point on the hybrid integrated circuit side.
作 用
本発明方、法によると、信号端子側のボンディングワイ
ヤ接続点が混成集積回路側のボンディングワイヤ接続点
よりも高い位置にあるようにしてワイヤボンディングを
行うようにしているので、ワイヤボンディングを行った
後に金属パッケージ基台を再加熱して金属パッケージ基
台と混成集積回路間に介在する半田材が再溶融して内部
応力が解放されたとしても、各部材は、信号端子側のボ
ンディングワイヤ接続点と混成集積回路側のボンディン
グワイヤ接続点が近づく方向に変形する。よって、本発
明方法によると、半田材の再溶融に起因するボンディン
グワイヤの伸びや断線が防止される。この場合、第2の
工程においてボンディングワイヤが最短距離となるよう
にワイヤボンディングを行うことによって、半田材が再
溶融した後におけるボンディングワイヤの湾曲が僅かな
ものとなるから、伝送特性の劣化は少ない。According to the method of the present invention, wire bonding is performed with the bonding wire connection point on the signal terminal side being located at a higher position than the bonding wire connection point on the hybrid integrated circuit side. Even if the metal package base is reheated and the solder material interposed between the metal package base and the hybrid integrated circuit is remelted and the internal stress is released, each component will not be able to connect to the bonding wire on the signal terminal side. The connection point and the bonding wire connection point on the hybrid integrated circuit side are deformed in a direction closer to each other. Therefore, according to the method of the present invention, elongation and breakage of the bonding wire due to remelting of the solder material can be prevented. In this case, by performing wire bonding in the second step so that the bonding wire has the shortest distance, the bending of the bonding wire after the solder material is remelted will be slight, so there will be little deterioration in transmission characteristics. .
実 施 例 以下本発明の実施例を図面に基づいて説胡する。Example Embodiments of the present invention will be explained below based on the drawings.
第5図は本発明の実施に使用することができるパッケー
ジの分解斜視図である。このパッケージは、複数(この
例では6個)の信号端子2が縁部に設けられた無酸素銅
からなる金属パッケージ基台4と、各信号端子18を横
切る形で金属パッケージ基台4に銀ロー接合により固着
される金属枠部材12と、金属枠部材12の上端に半田
付けにより固着される金属蓋部材14とから構成される
。FIG. 5 is an exploded perspective view of a package that can be used to implement the present invention. This package consists of a metal package base 4 made of oxygen-free copper on which a plurality (six in this example) of signal terminals 2 are provided on the edge, and a metal package base 4 made of oxygen-free copper with a silver It is composed of a metal frame member 12 fixed by low welding, and a metal lid member 14 fixed to the upper end of the metal frame member 12 by soldering.
金属パッケージ基台4上の各信号端子2で囲まれる位置
には、信号端子18の固着面と同一平面をなす平坦面が
形成されており、この平坦面上に混成集積回路6が固着
される。信号端子2は、金属パッケージ基台4上に固着
されたアルミナ等からなる誘電体ブロック16と、この
誘電体ブロック16上に形成された導体薄膜からなる端
子側マイクロストリップ線路18とから構成される。金
属枠部材12の下端には各信号端子2に対応する位置に
切込み20が形成されており、金属枠部材12と金属パ
ッケージ基台4との接合に際して切込み20にガラス封
止剤等を配しておくことによって、当該接合部の気密封
止及び端子側マイクロストリップ線路18の絶縁がなさ
れる。A flat surface coplanar with the fixing surface of the signal terminal 18 is formed at a position surrounded by each signal terminal 2 on the metal package base 4, and the hybrid integrated circuit 6 is fixed onto this flat surface. . The signal terminal 2 is composed of a dielectric block 16 made of alumina or the like fixed on the metal package base 4, and a terminal-side microstrip line 18 made of a conductive thin film formed on the dielectric block 16. . A notch 20 is formed at the lower end of the metal frame member 12 at a position corresponding to each signal terminal 2, and when joining the metal frame member 12 and the metal package base 4, a glass sealant or the like is placed in the notch 20. By doing so, the joint portion is hermetically sealed and the terminal side microstrip line 18 is insulated.
このパッケージを用いて混成集積回路6の実装を行う場
合には、予め信号端子2を金属パッケージ基台4に固着
しておき、金属枠部材工2も金属パッケージ基台4に接
合しておく。そして、混成集積回路6をA u / S
n半田等の半田材を用いて金属パッケージ基台4上に
固着く第1の工程)した後、ワイヤボンディングを行い
(第2の工程)、最後に各部材を加熱して金属蓋部材1
4を金属枠部材12に半田付けにより固着する(第3の
工程)。When mounting the hybrid integrated circuit 6 using this package, the signal terminals 2 are fixed to the metal package base 4 in advance, and the metal frame member work 2 is also joined to the metal package base 4. Then, the hybrid integrated circuit 6 is A u / S
After the first step of fixing the metal package base 4 on the metal package base 4 using a solder material such as n-solder, wire bonding is performed (the second step), and finally each member is heated to form the metal lid member 1.
4 is fixed to the metal frame member 12 by soldering (third step).
第1図は本発明の第1実施例を説明するための図であり
、ワイヤボンディングに際してのワイヤボンディング部
近傍の平面図(a)、断面図ら)が示されている。混成
集積回路6において、22は金属パッケージ基台4上に
半田材8により固着された誘電体基板、24は誘電体基
板22上に形成された集積回路側マイクロストリップ線
路である。26は金属枠部材の切込み20と信号端子2
間に介在するガラス封止剤である。この実施例では、信
号端子の誘電体ブロック16を混成集積回路の誘電体基
板22よりも厚く形成しておくことにより、信号端子側
のボンディングワイヤ接続点が混成集積回路側のボンデ
ィングワイヤ接続点よりも高い位置にあるようにしてい
る。FIG. 1 is a diagram for explaining a first embodiment of the present invention, and shows a plan view (a) and a cross-sectional view of the vicinity of a wire bonding portion during wire bonding. In the hybrid integrated circuit 6, 22 is a dielectric substrate fixed to the metal package base 4 with a solder material 8, and 24 is a microstrip line formed on the dielectric substrate 22 on the integrated circuit side. 26 is a notch 20 in the metal frame member and a signal terminal 2
A glass sealant is interposed between the two. In this embodiment, the dielectric block 16 of the signal terminal is formed thicker than the dielectric substrate 22 of the hybrid integrated circuit, so that the bonding wire connection point on the signal terminal side is greater than the bonding wire connection point on the hybrid integrated circuit side. It is also placed in a high position.
こうしておくと、金属蓋部材14を半田付けにより金属
枠部材12に固着するに際して半田材8が再溶融したと
しても、金属パッケージ基台4における塑性変形の残留
による信号端子2の混成集積回路6に対する相対変位は
、第4図に示すように、信号端子2及び混成集積回路6
におけるボンディングワイヤ接続点の高さが一致する方
向に生じるから、ボンディングワイヤ10に不所望な応
力が加わって、ボンディングワイヤ10が伸びたり断線
することが防止される。In this way, even if the solder material 8 is remelted when the metal lid member 14 is fixed to the metal frame member 12 by soldering, the signal terminals 2 will not be affected by the hybrid integrated circuit 6 due to residual plastic deformation in the metal package base 4. The relative displacement is determined by the signal terminal 2 and the hybrid integrated circuit 6, as shown in FIG.
Since the heights of the bonding wire connection points are aligned in the same direction, it is possible to prevent the bonding wire 10 from being stretched or broken due to undesired stress being applied to the bonding wire 10.
第2図は第2実施例を示す図である。この実施例では、
信号端子2の厚みについては従来と同様混成集積回路6
の厚みと同等に設定しておき、信号端子側のボンディン
グワイヤ接続を、端子側マイクロストリップ線路18上
に設けられたチップコンデンサ28を介してなすことに
より、信号端子側のボンディングワイヤ接続点が混成集
積回路側のボンディングワイヤ接続点よりも高い位置に
あるようにしている。マイクロ波集積回路においては、
直流バイアス素子用のチップコンデンサを搭載する必要
があることが多く、このような場合に第2実施例のよう
に本発明を実施すれば、混成集積回路6上へのチップコ
ンデンサの搭載が不要になり、誘電体基板22における
実装専有領域が拡大され、設計性、製造性が向上する。FIG. 2 is a diagram showing a second embodiment. In this example,
The thickness of the signal terminal 2 is the same as the conventional hybrid integrated circuit 6.
By setting the bonding wire connection on the signal terminal side to be equal to the thickness of It is located at a higher position than the bonding wire connection point on the integrated circuit side. In microwave integrated circuits,
It is often necessary to mount a chip capacitor for a DC bias element, and in such cases, if the present invention is implemented as in the second embodiment, it becomes unnecessary to mount a chip capacitor on the hybrid integrated circuit 6. Therefore, the exclusive mounting area on the dielectric substrate 22 is expanded, and designability and manufacturability are improved.
また、第2実施例によると、従来方法において使用され
ていた部材をそのまま使用することができる。Furthermore, according to the second embodiment, the members used in the conventional method can be used as they are.
第3図は本発明の第3実施例を示す図である。FIG. 3 is a diagram showing a third embodiment of the present invention.
この実施例では、第2実施例におけるチップコンデンサ
28に代えて、チップコンデンサ28と同等の大きさ及
び形状を有する金属ブロック30を用いている。この場
合にも、ワイヤボンディングに際しての信号端子側のボ
ンディングワイヤ接続点が混成集積回路側のボンディン
グワイヤ接続点よりも高い位置にあるようにすることが
できるので、ボンディングワイヤの伸びや断線を未然に
防止することができる。第3実施例においても、従来方
法において使用された信号端子等の部材をそのまま使用
することができる。In this embodiment, a metal block 30 having the same size and shape as the chip capacitor 28 is used in place of the chip capacitor 28 in the second embodiment. In this case, the bonding wire connection point on the signal terminal side can be placed at a higher position than the bonding wire connection point on the hybrid integrated circuit side during wire bonding, so stretching and disconnection of the bonding wire can be prevented. It can be prevented. In the third embodiment as well, members such as signal terminals used in the conventional method can be used as they are.
第1乃至第3の実施例において、ボンディングワイヤが
できる限り短くなるようにワイヤボンディングを行うこ
とによって、最終的な形態におけるボンディングワイヤ
の湾曲は僅かなものになるから、伝送特性の劣化は少な
い。即ち、従来方法において、予めボンディングワイヤ
を撓ましてワイヤボンディングを行ってボンディングワ
イヤの伸びや断線を防止しようとする場合には、最終的
な形態でのボンディングワイヤの撓みが僅かなものにな
るように予めボンディングワイヤの撓みを特定しておく
ことが困難であるという事実を考慮すると、第1乃至第
3の実施例のように最終的な形態でのボンディングワイ
ヤの湾曲を僅かなものに抑えておくことは、伝送特性の
劣化を最小限に抑えておく上で有効である。In the first to third embodiments, by performing wire bonding so that the bonding wire is as short as possible, the bending of the bonding wire in the final form is slight, so there is little deterioration in transmission characteristics. That is, in the conventional method, when wire bonding is performed by bending the bonding wire in advance to prevent the bonding wire from elongating or breaking, it is necessary to bend the bonding wire in advance so that the bending of the bonding wire in the final form is slight. Considering the fact that it is difficult to specify the bending of the bonding wire in advance, the bending of the bonding wire in the final form is kept to a slight level as in the first to third embodiments. This is effective in minimizing deterioration of transmission characteristics.
発明の詳細
な説明したように、本発明によると、実装に際してボン
ディングワイヤが伸びたり断線する恐れがなく、しかも
ワイヤボンディングによる伝送特性の劣化が少ない混成
集積回路の実装方法が提供されるという効果を奏する。As described in detail, the present invention provides a method for mounting a hybrid integrated circuit in which there is no risk of bonding wires being stretched or disconnected during mounting, and the transmission characteristics are less likely to deteriorate due to wire bonding. play.
第1図は本発明の第1実施例を示す図、第2図は本発明
の第2実施例を示す図、第3図は本発明の第3実施例を
示す図、第4図は本発明の実施例(第1実施例)におけ
る作用の説明図、
第5図は本発明の実施に使用することができるパッケー
ジの分解斜視図、
第6図は従来技術の説明図である。
2・・・信号端子、
4・・・金属パッケージ基台、
6・・・混成集積回路、
8・・・半田材、
16・・・誘電体ブロック、
18・・・端子側マイクロストリップ線路、22・・・
誘電体基板、
24・・・集積回路側マイクロストリップ線路、28・
・・チップコンデンサ、
30・・・金属ブロック。1 is a diagram showing a first embodiment of the present invention, FIG. 2 is a diagram showing a second embodiment of the present invention, FIG. 3 is a diagram showing a third embodiment of the present invention, and FIG. 4 is a diagram showing the present invention. FIG. 5 is an exploded perspective view of a package that can be used to implement the present invention. FIG. 6 is an explanatory diagram of the prior art. 2... Signal terminal, 4... Metal package base, 6... Hybrid integrated circuit, 8... Solder material, 16... Dielectric block, 18... Terminal side microstrip line, 22 ...
Dielectric substrate, 24... Integrated circuit side microstrip line, 28...
...Chip capacitor, 30...Metal block.
Claims (4)
た誘電体ブロック(16)からなる信号端子(2)が縁
部に設けられた金属パッケージ基台(4)を加熱して、
該金属パッケージ基台(4)の平坦面上に、集積回路側
マイクロストリップ線路(24)が形成された誘電体基
板(22)を備えた混成集積回路(6)を半田材(8)
により固着する第1の工程と、上記端子側マイクロスト
リップ線路(18)と上記集積回路側マイクロストリッ
プ線路(24)とをワイヤボンディング接続する第2の
工程と、 上記金属パッケージ基台(4)を再加熱する第3の工程
とをこの順に含んでなる混成集積回路の実装方法におい
て、 上記第2の工程における上記信号端子(2)側のボンデ
ィングワイヤ接続点が上記混成集積回路(6)側のボン
ディングワイヤ接続点よりも高い位置にあるようにした
ことを特徴とする混成集積回路の実装方法。1. Heating a metal package base (4) on which a signal terminal (2) consisting of a dielectric block (16) on which a terminal-side microstrip line (18) is formed is provided at the edge;
A hybrid integrated circuit (6) comprising a dielectric substrate (22) on which an integrated circuit side microstrip line (24) is formed is placed on the flat surface of the metal package base (4) using a solder material (8).
a second step of connecting the terminal-side microstrip line (18) and the integrated circuit-side microstrip line (24) by wire bonding; and a second step of bonding the metal package base (4). and a third step of reheating in this order, wherein the bonding wire connection point on the signal terminal (2) side in the second step is on the hybrid integrated circuit (6) side. A method for mounting a hybrid integrated circuit, characterized in that the bonding wire is located at a higher position than the connection point.
22)は上記金属パッケージ基台(4)上の同一平面上
に固着され、上記誘電体ブロック(16)を上記誘電体
基板(22)よりも厚く形成することにより、上記第2
の工程における上記信号端子(2)側のボンディングワ
イヤ接続点が上記混成集積回路(6)側のボンディング
ワイヤ接続点よりも高い位置にあるようにしたことを特
徴とする請求項1に記載の混成集積回路の実装方法。2. The dielectric block (16) and the dielectric substrate (
22) is fixed on the same plane on the metal package base (4), and by forming the dielectric block (16) thicker than the dielectric substrate (22), the second
2. The hybrid device according to claim 1, wherein the bonding wire connection point on the signal terminal (2) side in the step is located at a higher position than the bonding wire connection point on the hybrid integrated circuit (6) side. How to implement integrated circuits.
、上記端子側マイクロストリップ線路(18)上に設け
られたチップコンデンサ(28)を介してなすことによ
り、上記第2の工程における上記信号端子(2)側のボ
ンディングワイヤ接続点が上記混成集積回路(6)側の
ボンディングワイヤ接続点よりも高い位置にあるように
したことを特徴とする請求項1に記載の混成集積回路の
実装方法。3. By making the bonding wire connection on the signal terminal (2) side via a chip capacitor (28) provided on the terminal side microstrip line (18), the signal terminal (2) in the second step is made. 2. The method of mounting a hybrid integrated circuit according to claim 1, wherein the bonding wire connection point on the side of the hybrid integrated circuit (6) is located at a higher position than the bonding wire connection point on the hybrid integrated circuit (6) side.
、上記端子側マイクロストリップ線路(18)上に設け
られた金属ブロック(30)を介してなすことにより、
上記第2の工程における上記信号端子(2)側のボンデ
ィングワイヤ接続点が上記混成集積回路(6)側のボン
ディングワイヤ接続点よりも高い位置にあるようにした
ことを特徴とする請求項1に記載の混成集積回路の実装
方法。4. By making the bonding wire connection on the signal terminal (2) side via the metal block (30) provided on the terminal side microstrip line (18),
2. The method according to claim 1, wherein the bonding wire connection point on the signal terminal (2) side in the second step is located at a higher position than the bonding wire connection point on the hybrid integrated circuit (6) side. A method of implementing the described hybrid integrated circuit.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP6092090A JPH03263897A (en) | 1990-03-14 | 1990-03-14 | Packaging of hybrid integrated circuit |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP6092090A JPH03263897A (en) | 1990-03-14 | 1990-03-14 | Packaging of hybrid integrated circuit |
Publications (1)
Publication Number | Publication Date |
---|---|
JPH03263897A true JPH03263897A (en) | 1991-11-25 |
Family
ID=13156305
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP6092090A Pending JPH03263897A (en) | 1990-03-14 | 1990-03-14 | Packaging of hybrid integrated circuit |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPH03263897A (en) |
Cited By (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2006190712A (en) * | 2004-12-28 | 2006-07-20 | Toshiba Corp | Semiconductor device |
JP2010153925A (en) * | 2010-04-02 | 2010-07-08 | Toshiba Corp | Semiconductor device |
JP2011171576A (en) * | 2010-02-19 | 2011-09-01 | Fujitsu Ltd | Integrated circuit device, amplifier, and communication apparatus module |
Citations (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS63229725A (en) * | 1987-03-18 | 1988-09-26 | Nec Corp | Semiconductor device |
-
1990
- 1990-03-14 JP JP6092090A patent/JPH03263897A/en active Pending
Patent Citations (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS63229725A (en) * | 1987-03-18 | 1988-09-26 | Nec Corp | Semiconductor device |
Cited By (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2006190712A (en) * | 2004-12-28 | 2006-07-20 | Toshiba Corp | Semiconductor device |
JP4519637B2 (en) * | 2004-12-28 | 2010-08-04 | 株式会社東芝 | Semiconductor device |
JP2011171576A (en) * | 2010-02-19 | 2011-09-01 | Fujitsu Ltd | Integrated circuit device, amplifier, and communication apparatus module |
JP2010153925A (en) * | 2010-04-02 | 2010-07-08 | Toshiba Corp | Semiconductor device |
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