JPH05299570A - Semiconductor device - Google Patents
Semiconductor deviceInfo
- Publication number
- JPH05299570A JPH05299570A JP4103245A JP10324592A JPH05299570A JP H05299570 A JPH05299570 A JP H05299570A JP 4103245 A JP4103245 A JP 4103245A JP 10324592 A JP10324592 A JP 10324592A JP H05299570 A JPH05299570 A JP H05299570A
- Authority
- JP
- Japan
- Prior art keywords
- capacitor
- transmission line
- signal transmission
- semiconductor element
- frame
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Withdrawn
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/484—Connecting portions
- H01L2224/48463—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond
- H01L2224/48465—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond the other connecting portion not on the bonding area being a wedge bond, i.e. ball-to-wedge, regular stitch
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
- H01L2224/491—Disposition
- H01L2224/4912—Layout
- H01L2224/49175—Parallel arrangements
Landscapes
- Lead Frames For Integrated Circuits (AREA)
- Microwave Amplifiers (AREA)
Abstract
Description
【０００１】[0001]
【産業上の利用分野】本発明は、半導体装置に関し、よ
り詳しくは、マイクロ波通信等に用いられる高周波増幅
器を備えた半導体装置に関する。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device, and more particularly to a semiconductor device having a high frequency amplifier used for microwave communication and the like.
【０００２】近年、マイクロ波通信の発展に伴って、高
周波増幅器の小型化が要求されている。In recent years, along with the development of microwave communication, miniaturization of high frequency amplifiers has been demanded.
【０００３】[0003]
【従来の技術】高周波増幅器においては、半導体素子と
信号源及び負荷とのインーダンス整合をとるために、キ
ャパシタとインダクタンスよりなる整合回路が設けられ
る。2. Description of the Related Art In a high frequency amplifier, a matching circuit composed of a capacitor and an inductance is provided in order to achieve impedance matching between a semiconductor element and a signal source and a load.
【０００４】整合回路としては、図３に例示するよう
に、半導体素子（増幅器）収納用のパッケージ３１内に
コンデンサＣ1 を組み込んだものがある。このパッケー
ジ３１は、接地線に接続される金属製の基台３２と、そ
の上に取り付けられるセラミック製の枠体３３と、枠体
３３を覆う蓋体３４とを有しており、枠体３３に囲まれ
た基台３１の中央には半導体素子（増幅器）３５が搭載
され、また、その両側の基台３１上には、誘電体３６を
挟んだ電極３７からなるコンデンサＣ1 が形成されてい
る。As an example of the matching circuit, there is a matching circuit in which a capacitor C 1 is incorporated in a package 31 for accommodating a semiconductor element (amplifier). The package 31 has a metal base 32 connected to a ground wire, a ceramic frame 33 mounted on the base 32, and a lid 34 covering the frame 33. A semiconductor element (amplifier) 35 is mounted in the center of a base 31 surrounded by the, and a capacitor C 1 composed of electrodes 37 sandwiching a dielectric 36 is formed on the bases 31 on both sides thereof. There is.
【０００５】そして、半導体素子３５の端子は、コンデ
ンサＣ1 の電極３７を介して枠体３３の入出力端子とな
るリード３８ａ，３８ｂに接続され、そのリード３８
ａ，３８ｂは、図３(b) に示すように、配線基板３９上
の信号伝送線路Ｌ1 に半田付けされている（図３(b))。
また、半導体素子３５を構成するＦＥＴのゲートは一方
の端子３８に接続され、ドレインは他方の端子３９に接
続され、ソースは基台３１を介して接地線GND に繋がっ
ている。The terminals of the semiconductor element 35 are connected to the leads 38a and 38b, which are the input / output terminals of the frame 33, through the electrodes 37 of the capacitor C 1.
As shown in FIG. 3 (b), a and 38b are soldered to the signal transmission line L 1 on the wiring board 39 (FIG. 3 (b)).
Further, the gate of the FET constituting the semiconductor element 35 is connected to one terminal 38, the drain is connected to the other terminal 39, and the source is connected to the ground line GND via the base 31.
【０００６】しかしながら、キャパシタＣ1 をパッケー
ジ３０内に収容するタイプのものでは、半導体素子３５
のインピーダンスがばらついたり、半導体素子３５がパ
ッケージ３０に収められた半導体装置を多段接続するこ
とにより電源又は負荷のインーダンスが変わったり、或
いは、使用する周波数を変えたりする場合等には、完全
な整合がとれなくなるために半導体素子３５の本来の特
性が十分に得られないという問題が生じる。However, in the type in which the capacitor C 1 is housed in the package 30, the semiconductor element 35
If the impedance of the power supply or the load is changed by connecting the semiconductor devices having the semiconductor element 35 housed in the package 30 in multiple stages, or if the frequency to be used is changed, etc. As a result, the original characteristics of the semiconductor element 35 cannot be obtained sufficiently.
【０００７】そこで、図４に示すように、インーダンス
整合用のコンデンサをパッケージの外部に設けるものが
提案されている。この半導体装置４０は、金属製基台４
１上のセラミック製枠体４２内に収容された半導体素子
４３の両側にセラミック基板４４を形成し、そのセラミ
ック基板４４上に形成されたＴ字形の導電膜４５を中継
して半導体素子４３をリード４６ａ，４６ｂに接続する
ものであり、半導体装置４０のリード４６ａ，４６ｂの
外端にコンデンサＣ2 を取り付けるようにしている。Therefore, as shown in FIG. 4, there has been proposed a capacitor for impedance matching provided outside the package. The semiconductor device 40 includes a metal base 4
1. A ceramic substrate 44 is formed on both sides of a semiconductor element 43 housed in a ceramic frame body 42 on 1 and a semiconductor element 43 is lead by relaying a T-shaped conductive film 45 formed on the ceramic substrate 44. 46a and 46b, and the capacitor C 2 is attached to the outer ends of the leads 46a and 46b of the semiconductor device 40.
【０００８】具体的には、図４(b) に示すように、半導
体装置４０のリード４６ａ，４６ｂを配線基板４７上の
信号伝送線路パターンＬ2 に半田付けするとともに、信
号伝送線路パターンＬ2 と接地線GND の間にインピーダ
ンス整合用のコンデンサＣ2を半田などで接続する。な
お、符号４８は、枠体４２の蓋体を示している。[0008] Specifically, as shown in FIG. 4 (b), the lead 46a of the semiconductor device 40, together with the soldered to the signal transmission line pattern L 2 on the wiring substrate 47 to 46b, the signal transmission line pattern L 2 Connect a capacitor C 2 for impedance matching between this and ground line GND by soldering. Note that reference numeral 48 indicates a lid of the frame body 42.
【０００９】[0009]
【発明が解決しようとする課題】しかし、コンデンサＣ
2 を取付ける場合に、パッケージ４０のリード４６ａ，
４６ｂを接続しているロウ材が溶けてリード４６ａ，４
６ｂと信号伝送線路の接続が不良になることを防止する
ために、リード４６ａ，４６ｂから離れた位置にコンデ
ンサＣ2 を取付けることになり、無駄な取付けスペース
が生じてしまう。However, the capacitor C
When mounting 2 , the leads 46a of the package 40,
The brazing material connecting 46b is melted and leads 46a, 4
In order to prevent the connection between the signal transmission line 6b and the signal transmission line from becoming defective, the capacitor C 2 is mounted at a position away from the leads 46a and 46b, resulting in a wasteful mounting space.
【００１０】また、最適な容量値を探す場合には、容量
が異なるコンデンサを信号伝送線路Ｌ2 に接続させたり
離脱させる作業を繰り返すために、信号伝送線路Ｌ2 の
表面が劣化して損失が増加するなどの問題があった。Further, when the optimum capacitance value is searched for, since the work of connecting and disconnecting the capacitors having different capacitances to the signal transmission line L 2 is repeated, the surface of the signal transmission line L 2 is deteriorated and loss is caused. There was a problem such as an increase.
【００１１】本発明はこのような問題に鑑みてなされた
ものであって、コンデンサの取付けマージンを小さく
し、しかも信号伝送線路の劣化を防止できる半導体装置
を提供することを目的とする。The present invention has been made in view of the above problems, and an object of the present invention is to provide a semiconductor device capable of reducing the mounting margin of a capacitor and preventing deterioration of a signal transmission line.
【００１２】[0012]
【課題を解決するための手段】上記した課題は、図１に
例示するように、基台１の上に取付けられた絶縁性の枠
体２と、前記枠体２に囲まれた領域の前記基台１の上に
搭載される半導体素子10と、前記枠体２の両側部に形成
され、かつ前記半導体素子10に接続される導電性パター
ン４、５と、一端が前記導電性パターン４、５の外縁部
に接続され、他端が外部の信号伝送線路に繋げられる第
一のリード８ａ、９ａと、一端が前記導電性パターン
４、５の外縁部に接続され、他端が外部のコンデンサＣ
0 に導通される第二のリード８ｂ、９ｂとを有すること
を特徴とする半導体装置によって達成する。As illustrated in FIG. 1, the above-mentioned problems are solved by an insulating frame 2 mounted on a base 1 and an area surrounded by the frame 2. The semiconductor element 10 mounted on the base 1, conductive patterns 4 and 5 formed on both sides of the frame 2 and connected to the semiconductor element 10, and one end of the conductive pattern 4, 5, first leads 8a and 9a connected to the outer edge of the conductive pattern 4 and 5, the other end of which is connected to an external signal transmission line, and one end of which is connected to the outer edge of the conductive patterns 4 and 5 and the other end of which is an external capacitor. C
This is achieved by a semiconductor device having second leads 8b and 9b that are electrically connected to 0 .
【００１３】[0013]
【作 用】本発明によれば、外部の信号伝送線路に接続
されるリード８ａ，９ａと並列に第二のリード８ｂ、９
ｂを設け、ここに直接又は導電膜を介して外部のコンデ
ンサＣ0 を接続するようにしている。[Operation] According to the present invention, the second leads 8b, 9 are connected in parallel with the leads 8a, 9a connected to the external signal transmission line.
b is provided, and the external capacitor C 0 is connected to this directly or through a conductive film.
【００１４】このため、半導体素子１０および信号源、
負荷のインピーダンスの変化や、使用周波数の変化に応
じてコンデンサＣ0 を取換える際に、ロウ材を溶融する
ための熱は信号伝送線路に伝達しないので、信号伝送線
路の劣化が防止され、損失が増加せず、半導体装置の本
来の性能向上に寄与する。Therefore, the semiconductor element 10 and the signal source,
Since the heat for melting the brazing material is not transferred to the signal transmission line when the capacitor C 0 is replaced according to the change in the impedance of the load or the change in the operating frequency, deterioration of the signal transmission line is prevented and loss is caused. Does not increase and contributes to the original improvement of the performance of the semiconductor device.
【００１５】また、半導体装置に近いところにコンデン
サＣ0 を接続することが可能になるため、取付けマージ
ンが小さくなり、半導体装置装着用基板の無駄なスペー
スを減らして小型化が促進される。Further, since it becomes possible to connect the capacitor C 0 to a place near the semiconductor device, the mounting margin is reduced, the wasted space of the semiconductor device mounting substrate is reduced, and miniaturization is promoted.
【００１６】[0016]
【実施例】そこで、以下に本発明の実施例を図面に基づ
いて説明する。図１(a) は、本発明の一実施例装置を示
す平面図、図１(b) は、その部分拡大平面図、図１(c),
(d) は、同図(b) のＸ−Ｘ線、Ｙ−Ｙ線の断面図であ
る。Embodiments of the present invention will be described below with reference to the drawings. 1 (a) is a plan view showing an apparatus according to an embodiment of the present invention, FIG. 1 (b) is a partially enlarged plan view thereof, and FIG.
6D is a sectional view taken along line XX and YY in FIG.
【００１７】図において符号１は、CuW 等の金属よりな
る基台で、その上には、セラミック製の枠体２が取付け
られ、この枠体２には、コバール(kovar) などの金属材
よりなる蓋体３が被せられている。In the figure, reference numeral 1 is a base made of a metal such as CuW, on which a ceramic frame 2 is attached, and the frame 2 is made of a metal material such as kovar. The cover 3 is covered.
【００１８】また、枠体２のうち両側部の中間層には金
の配線パターン４、５が挟まれて形成されている。これ
らの配線パターン４、５は、枠体２の内縁から外縁にか
けて２つに分岐された形状をしており、その内縁部４
ａ、５ａ及び外縁部４ｂ，４ｃ，５ｂ，５ｃは枠体上層
部２ａの窓６ａ〜ｃ、７ａ〜ｃから露出してマイクロス
トリップ線路となり、その他の領域はストリップ線路を
構成している。Gold wiring patterns 4 and 5 are sandwiched between the intermediate layers on both sides of the frame body 2. These wiring patterns 4 and 5 have a shape branched into two from the inner edge to the outer edge of the frame body 2, and the inner edge portion 4 thereof.
The a, 5a and the outer edge portions 4b, 4c, 5b, 5c are exposed from the windows 6a to 7c of the frame upper layer portion 2a to become microstrip lines, and the other regions form strip lines.
【００１９】そして、配線パターン４，５の外縁部４
ｂ，４ｃ、５ｂ，５ｃにはそれぞれ２つのリード８ａ，
８ｂ、９ａ，９ｂが接続されている。このうち、一側の
配線パターン４に繋がる一方のリード８ａは入力端子と
なり、他方のリード８ｂにはコンデンサが繋げられる。
また、別の配線パターン５上の一方のリード９ａは出力
端子であり、他方のリード９ｂにはコンデンサが接続さ
れる。Then, the outer edge portion 4 of the wiring patterns 4 and 5
b, 4c, 5b, 5c have two leads 8a,
8b, 9a and 9b are connected. Of these, one lead 8a connected to the wiring pattern 4 on one side serves as an input terminal, and a capacitor is connected to the other lead 8b.
Further, one lead 9a on another wiring pattern 5 is an output terminal, and the other lead 9b is connected to a capacitor.
【００２０】１０は、枠体２に囲まれた基台１の中央に
取付けられたＦＥＴよりなる半導体素子で、その両側方
の基台１上にはセラミック等の誘電体基板１１が形成さ
れ、この誘電体基板１１の上には、半導体素子１０のゲ
ート端子ｇとドレイン端子ｄに沿って導電性薄膜１２、
１３がそれぞれ形成されている。そして、ゲート端子ｇ
と入力側の導電性薄膜１２、およびドレイン端子ｄと出
力側の導電性薄膜１３は、それぞれ金線１４を介して接
続されている。また、それらの導電性薄膜１２、１３
は、外方に向けて延在する非直線部１２ａ、１３ａを有
し、それらの外端部は、金線１５を介して枠体２上の配
線パターン４、５の内縁部４ａ、５ａに接続されてい
る。Reference numeral 10 denotes a semiconductor element composed of an FET mounted in the center of the base 1 surrounded by the frame 2, and a dielectric substrate 11 made of ceramic or the like is formed on the bases 1 on both sides thereof. A conductive thin film 12 is formed on the dielectric substrate 11 along the gate terminal g and the drain terminal d of the semiconductor element 10.
13 are formed respectively. And the gate terminal g
The conductive thin film 12 on the input side and the conductive thin film 13 on the output side, and the conductive thin film 13 on the output side are connected to each other via a gold wire 14. Also, those conductive thin films 12, 13
Has non-linear portions 12a and 13a extending outward, and their outer ends are connected to the inner edge portions 4a and 5a of the wiring patterns 4 and 5 on the frame body 2 via the gold wire 15. It is connected.
【００２１】なお、図中符号１６は、基台１の両端部に
形成されたビス止め用の凹部を示している。次に、上記
した実施例の作用を図２に基づいて説明する。Reference numeral 16 in the figure denotes recesses formed at both ends of the base 1 for screwing. Next, the operation of the above embodiment will be described with reference to FIG.
【００２２】図２において、符号２０は、上述した半導
体装置の基台１を収納する窪み２１を有する放熱板で、
その両側方には、絶縁性の配線用基板１９が形成され、
それぞれには信号伝送線路パターン２２，２３と接地パ
ターン２４，２５が形成され、また、それらの間であっ
て窪み２１の近傍には中継用電極２６，２７が形成され
ている。In FIG. 2, reference numeral 20 is a radiator plate having a recess 21 for accommodating the base 1 of the semiconductor device described above.
Insulating wiring boards 19 are formed on both sides of the wiring board 19.
Signal transmission line patterns 22 and 23 and ground patterns 24 and 25 are formed respectively, and relay electrodes 26 and 27 are formed between them and near the recess 21.
【００２３】まず、基台１を窪み２１に嵌め込むととも
に上記半導体装置の両側の２つのリード８ａ，８ｂ、９
ａ，９ｂを信号伝送線路パターン２２，２３と中継用電
極２６，２７の上に設置し、この状態で、基台１の両端
をビス止めして固定するとともに、各リード８ａ，８
ｂ、９ａ，９ｂを半田等のロウ材によってその下の信号
伝送線路パターン２２、２３及び中継用電極２６、２７
に接続する。First, the base 1 is fitted into the recess 21 and the two leads 8a, 8b, 9 on both sides of the semiconductor device are formed.
a and 9b are installed on the signal transmission line patterns 22 and 23 and the relay electrodes 26 and 27, and in this state, both ends of the base 1 are fixed with screws and fixed to the leads 8a and 8b.
b, 9a, 9b are made of a brazing material such as solder, and the signal transmission line patterns 22, 23 and relay electrodes 26, 27 thereunder are provided.
Connect to.
【００２４】そして、インピーダンス整合素子としてコ
ンデンサを接続する場合には、図２(b) に示すように、
ロウ材によりコンデンサＣ0 の２つの端子を中継用電極
２６，２７と接地パターン２４，２５に接続することに
なる。When a capacitor is connected as an impedance matching element, as shown in FIG. 2 (b),
The brazing material connects the two terminals of the capacitor C 0 to the relay electrodes 26 and 27 and the ground patterns 24 and 25.
【００２５】したがって、コンデンサＣ0 を接続する際
には信号伝送線路パターン２２，２３は加熱されないの
で、その上のロウ材が溶けて劣化したりリード８ａ、９
ｂの接続が不良になる事態は回避される。Therefore, since the signal transmission line patterns 22 and 23 are not heated when the capacitor C 0 is connected, the brazing material on the patterns is melted and deteriorated and the leads 8a and 9 are formed.
The situation in which the connection of b is bad is avoided.
【００２６】さらに、コンデンサＣ0 の取付け位置は、
中継用電極２６，２７のうちパッケージに近い部分に寄
せて取付けることができ、これにより無駄なスペースが
少なくなる。この場合、半導体素子１０とコンデンサＣ
0 との距離が従来装置に比べて短くなるが、基台１上の
導電性薄膜１２，１３の非直線部１２ａ、１３ａの折れ
曲がりによる距離を長くすれば、その分だけストリップ
ラインが増加するので、コンデンサＣ0 と半導体素子１
０との間の電気長が長くなる。Further, the mounting position of the capacitor C 0 is
Since the relay electrodes 26, 27 can be mounted close to the package, the wasteful space can be reduced. In this case, the semiconductor element 10 and the capacitor C
Although the distance from 0 is shorter than that of the conventional device, if the distance due to the bending of the non-linear portions 12a and 13a of the conductive thin films 12 and 13 on the base 1 is lengthened, the strip line increases accordingly. , Capacitor C 0 and semiconductor element 1
The electrical length between 0 and 0 becomes long.
【００２７】以上により、半導体素子１０及び信号源、
負荷のインーダンスの変化や使用周波数の変化に応じて
コンデンサＣ0 を交換する場合に、信号伝送線路パター
ン２２，２３の表面が劣化することはなく、信号伝送線
路の損失が増加することはない。From the above, the semiconductor element 10 and the signal source,
When the capacitor C 0 is replaced according to the change of the impedance of the load or the change of the used frequency, the surfaces of the signal transmission line patterns 22 and 23 are not deteriorated and the loss of the signal transmission line is not increased.
【００２８】なお、コンデンサＣ0 は、中継用電極２
５、２６の上に接続してもよいし、リード８ｂ，９ｂの
上に直に接続してもよい。また、コンデンサＣ0 を取り
付ける際の加熱が配線パターン４、５を介して信号伝送
線路パターン２２、２３に伝わるおそれがある場合に
は、リード８ａ，８ｂ（９ａ，９ｂ）間の間隔を広げれ
ばよい。The capacitor C 0 is connected to the relay electrode 2
5, 26, or directly on the leads 8b, 9b. If there is a possibility that the heat generated when the capacitor C 0 is attached is transmitted to the signal transmission line patterns 22 and 23 via the wiring patterns 4 and 5, increase the distance between the leads 8a and 8b (9a and 9b). Good.
【００２９】[0029]
【発明の効果】以上述べたように本発明によれば、外部
の信号伝送線路に接続されるリードと並列に第二のリー
ドを設け、ここに直接又は導電膜を介して外部のコンデ
ンサを接続するようにしたので、半導体素子および信号
源、負荷のインピーダンスの変化や、使用周波数の変化
に応じてコンデンサを取換える際に、ロウ材を溶融する
ための熱は信号伝送線路に伝達せず、信号伝送線路の劣
化が防止され、半導体装置の本来の性能向上に寄与す
る。As described above, according to the present invention, the second lead is provided in parallel with the lead connected to the external signal transmission line, and the external capacitor is connected thereto directly or through the conductive film. Therefore, when the capacitors are changed according to the change in the impedance of the semiconductor element and the signal source and the load, and the change in the operating frequency, the heat for melting the brazing material is not transferred to the signal transmission line, The deterioration of the signal transmission line is prevented, which contributes to the original performance improvement of the semiconductor device.
【００３０】しかも、半導体装置に近いところにコンデ
ンサを接続して取付けマージンを小さくすることがで
き、半導体装置装着用基板の無駄なスペースを減らして
小型化が図れる。In addition, the mounting margin can be reduced by connecting a capacitor close to the semiconductor device, and the useless space of the semiconductor device mounting substrate can be reduced to achieve miniaturization.
【図１】本発明の一実施例を示す平面図、部分拡大平面
図及び部分拡大断面図である。FIG. 1 is a plan view, a partially enlarged plan view and a partially enlarged sectional view showing an embodiment of the present invention.
【図２】本発明の一実施例の作用を示す平面図である。FIG. 2 is a plan view showing the operation of one embodiment of the present invention.
【図３】従来の第１例を示す平面図である。FIG. 3 is a plan view showing a first conventional example.
【図４】従来の第２例を示す平面図である。FIG. 4 is a plan view showing a second conventional example.
１ 基台 ２ 枠体 ３ 蓋体 ４、５ 配線パターン（導電性パターン） ４ａ、５ａ 内縁部 ４ｂ、４ｃ、５ｂ、５ｃ 外縁部 ６ａ〜６ｃ 窓 ７ａ〜７ｃ 窓 ８ａ、８ｂ リード ９ａ、９ｂ リード １０ 半導体素子 １１ 絶縁膜 １２、１３ 導電性薄膜 1 Base 2 Frame 3 Lid 4, 5 Wiring Pattern (Conductive Pattern) 4a, 5a Inner Edge 4b, 4c, 5b, 5c Outer Edge 6a-6c Window 7a-7c Window 8a, 8b Lead 9a, 9b Lead 10 Semiconductor element 11 Insulating film 12, 13 Conductive thin film
Claims (1)
体（２）と、 前記枠体（２）に囲まれた領域の前記基台（１）の上に
搭載される半導体素子（10）と、 前記枠体（２）の両側部に形成され、かつ前記半導体素
子（10）に接続される導電性パターン（４、５）と、 一端が前記導電性パターン（４、５）の外縁部に接続さ
れ、他端が外部の信号伝送線路に繋げられる第一のリー
ド（８ａ、９ａ）と、 一端が前記導電性パターン（４、５）の外縁部に接続さ
れ、他端が外部のコンデンサ（Ｃ0 ）に導通される第二
のリード（８ｂ、９ｂ）とを有することを特徴とする半
導体装置。1. An insulative frame (2) mounted on a base (1), and mounted on the base (1) in an area surrounded by the frame (2). A semiconductor element (10), conductive patterns (4, 5) formed on both sides of the frame body (2) and connected to the semiconductor element (10), and one end of the conductive pattern (4, 5) a first lead (8a, 9a) connected to the outer edge of the conductive pattern (4, 5), the other end of which is connected to an external signal transmission line, and the other end of which is connected to the outer edge of the conductive pattern (4, 5) A semiconductor device having a second lead (8b, 9b) whose end is electrically connected to an external capacitor (C 0 ).
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP4103245A JPH05299570A (en) | 1992-04-22 | 1992-04-22 | Semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP4103245A JPH05299570A (en) | 1992-04-22 | 1992-04-22 | Semiconductor device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH05299570A true JPH05299570A (en) | 1993-11-12 |
Family
ID=14349060
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP4103245A Withdrawn JPH05299570A (en) | 1992-04-22 | 1992-04-22 | Semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH05299570A (en) |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2004304615A (en) * | 2003-03-31 | 2004-10-28 | Tdk Corp | High frequency composite part |
| JP2017228684A (en) * | 2016-06-23 | 2017-12-28 | 株式会社東芝 | Package for high frequency semiconductor |
-
1992
- 1992-04-22 JP JP4103245A patent/JPH05299570A/en not_active Withdrawn
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2004304615A (en) * | 2003-03-31 | 2004-10-28 | Tdk Corp | High frequency composite part |
| JP2017228684A (en) * | 2016-06-23 | 2017-12-28 | 株式会社東芝 | Package for high frequency semiconductor |
| US10224291B2 (en) | 2016-06-23 | 2019-03-05 | Kabushiki Kaisha Toshiba | Semiconductor device package with strip line structure and high frequency semiconductor device thereof |
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Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| A300 | Withdrawal of application because of no request for examination |
Free format text: JAPANESE INTERMEDIATE CODE: A300 Effective date: 19990706 |