JP6327379B1 - Gallium nitride semiconductor device and method for manufacturing gallium nitride semiconductor device - Google Patents

Abstract

A problem caused by a gate trench portion and a mesa portion is solved. A planar gate type gallium nitride semiconductor device, comprising: a gallium nitride single crystal substrate; a gallium nitride layer on the gallium nitride single crystal substrate; and a gallium nitride layer provided at least in part in the gallium nitride layer. A first source region of the first conductivity type exposed on the surface of the first source region, and a first buried region provided in the gallium nitride layer below the bottom of the first source region and having an impurity of the second conductivity type A first conductivity-type first base region that is adjacent to the first source region in a direction parallel to the surface, is provided on the first buried region, and is at least partially exposed to the surface; And a gate electrode provided above the first base region, and in a direction parallel to the depth direction of the gallium nitride layer, the second conductivity type impurity concentration in the first base region is the first buried region. From the top of Gradually decreases toward the surface, to provide a gallium nitride semiconductor device. [Selection] Figure 2

Description

  The present invention relates to a gallium nitride semiconductor device and a method for manufacturing a gallium nitride semiconductor device.

Conventionally, it is known that a gate trench portion is provided by partially removing an epitaxially formed p ⁻ -type gallium nitride (hereinafter referred to as GaN) layer (see, for example, Non-Patent Document 1). It is also known that a p ^- type GaN layer is partially removed to form a mesa portion of the GaN layer, and field plates are formed on the side and bottom of the mesa portion (see, for example, the same document). ). Patent Document 1 describes that magnesium (hereinafter referred to as Mg) is partially ion-implanted into a GaN layer, and then the diffusion region is made p-type by thermally diffusing Mg.
[Prior art documents]
[Non-patent literature]
[Non-Patent Document 1] Tohru Oka et al. , "Vertical GaN-based trench metal oxide semiconductor field-effect transistors on a free-standing GaN substrate with blocking voltage of 1.6 kV", Applied Physics Express, published 28 January 2014, Volume 7, Number 2,021002
[Patent Literature]
[Patent Document 1] JP 2007-258578 A

  In the case where the gate trench portion and the mesa portion are provided, the breakdown voltage is reduced due to electric field concentration at the corner portion at the bottom portion of the gate trench portion and the corner portion at the bottom portion of the mesa portion. In addition, the gate trench part and the mesa part have a problem of hindering microfabrication in the photolithography process. Furthermore, there is a problem that the surface of the GaN layer is damaged when the gate trench part and the mesa part are formed.

  In a first aspect of the present invention, a planar gate type gallium nitride semiconductor device is provided. The gallium nitride semiconductor device may include a gallium nitride single crystal substrate, a gallium nitride layer, a first source region, a first buried region, a first base region, and a gate electrode. The gallium nitride layer may be provided on the gallium nitride single crystal substrate. The first source region may be provided in the gallium nitride layer. The first source region may be at least partially exposed on the surface of the gallium nitride layer. The first source region may be of the first conductivity type. The first buried region may be provided in the gallium nitride layer below the bottom of the first source region. The first buried region may have a second conductivity type impurity. The first base region may be adjacent to the first source region in a direction parallel to the surface. The first base region may be provided on the first buried region. At least a part of the first base region may be exposed on the surface. The first base region may be of the second conductivity type. The gate electrode may be provided above the first base region. In a direction parallel to the depth direction of the gallium nitride layer, the second conductivity type impurity concentration in the first base region may gradually decrease from the upper end of the first buried region toward the surface.

  The first buried region may have a peak of the second conductivity type impurity concentration distribution at a predetermined depth position.

  The gallium nitride semiconductor device may further include a first lower diffusion region. The first lower diffusion region may be in direct contact with the first buried region. The first lower diffusion region may be provided between the first buried region and the gallium nitride single crystal substrate. The first lower diffusion region may have a second conductivity type impurity concentration lower than that of the first buried region. In a direction parallel to the depth direction of the gallium nitride layer, the second conductivity type impurity concentration in the first lower diffusion region gradually decreases from the lower end of the first buried region toward the gallium nitride single crystal substrate. Good.

  In a direction parallel to the depth direction of the gallium nitride layer, the residual defect concentration in the first base region may gradually decrease from the upper end of the first buried region toward the surface.

  The first buried region may have a residual defect concentration peak at a predetermined depth position.

  In a cross-sectional view of the gallium nitride semiconductor device, the gallium nitride layer may further include a second buried region, a second base region, and a drift region. The second buried region may correspond to the first buried region with respect to a line symmetry axis extending in a direction parallel to the depth direction. The second base region may correspond to the first base region with respect to the line symmetry axis. The drift region may include a first conductivity type upper region and a first conductivity type lower region. The upper region may be provided between the first base region and the first buried region and the second base region and the second buried region. The lower region may be provided between the upper region and the gallium nitride single crystal substrate. The first conductivity type impurity concentration in the upper region may be higher than the first conductivity type impurity concentration in the lower region.

  The surface may include an upper end of the first source region, an upper end of the first base region, and an upper end of the upper region in the drift region. The upper end of the first source region, the upper end of the first base region, and the upper end of the upper region in the drift region may constitute one plane.

  The gallium nitride single crystal substrate may be a low dislocation free-standing substrate.

  In a second aspect of the present invention, a method for manufacturing a planar gate type gallium nitride semiconductor device is provided. A method of manufacturing a gallium nitride semiconductor device includes a step of forming a gallium nitride layer, a step of ion-implanting a second conductivity type impurity, a step of forming a first base region of a second conductivity type, The method may comprise the step of ion-implanting the first conductivity type impurity and the step of forming a gate electrode. The gallium nitride layer may be formed on a gallium nitride single crystal substrate. The step of ion-implanting the second conductivity type impurity may be ion implantation for the purpose of forming the first buried region at a predetermined depth position of the gallium nitride layer. In the step of forming the first base region, the first base region may be formed by heat-treating the gallium nitride single crystal substrate and the gallium nitride layer. The step of ion-implanting the first conductivity type impurity may be performed for the purpose of forming a first source region in a region above a predetermined depth position in the gallium nitride layer. The gate electrode may be formed above the first base region. After the step of forming the first base region, the first base region is adjacent to the first source region in a direction parallel to the surface of the gallium nitride layer and located on the first buried region, At least a part of the surface may be exposed. In addition, after the step of forming the first base region, the second conductivity type impurity concentration in the first base region in the direction parallel to the depth direction of the gallium nitride layer is the upper end of the first buried region. It may gradually decrease from to the surface.

  The heat treatment may be a rapid heat treatment. In the rapid heat treatment, the gallium nitride layer may be heated at a predetermined temperature of 1300 ° C. or higher for a time of less than 10 minutes.

  In the rapid heating process, the gallium nitride layer may be heated at a heating rate of several hundred degrees C / min until a predetermined temperature is reached.

  In a cross-sectional view of the gallium nitride semiconductor device, the gallium nitride semiconductor device may further include a second buried region, a second base region, and a first conductivity type drift region. The second buried region may correspond to the first buried region with respect to a line symmetry axis extending in a direction parallel to the depth direction. The second base region may correspond to the first base region with respect to the line symmetry axis. The drift region may include a first conductivity type upper region and a first conductivity type lower region. The upper region may be provided between the first base region and the first buried region and the second base region and the second buried region. The lower region may be provided between the upper region and the gallium nitride single crystal substrate. The method for manufacturing a gallium nitride semiconductor device may further include a step of ion-implanting a first conductivity type impurity in the upper region. By ion-implanting the first conductivity type impurity into the upper region, the first conductivity type impurity concentration in the upper region may be higher than the first conductivity type impurity concentration in the lower region.

  The step of ion-implanting the first conductivity type impurity in the upper region is performed before or after the step of forming the first base region and the second base region by heat-treating the gallium nitride single crystal substrate and the gallium nitride layer. It may be.

  It should be noted that the above summary of the invention does not enumerate all the necessary features of the present invention. In addition, a sub-combination of these feature groups can also be an invention.

FIG. 3 is a top view of the vertical MOSFET 100 in the first embodiment. It is a figure which shows the AA cross section and BB cross section of FIG. It is a figure which shows Mg density | concentration distribution and residual defect distribution in the CC cross section of FIG. 5 is a flowchart showing a manufacturing process of the vertical MOSFET 100. FIG. It is a figure which shows step S210. It is a figure which shows step S220. It is a figure which shows step S225. It is a figure which shows step S230. It is a figure which shows step S240. It is a figure which shows step S250. It is a figure which shows step S260. It is a figure which shows step S265. It is a figure which shows step S270. It is a figure which shows step S280. It is a figure which shows step S290. It is a figure which shows step S300. It is a figure which shows the time change of the heat processing temperature in step S250. These are figures which show the outline | summary of the heat processing apparatus 150. FIG. It is a flowchart which shows the manufacturing process of the vertical MOSFET100 in 2nd Embodiment. It is a figure which shows step S265. It is a figure which shows step S268.

  Hereinafter, the present invention will be described through embodiments of the invention, but the following embodiments do not limit the invention according to the claims. In addition, not all the combinations of features described in the embodiments are essential for the solving means of the invention.

  FIG. 1 is a top view of a vertical MOSFET (Metal Oxide Semiconductor Field Effect Transistor) 100 according to the first embodiment. FIG. 1 is also an XY plan view of the vertical MOSEFT 100. In this example, the X-axis direction and the Y-axis direction are directions perpendicular to each other, and the Z-axis direction is a direction perpendicular to the XY plane. The X, Y, and Z axes form a so-called right-handed system.

  In this example, the positive direction of the Z axis may be referred to as “up” and the negative direction of the Z axis may be referred to as “down”. “Up” and “down” do not necessarily mean a vertical direction with respect to the ground. That is, the “up” and “down” directions are not limited to the direction of gravity. “Upper” and “lower” are merely convenient expressions for specifying a relative positional relationship among regions, layers, films, substrates, and the like.

  The vertical MOSFET 100 of this example has an active region 110 and an edge termination region 130. The active region 110 in this example has a gate pad 112 and a source pad 114. The gate pad 112 and the source pad 114 are electrode pads that are electrically connected to a gate electrode 44 and a source electrode 54 described later, respectively.

  The edge termination region 130 is provided so as to surround the active region 110 in a top view. The edge termination region 130 may have one or more of a guard ring structure, a field plate structure, and a JTE (Junction Termination Extension) structure. The edge termination region 130 may have a function of preventing electric field concentration in the active region 110 by expanding a depletion layer generated in the active region 110 to the edge termination region 130.

  FIG. 2 is a view showing the AA cross section and the BB cross section of FIG. Each of the AA cross section and the BB cross section is a cross section parallel to the YZ plane. The AA cross-section is a partial cross-sectional view of the active region 110, and the BB cross-section is a partial cross-sectional view of the edge termination region 130. The AA cross section shows the structure of the repeating unit of the MOSFET. The structure of the repeating unit of the MOSFET may be repeatedly provided in the Y-axis direction.

  (A-A cross section) The vertical MOSFET 100 of this example has a planar gate type vertical MOSFET in the active region 110. The vertical MOSFET 100 of this example includes a GaN substrate 10, a GaN layer 16, a gate insulating film 42, a gate electrode 44, a source electrode 54 and a drain electrode 56.

The GaN substrate 10 is an example of a GaN single crystal substrate. The GaN substrate 10 may be a first conductivity type substrate. The GaN substrate 10 of this example is an n ⁺ type substrate. The GaN layer 16 may be provided on the GaN substrate 10. The GaN layer 16 of this example is formed epitaxially on the GaN substrate 10. The GaN layer 16 may be a first conductivity type layer. The GaN layer 16 in this example is an n ⁻ type layer.

  In this example, the first conductivity type is n-type and the second conductivity type is p-type. However, in another example, the first conductivity type may be p-type and the second conductivity type may be n-type. Here, n or p means that electrons or holes are majority carriers, respectively. For + or-listed on the right shoulder of n or p, + means that the carrier concentration is higher than that in which it is not described, and-means that the carrier concentration is lower than that in which it is not described.

  The first conductivity type (n-type) impurity for GaN may be one or more elements of Si (silicon), Ge (germanium), and O (oxygen). In this example, Si is used as the n-type impurity. The first conductivity type (p-type) impurity for GaN may be one or more elements of Mg (magnesium), Ca (calcium), Be (beryllium), and Zn (zinc). In this example, Mg is used as the p-type impurity.

In the vertical MOSFET 100 of this example, the semiconductor material is GaN, but the semiconductor material may include one or more elements of aluminum (Al) and indium (In). The semiconductor material may be a mixed crystal semiconductor containing a small amount of Al and In, that is, Al _x In _y Ga _1-xy N (0 ≦ x <1, 0 ≦ y <1). However, the semiconductor material of this example is GaN in which x = y = 0 in Al _x In _y Ga _1-xy N.

The GaN substrate 10 may be a low dislocation free-standing substrate. The GaN substrate 10 of this example is a self-supporting substrate having a threading dislocation density of less than 1E + 7 cm ⁻² . By setting the GaN substrate 10 to a low dislocation density, the dislocation density of the GaN layer 16 formed on the GaN substrate 10 can also be reduced. Furthermore, by using such a low dislocation substrate, leakage current can be reduced even when a large area power device is formed. Thereby, a power device can be manufactured with a high yield rate. Further, it is possible to prevent the ion-implanted impurity from deeply diffusing along the dislocation during the heat treatment.

  In this example, the interface between the GaN layer 16 and the GaN substrate 10 is defined as a boundary 12. In this example, the boundary 12 is the first main surface of the GaN substrate 10. The second main surface of the GaN substrate 10 is a back surface 18 opposite to the boundary 12. In the present example, the first main surface of the GaN layer 16 is the front surface 14 opposite to the boundary 12, and the second main surface of the GaN layer 16 is the boundary 12.

  (Ion implantation region) Impurities may be ion implanted into the GaN layer 16. In this example, the GaN layer 16 has a contact region 25, a source region 26, and a buried region 28, which are regions in which impurities are ion-implanted in a predetermined depth range from the surface 14. That is, the contact region 25, the source region 26 and the buried region 28 are provided in the GaN layer 16.

Mg may be implanted into the contact region 25 and the buried region 28. Each of contact region 25 and buried region 28 may become a second conductivity type region through a heat treatment after ion implantation. Each of the contact region 25 and the buried region 28 in this example becomes p ⁺ type after the heat treatment.

When the buried region 28 is p ⁺ type, the buried region 28 can function as a breakdown voltage structure. For example, when there is no p ⁺ type buried region 28, the depletion layer formed by the pn junction between the base region 23 and the drift region 22 reaches the upper end of the base region 23, so that the breakdown voltage at the gate-off time is increased. May decrease. On the other hand, since the depletion layer can be prevented from reaching the upper end of the base region 23 by providing the buried region 28, the breakdown voltage when the gate is turned off is improved as compared with the case where there is no buried region 28. be able to.

Si may be ion-implanted into the source region 26. Thus, the source region 26 has the first conductivity type impurity. The source region 26 may become a first conductivity type region through a heat treatment after ion implantation. The source region 26 in this example becomes n ⁺ type after the heat treatment. Note that the contact region 25, the source region 26, and the buried region 28 of this example may have a stripe shape extending in the X-axis direction.

  The buried region 28 is located below the bottom of the source region 26. A base region 23 may be located between the bottom of the source region 26 and the top of the buried region 28. The GaN layer 16 of this example includes a first buried region 28-1 and a second buried region 28-2. The second buried region 28-2 may correspond to the first buried region 28-1 with respect to the line symmetry axis 60. The line symmetry axis 60 is an imaginary straight line extending in a direction parallel to the depth direction. The depth direction is a direction parallel to the Z-axis direction. One line symmetry axis 60 may exist in the structure of the repeating unit of the MOSFET. The first buried region 28-1 and the second buried region 28-2 in this example are symmetric with respect to the line symmetry axis 60.

  The source region 26 may provide a path for the electron current to flow. The source region 26 in this example is at least partially exposed to the surface 14. The source region 26 may have a bottom portion and an inner side portion in contact with the base region 23, and an outer side portion in contact with the contact region 25. In this example, a position close to the line symmetry axis 60 in one region may be referred to as the inside, and a position far from the line symmetry axis 60 in the one region may be referred to as the outside. Further, the GaN layer 16 of this example includes a first source region 26-1 and a second source region 26-2 that are symmetrical with respect to the line symmetry axis 60.

  The contact region 25 may have a function of reducing contact resistance with the source electrode 54 and a function of providing a hole extraction path when the gate is off. The contact region 25 of this example is at least partially exposed on the surface 14. The contact region 25 may have an inner side in contact with the source region 26 and the base region 23 and a bottom in contact with the buried region 28. Further, the GaN layer 16 of this example includes a first contact region 25-1 and a second contact region 25-2 that are symmetric with respect to the line symmetry axis 60.

(Thermal diffusion region) The GaN layer 16 of this example further has a base region 23, a side diffusion region 27, and a lower diffusion region 29. That is, the base region 23, the side diffusion region 27, and the lower diffusion region 29 are provided in the GaN layer 16. The base region 23, the side diffusion region 27, and the lower diffusion region 29 in this example are regions formed by diffusing impurities of the second conductivity type in the buried region 28 as a result of heat treatment of the buried region 28. is there. These thermal diffusion regions are second conductivity type regions. In this example, the base region 23, the side diffusion region 27, and the lower diffusion region 29 have a second conductivity type impurity concentration lower than that of the buried region 28. The base region 23, the side diffusion region 27, and the lower diffusion region 29 in this example are p-type or p ^- type.

  Base region 23 is provided on buried region 28. The GaN layer 16 of the present example includes a first base region 23-1 and a second base region 23-2 that are symmetric with respect to the line symmetry axis 60. An upper region that is part of the base region 23 may be exposed on the surface 14. In this example, the upper region is a region corresponding to the channel formation region 24. The upper region (channel formation region 24) in this example is in contact with the gate insulating film 42 on the surface 14.

  The base region 23 in this example includes a channel formation region 24 (upper region) and a lower region located under the source region 26. The side portions inside the upper region and the lower region in the base region 23 are in contact with the drift region 22. Further, the channel forming region 24 of this example may be adjacent to the source region 26 in a direction parallel to the surface 14. The outside of the channel forming region 24 in this example is in contact with the source region 26. Note that the outside of the lower region in this example is in contact with the contact region 25.

  The side diffusion region 27 in this example is adjacent to the buried region 28 in the Y-axis direction. The GaN layer 16 of this example includes a first side diffusion region 27-1 and a second side diffusion region 27-2 that are symmetrical with respect to the line symmetry axis 60, and a first lower diffusion region 29. -1 and a second lower diffusion region 29-2. The side diffusion region 27 is located inside the buried region 28.

  The lower diffusion region 29 of this example is in direct contact with the buried region 28. The lower diffusion region 29 in this example is located between the buried region 28 and the GaN substrate 10. The inner side portions of the base region 23, the side diffusion region 27, and the lower diffusion region 29 are continuously provided boundaries between the thermal diffusion region of the second conductivity type impurity and the drift region 22 of the first conductivity type. 17 may be configured.

The drift region 22 of this example includes an upper region 22-T and a lower region 22-B, each of the first conductivity type. The upper region 22-T and the lower region 22-B in this example are each an n ⁻ type region. The upper region 22-T includes a first base region 23-1, a side diffusion region 27-1, a first buried region 28-1, a first lower diffusion region 29-1, and a second base region. 23-2, the side diffusion region 27-2, the second buried region 28-2, and the second lower diffusion region 29-2. The upper region 22 -T of this example is located between two boundaries 17 provided symmetrically with respect to the line symmetry axis 60. In this example, the upper end of the upper region 22 -T coincides with the surface 14, and the lower end of the upper region 22 -T coincides with the same depth position as the lower end of the lower diffusion region 29.

  The lower region 22 -B may be located between the upper region 22 -T and the GaN substrate 10. The lower region 22-B in this example is located between the lower end of the lower diffusion region 29 and the upper end (that is, the boundary 12) of the GaN substrate 10. The lower region 22-B may be provided over the entire Y-axis direction in the structure of the repeating unit of the MOSFET.

  The gate insulating film 42 may be provided in direct contact with at least the channel formation region 24. The gate insulating film 42 in this example is provided in direct contact with the upper region 22 -T of the drift region 22, the channel formation region 24, and a part of the source region 26. The gate insulating film 42 in this example is provided on the flat surface 14.

  In this example, the flat surface 14 means a surface 14 on which no intentional unevenness is provided by etching for the purpose of providing a gate trench portion or a mesa structure. However, the flat surface 14 may have unevenness of, for example, about 10 nm due to etching and heat treatment of the mask 80 and the cap layer 85 described later. The unevenness may be evaluated by, for example, the maximum height roughness Rz. The maximum height roughness Rz is a graph in which the contour curve is extracted by the reference length L in the direction of the average line of the contour curve showing the unevenness, and the height Rp from the average line to the highest peak and the lowest valley Means the difference from the depth Rv.

  The surface 14 of this example includes the upper end of the source region 26, the upper end of the channel forming region 24, and the upper end of the upper region 22-T. In this example, the upper end of the source region 26, the upper end of the channel forming region 24, the upper end of the upper region 22 -T, and the upper end of the contact region 25 constitute one plane that matches the surface 14. As described above, in this example, since neither the gate trench part nor the mesa part is provided, it is possible to solve the problem that the breakdown voltage is lowered due to the electric field concentration at the corner part of the gate trench part or the corner part of the mesa part. it can.

  The gate electrode 44 may be provided above the base region 23. The gate electrode 44 of this example is provided on at least the channel formation region 24 in direct contact with the gate insulating film 42. More specifically, the gate electrode 44 of this example is provided above the upper region 22 -T, the channel formation region 24, and a part of the source region 26. Thus, the gate electrode 44 of this example is a planar type provided on the flat gate insulating film 42. The gate electrode 44 may be formed of a material different from that of the gate pad 112. In this example, the gate electrode 44 is formed of polysilicon doped with impurities, and the gate pad 112 is formed of Al or an Al—Si alloy.

  The source electrode 54 may be provided on the surface 14. The source electrode 54 in this example is provided in contact with a part of the source region 26 and the contact region 25. The source electrode 54 may also be provided on the gate electrode 44 through an interlayer insulating film. The interlayer insulating film may cover an upper portion and a plurality of side portions of the gate electrode 44 so that the gate electrode 44 is not electrically connected to the source electrode 54.

  Note that the source electrode 54 may be formed of the same material as the source pad 114. In this example, the source electrode 54 made of Al or an Al—Si alloy also serves as the source pad 114. The source electrode 54 may have a barrier metal layer between the surface 14 and the Al layer or Al—Si layer. Titanium (Ti) may be used as a material for the barrier metal layer. That is, the source electrode 54 may be a laminate of a Ti layer and an Al layer, or a laminate of a Ti layer and an Al—Si alloy layer. The drain electrode 56 is provided under the back surface 18 in contact with the back surface 18. The drain electrode 56 may be made of the same material as the source electrode 54.

  The gate terminal, source terminal and drain terminal are denoted by G, D and S, respectively. For example, when a potential equal to or higher than the threshold voltage is applied to the gate electrode 44 through the gate terminal, an inversion layer is formed in the channel formation region 24. When the inversion layer is formed, when a predetermined high potential is applied to the drain electrode 56 and a ground potential is applied to the source electrode 54, a current flows from the drain terminal to the source terminal. Further, when a potential lower than the threshold voltage is applied to the gate electrode 44, the inversion layer in the channel formation region 24 disappears and the current is cut off. Thereby, the vertical MOSFET 100 can switch a current between the source terminal and the drain terminal.

  (BB cross section) The vertical MOSFET 100 of this example has a GaN substrate 10, a GaN layer 16, an electrode 58, a protective film 70, and a drain electrode 56 in an edge termination region 130. The GaN substrate 10 and the GaN layer 16 are provided in common in the edge termination region 130 and the active region 110. That is, a part of the GaN substrate 10 and the GaN layer 16 is the active region 110, and another part of the GaN substrate 10 and the GaN layer 16 is the edge termination region 130. However, the internal structure of the GaN layer 16 in the edge termination region 130 is different from that of the active region 110.

The GaN layer 16 in the edge termination region 130 includes a drift region 22, an upper diffusion region 34, a first doped region 35, a second doped region 36, a side diffusion region 37, a buried region 38 and a lower diffusion region 39. In this example, the first doped region 35, the second doped region 36, and the buried region 38 are regions where Mg ions are implanted. In contrast, the upper diffusion region 34, the side diffusion region 37, and the lower diffusion region 39 are regions formed by heat treatment after ion implantation. In the heat treatment, the buried region 38 may be a p ⁺ -type region, and the first doped region 35, the second doped region 36, the upper diffusion region 34, the side diffusion region 37, and the lower diffusion region 39 may be p-type or p ^−. It may be a mold area.

The upper diffusion region 34 is provided in direct contact with the buried region 38. In the XY plane, the second doped region 36, the first doped region 35, and the upper diffusion region 34 are close to the side end portion of the GaN layer 16 in this order. The first doped region 35 is located between the second doped region 36 and the upper diffusion region 34. The side diffusion region 37 is located on the side of the buried region 38 and is located between the first doped region 35 and the lower diffusion region 39 in the depth direction. The lower diffusion region 39 is in contact with the bottom of the buried region 38 and is located below the bottom.

  The edge termination region 130 of this example has a guard ring structure 74 and a JTE (Junction Termination Extension) structure 78. In this example, the upper diffusion region 34, the side diffusion region 37, the buried region 38, the lower diffusion region 39, and the electrode 58 constitute a guard ring structure 74. The edge termination region 130 may have a plurality of guard ring structures 74 that are spaced apart from each other.

  The electrode 58 is provided in direct contact with the upper diffusion region 34. The electrode 58, the upper diffusion region 34, the side diffusion region 37, the buried region 38, and the lower diffusion region 39 may be provided in a ring shape so as to surround the active region 110 in the XY plane. The electrode 58 may have a ground potential. Due to the guard ring structure 74, the depletion layer in the gate-off state easily spreads to the side end portion of the GaN layer 16. Thereby, the breakdown voltage of the vertical MOSFET 100 can be improved as compared with the case where the guard ring structure 74 is not provided.

  The first doped region 35 and the second doped region 36 constitute a JTE structure 78. In this example, the Mg concentration of the second doped region 36 is lower than the Mg concentration of the first doped region 35. The lower the Mg concentration, the wider the depleted range. By making the Mg concentration of the second doped region 36 close to the side edge of the GaN layer 16 relatively low, the depletion layer in the gate-off state is likely to spread outward. Thereby, the withstand voltage of the vertical MOSFET 100 can be improved as compared with the case without the JTE structure 78.

  FIG. 3 is a diagram showing the Mg concentration distribution and the residual defect distribution in the CC section of FIG. The CC cross section is a cross section parallel to the XZ plane passing through the base region 23 (particularly the channel forming region 24), the buried region 28, the lower diffusion region 29, and the lower region 22-B.

The upper graph is the Mg concentration distribution, and the lower graph is the residual defect distribution. In this example, the Mg concentration distribution means the Mg concentration distribution after the heat treatment. In the Mg concentration distribution, the vertical axis represents the Mg concentration [cm ⁻³ ], and the horizontal axis represents the depth [nm]. Further, in this example, the residual defect distribution means a distribution of residual defect concentration after the heat treatment. Therefore, the vertical axis is the residual defect concentration [cm ⁻³ ], and the horizontal axis is the depth [nm]. The residual defect is, for example, a point defect.

  In this example, the buried region 28 has a p-type impurity concentration distribution peak at a predetermined depth position. The buried region 28 has a peak of residual defect concentration at a predetermined depth position. In this example, the peak depth position of the p-type impurity concentration distribution in the buried region 28 coincides with the peak depth position of the residual defect concentration. That is, since Mg ions are ion-implanted at a predetermined depth position, the Mg concentration distribution and the residual defect distribution have maximum values at the predetermined depth position.

  The p-type impurity concentration in the base region 23 may gradually decrease from the upper end of the buried region 28 toward the surface 14 in a direction parallel to the depth direction of the GaN layer 16. Note that the upper and lower ends of the embedded region 28 in FIG. 3 are indicated by broken lines. Due to the thermal diffusion of the p-type impurity from the buried region 28 to the base region 23, the p-type impurity may gradually decrease in the positive direction of the Z axis.

  Similarly, the residual defect concentration in the base region 23 may gradually decrease from the upper end of the buried region 28 toward the surface 14 in a direction parallel to the depth direction of the GaN layer 16. Due to the thermal diffusion of the p-type impurity from the buried region 28 to the base region 23, the defect may be similarly thermally diffused. Thereby, the residual defect concentration may gradually decrease in the positive direction of the Z axis. Note that the gradual decrease in the impurity concentration or the defect concentration in the Z-axis direction may mean that the impurity concentration or the defect concentration is monotonously decreased in the Z-axis direction.

  As described above, the Mg concentration distribution and the residual defect distribution in this example have a tail region from the upper end of the buried region 28 toward the surface 14. Although details will be described later, the channel formation region 24 having a low Mg concentration and a low defect concentration can be formed by forming the channel formation region 24 by heat treatment (particularly rapid heating treatment) of the buried region 28. .

  Further, the p-type impurity concentration in the lower diffusion region 29 may gradually decrease from the lower end of the buried region 28 toward the GaN substrate 10 in a direction parallel to the depth direction of the GaN layer 16. Due to the thermal diffusion of the p-type impurity from the buried region 28 to the lower region 22 -B of the drift region 22, the p-type impurity may gradually decrease in the negative direction of the Z axis.

  Furthermore, the residual defect concentration in the lower diffusion region 29 may gradually decrease from the lower end of the buried region 28 toward the GaN substrate 10 in a direction parallel to the depth direction of the GaN layer 16. That is, due to the thermal diffusion of the p-type impurity from the buried region 28 to the drift region 22, the defect may be thermally diffused as well. Thereby, the residual defect concentration may gradually decrease in the negative direction of the Z axis.

  In this example, a pn junction is not formed between the buried region 28 and the lower region 22-B having a relatively high residual defect concentration, but the lower diffusion region 29 and the lower region 22 having a relatively low residual defect concentration. A pn junction is formed with -B. Therefore, in this example, a good depletion layer with less leakage current at the time of reverse bias is formed as the lower diffusion region 29 and the lower region 22 compared with the case where a pn junction is formed by the buried region 28 and the lower region 22-B. -B.

  FIG. 4 is a flowchart showing the manufacturing process of the vertical MOSFET 100. The manufacturing process of this example is performed in the order of steps S210 to S300 (that is, in ascending order of numbers).

FIG. 5A is a diagram illustrating step S210. In step S210, the GaN layer 16 is epitaxially formed on the GaN substrate 10. In step S210 of this example, the n-type GaN layer 16 is epitaxially formed on the n ⁺ -type GaN substrate 10 by metal organic growth (MOCVD), halide vapor phase epitaxy (HVPE), or the like. The epitaxially formed GaN layer 16 may have Si of 1E + 15 cm ⁻³ or more and 5E + 16 cm ⁻³ or less. Note that E represents 10 folds. For example, 1E + 15 means 1 × 10 ¹⁵ . The thickness of the GaN layer 16 (that is, the length from the boundary 12 to the surface 14) may be changed according to the breakdown voltage, but is, for example, 1 μm or more and 50 μm or less.

FIG. 5B shows step S220. In step S220 of this example, Mg ions are implanted into a part of the edge termination region 130 in order to form the first doped region 35. In step S220 of this example, Mg ions are implanted into the GaN layer 16 through a mask 80-1 having an opening in a part of the edge termination region 130. The mask 80 may be a silicon dioxide (SiO ₂ ) mask or a photoresist mask that can be selectively removed with respect to the GaN layer 16.

  The acceleration energy of ion implantation may be changed according to the implantation depth. The acceleration energy is proportional to the acceleration voltage. Impurity energy can be increased as the acceleration voltage is increased. The greater the acceleration voltage, the deeper the implantation depth.

In this example, acceleration ions of 10, 20, 40, 70, 110, 150, and 200 (units are keV) and Mg are ion-implanted into the GaN layer 16 by multi-stage implantation with a dose amount of 1E + 12 cm ^{−2 to} 1E + 14 cm ^−2. To do. The implantation depth may range from the surface 14 to 0.4 μm. The mask 80-1 may be removed after the ion implantation. In other processes, the mask 80 may be removed after the ion implantation.

  FIG. 5C is a diagram illustrating step S225. In step S225 of this example, Mg ions are implanted into another part of the edge termination region 130 in order to form the second doped region. More specifically, Mg is ion-implanted into the GaN layer 16 through a mask 80-2 having an opening in the other part of the edge termination region 130 adjacent to the first doped region 35 in the positive Y-axis direction. . The acceleration voltage and implantation depth in step S225 are the same as in step S220, but the dose in step S225 may be smaller than in step S220. Thereby, the Mg concentration of the second doped region 36 is made lower than that of the first doped region 35. In another example, step S225 may be performed first, and then step S220 may be performed.

FIG. 5D is a diagram illustrating step S230. In step S230, Mg is ion-implanted at a predetermined depth position of the GaN layer 16 in order to form the buried region 28 of the active region 110 and the buried region 38 of the edge termination region 130. In step S230 of this example, the buried region 28 and the buried region 38 are simultaneously formed by ion implantation. In this example, Mg is ion-implanted into the GaN layer 16 through the mask 80-3 under the conditions of an acceleration voltage of 250 keV to 500 keV and a dose of 1E + 14 cm ^{−2 to} 1E + 15 cm ⁻² . The implantation depth may be in the range from 0.3 μm to 0.5 μm from the surface 14.

  Note that the acceleration voltage and the dose are the minimum necessary conditions for forming the buried region 28 and the buried region 38. Step S230 may further include ion implantation with an acceleration voltage and a dose other than those described above. The ion implantation in step S230 may be multi-stage implantation. That is, the ion implantation in step S230 may be multiple ion implantations with different acceleration voltages and doses, rather than a single ion implantation under a predetermined condition. Thereby, the thickness of the buried region 28 and the buried region 38 can be controlled.

  FIG. 5E shows step S240. In step S240 of this example, a first cap layer 85-1 is formed on the entire surface 14 of the GaN layer 16. In this example, the stack of the GaN substrate 10, the GaN layer 16, and the cap layer 85 may be referred to as a stack 90.

  The cap layer 85 may have a function of preventing nitrogen atoms from being released from the GaN layer 16 during the heat treatment. Nitrogen vacancies are formed at positions where nitrogen atoms are released from the GaN layer 16. Nitrogen vacancies can function as donor-type defects, so that the expression of p-type characteristics may be inhibited. In this example, in order to prevent this, a cap layer 85 that is in direct contact with the surface 14 of the GaN layer 16 is provided.

  The cap layer 85 has high heat resistance, good adhesion to the surface 14, impurities do not diffuse from the cap layer 85 to the GaN layer 16, and can be selectively removed from the GaN layer 16. It is desirable. High heat resistance of the cap layer 85 means that the cap layer 85 is not substantially decomposed to such an extent that no pits (through openings) are formed in the cap layer 85 even when heat-treated at a temperature of 1100 ° C. or higher and 1400 ° C. or lower. Means that.

The cap layer 85 in this example is an AlN layer, but may be a silicon dioxide (SiO ₂ ) layer or a silicon nitride (SiN) layer. However, the AlN layer is desirable to eliminate the possibility of Si or O diffusing into the GaN layer 16. The cap layer 85 may further include one or more of a SiO ₂ layer, a SiN layer, and a GaN layer on the AlN layer. In this case, the AlN layer may function also as an n-type impurity diffusion prevention layer.

  FIG. 5F is a diagram illustrating step S250. In step S250 of this example, the laminated body 90-1 is heat-treated at a temperature of 1300 ° C. or higher and 1400 ° C. or lower using the heat treatment apparatus 150. As will be described later, step S250 is a rapid heating process.

By heat treatment in step S250, Mg is thermally diffused from the buried region 28 to form the p-type or p ^- type base region 23, the side diffusion region 27, and the lower diffusion region 29, respectively. Similarly, Mg is thermally diffused from the buried region 38 to form the upper diffusion region 34, the side diffusion region 37 and the lower diffusion region 39. Further, the impurities in the buried region 28 and the buried region 38 are activated, and defects caused by ion implantation can be recovered to some extent.

FIG. 5G shows step S260. In this example, step S260 is a step of ion-implanting Mg to form the contact region 25. In this example, through a mask 80-4, accelerating voltage 10,20,40,70,110,150 and 200 (in units of keV), and, by a multistage injection follows dose 1E + 15cm ^-2 least 1E + 16cm ^-2 Mg ions are implanted into the GaN layer 16 in the active region 110. The implantation depth may be in the range from 0.05 μm to 0.1 μm from the surface 14. The mask 80-4 may be removed after the ion implantation.

FIG. 5H is a diagram illustrating step S265. In step S265 of this example, n-type impurities are ion-implanted into the GaN layer 16 in order to form the source region 26 in a region above the buried region 28. In this example, the acceleration voltage of 10, 20, 40, 70, 110 and 150 (all units are keV) and multi-stage implantation with a dose of 1E + 15 cm ⁻² or more and 1E + 16 cm ⁻² or less through the mask 80-5, Si Are ion-implanted into the GaN layer 16 in the active region 110.

  FIG. 5I is a diagram illustrating step S270. In step S270 of this example, a second cap layer 85-2 is formed. The second cap layer 85-2 may be the same material and configuration as the first cap layer 85-1. The second cap layer 85-2 is also formed on the entire surface 14 of the GaN layer 16. Thereby, the laminated body 90-2 is formed.

  FIG. 5J shows step S280. In step S280 of this example, the laminated body 90-2 is heat-treated using the heat treatment apparatus 150 at a temperature lower than that in step S250. The heat treatment in step S280 may not be rapid heat treatment. In step S280, the stacked body 90-2 may be heat-treated at a temperature of 1100 ° C. or higher and 1200 ° C. or lower for 5 minutes. As a result, the impurities in the contact region 25 and the source region 26 can be activated, and defects caused by ion implantation can be recovered to some extent.

  In this example, the heat treatment is performed in two steps, S250 and S280. However, in another example, the heat treatment in steps S250 and S280 may be performed by one heat treatment. In the other example, step S230, step S260 and step S265 of this example are executed, and thereafter step S240 and step S250 are executed. Thereby, step S270 and step S280 of this example can be omitted, which is advantageous in terms of the number of manufacturing steps, manufacturing time, and manufacturing cost.

FIG. 5K shows step S290. In step S290 of this example, a gate insulating film 42 that covers at least the base region 23 exposed on the surface 14 is formed. First, an insulating film is formed by chemical vapor deposition (CVD), and then the insulating film is formed into a predetermined shape through photolithography and etching processes. Thereby, the gate insulating film 42 may be formed. The gate insulating film 42 may have a thickness of 100 nm. The gate insulating film 42 may be a SiO ₂ film or an aluminum oxide (Al ₂ O ₃ ) film.

  FIG. 5L is a diagram illustrating step S300. In step S300 of this example, the gate electrode 44, the source electrode 54, the drain electrode 56, the electrode 58, and the protective film 70 are formed. The protective film 70 is a passivation film. The gate electrode 44, the source electrode 54, the electrode 58, and the drain electrode 56 may be formed through sputtering, photolithography, etching, and the like.

The protective film 70 may cover the GaN layer 16 exposed on the surface 14 in the edge termination region 130. Thereby, impurities can be prevented from entering from the surface 14. The protective film 70 in this example is a SiO ₂ film. In this example, an interlayer insulating film is formed on the gate electrode 44 and the gate pad 112 electrically connected to the gate electrode 44 is formed. Thereby, the vertical MOSFET 100 is completed.

  FIG. 6 is a diagram showing a temporal change in the heat treatment temperature in step S250. The vertical axis is temperature [° C.], and the horizontal axis is time. The heat treatment in step S250 is a rapid heat treatment. In the rapid heat treatment of this example, the heat treatment time at the target temperature is a short time of several tens of seconds to several minutes. In one example, in the heat treatment in step S250, the laminate 90-1 may be heated at a predetermined temperature of 1300 ° C. or higher for a time of less than 10 minutes.

  Between the time t0 and the time t1, the temperature inside the heat treatment furnace of the heat treatment apparatus 150 in which the laminate 90-1 is arranged may be raised at several hundred degrees C / min. Thereby, the laminated body 90-1 is heated at a heating rate of several hundred degrees C / min until reaching a predetermined temperature. In this example, the temperature inside the heat treatment furnace is raised at a temperature of 200 ° C. to 400 ° C. per minute. In this example, by rapid heating in this way, it is possible to suppress the p-type impurity from being captured by the defect cluster as described later.

  Thereafter, the temperature inside the heat treatment furnace may be maintained at a constant temperature from time t1 to time t2. However, the constant temperature may include a fluctuation of about ± 25 ° C. In this example, the temperature inside the heat treatment furnace is maintained at a predetermined temperature of 1300 ° C. or higher and lower than 1400 ° C. for 5 minutes, or the temperature inside the heat treatment furnace is maintained at 1400 ° C. for 30 seconds. Thereafter, during the time t2 to the time t3, the temperature inside the heat treatment furnace may be decreased at several hundred degrees C / min. Thereby, the rapid heating process of step S250 is completed.

  In this example, the Mg in the buried region 28 and the buried region 38 can be thermally diffused by heat treatment at a high temperature of 1300 ° C. or higher and 1400 ° C. or lower. According to the knowledge of the inventors of the present application, it is considered that Mg does not thermally diffuse from the buried region 28 and the buried region 38 at a temperature of about 1100 ° C.

In this example, the laminate 90-1 is rapidly heated in a short time of several tens of seconds to several minutes. On the other hand, when the stacked body 90-1 is heat-treated at a predetermined temperature of 700 ° C. or higher and 1100 ° C. or lower for a long time of about 1 hour, defects in the GaN layer 16 are aggregated to form clusters. There is a risk of forming. Defects in the GaN layer 16 include V _Ga which is a gallium (Ga) vacancy and V _N which is a nitrogen (N) vacancy. Further, the cluster of defects in GaN layer 16, a complex defects of one of _{V Ga} and one _{V N V} Ga _V N, one _{V Ga} and consisting of two _{V N} complex defects _V Ga _{(V N 2} ) etc.

Once the defect cluster is supplemented with the p-type impurity, it becomes difficult for the p-type impurity to escape from the cluster. As a result, the thermal diffusion of the p-type impurity is hindered, so that it becomes difficult to form the p-type or p ⁻ -type base region 23 or the like by the thermal diffusion. On the other hand, in this example, since the stacked body 90-1 is subjected to the rapid heat treatment, the p-type impurities can be thermally diffused before the p-type impurities are captured by the clusters.

  FIG. 7 is a diagram showing an outline of the heat treatment apparatus 150. In step S250 and step S280, heat treatment may be performed using the heat treatment apparatus 150. The heat treatment apparatus 150 of this example includes a control unit 160, a power supply unit 170, a heat treatment furnace 200, a shutter unit 210, and an elevating unit 220. The Z-axis direction in FIG. 7 is the same as the Z-axis direction in FIGS.

  The heat treatment furnace 200 of this example is an electric heat treatment furnace. The control unit 160 controls the power input to the heat treatment furnace 200 by sending a control signal to the power supply unit 170. Thereby, the control unit 160 can determine the temperature inside the heat treatment furnace 200. The control unit 160 may make the input power constant with respect to time, and may increase or decrease the input power with respect to time.

  The heat treatment furnace 200 may have a predetermined temperature distribution in the Z-axis direction. When electric power is supplied to the heat treatment furnace 200, the temperature distribution inside the heat treatment furnace 200 may become higher in the positive direction of the Z axis. For convenience of explanation, in the heat treatment furnace 200, the uppermost position where the stacked body 90 can be arranged is P1, and the lowermost position is P4. The temperature inside the heat treatment furnace 200 may increase as it goes from P4 to P1.

  The heat treatment apparatus 150 of this example controls the heat treatment temperature of the stacked body 90 according to the position of the stacked body 90 (for example, P1 to P4). For example, the temperature of the stacked body 90 is 1100 ° C. at the position P4, and the temperature of the stacked body 90 is 1200 ° C. at the position P3. Moreover, the temperature of the laminated body 90 is 1300 degreeC in the position P2, and the temperature of the laminated body 90 is 1400 degreeC in the position P1.

  The control unit 160 may control opening and closing of the shutter unit 210. The shutter unit 210 includes a shutter 214 and a drive unit 212. The drive unit 212 opens and closes the shutter 214 in response to a command from the control unit 160.

  The controller 160 may also control the operation of the drive unit 180 in the elevating unit 220. The drive unit 180 moves the stage 182 parallel to the Z-axis direction. Thereby, the tray 184 and the laminated body 90 can move in the Z-axis direction. The tray 184 is provided at the end of the stage 182 in the positive direction of the Z axis, and the stacked body 90 is placed on the tray 184.

  When the shutter 214 is open, the tray 184 may enter and exit the heat treatment furnace 200 in the Z-axis direction. In addition, when the shutter 214 is in the closed state, the tray 184 may be stationary inside the heat treatment furnace 200 and may move in the Z-axis direction inside the heat treatment furnace 200.

  The specific procedure of the heat treatment in step S250 and step S280 is as follows, for example. First, the shutter 214 is opened. Thereafter, the tray 184 on which the stacked body 90 is placed is positioned inside the heat treatment furnace 200. Thereafter, the shutter 214 is closed. Then, the laminated body 90 is heat-treated by positioning the laminated body 90 at a position in the Z-axis direction (for example, P1 to P4) corresponding to the target temperature for a predetermined time.

In the heat treatment in step S250, the laminated body 90 is heat-treated at a temperature of 1300 ° C. or higher and 1400 ° C. or lower at a predetermined position between the position P2 and the position P1. Further, in the heat treatment in step S280, the laminated body 90 is heat-treated at a temperature of 1100 ° C. or more and 1200 ° C. or less at a predetermined position between the position P4 and the position P3. Note that when heat treatment is performed, the heat treatment furnace 200 may be filled with a gas containing nitrogen (N ₂ ) and ammonia (NH ₃ ). After the heat treatment, the shutter 214 is opened and the stacked body 90 and the tray 184 are moved to the driving unit 212.

  FIG. 8 is a flowchart showing a manufacturing process of the vertical MOSFET 100 in the second embodiment. In the second embodiment, the range in the Y-axis direction of the base region 23, the side diffusion region 27, and the lower diffusion region 29 formed in step S265 is wider than that in the first embodiment. In addition, the second embodiment further includes S268 between step S265 and step S270. In that respect, unlike the first embodiment, the other points are the same as in the first embodiment.

  FIG. 9A shows step S265. Step S265 is a step of ion-implanting n-type impurities into the GaN layer 16. However, in this example, the upper region 22 -T of the drift region 22 disappears due to the base region 23 and the like being formed by heat-treating the stacked body 90-1. That is, the base region 23-1 and the base region 23-2 are connected to each other in the Y-axis direction. The side diffusion region 27-1 and the side diffusion region 27-2, and the lower diffusion region 29-1 and the lower diffusion region 29-2 are also connected to each other in the Y-axis direction.

  FIG. 9B shows step S268. In the step S268 of this example, the upper region 22-T is formed through the mask 80-6 so that the n-type impurity concentration of the upper region 22-T is higher than the n-type impurity concentration of the lower region 22-B. Si is ion-implanted.

  When the p-type impurity is thermally diffused to the line symmetry axis 60 and the n-type upper region 22-T disappears as in step S265 of this example, the vertical MOSFET 100 cannot be turned on. Even if the upper region 22-T does not disappear, the on-resistance of the vertical MOSFET 100 increases when the width in the Y-axis direction becomes narrow. Therefore, in this example, n-type impurities are ion-implanted in a region near the line symmetry axis 60 and above the lower end of the lower diffusion region 29 in order to prevent malfunction or increase in on-resistance. Thereby, the p-type diffusion region diffused to the position of the line symmetry axis 60 is counter-doped. An n-type upper region 22-T is formed by heat treatment after the counter-doping.

  When the n-type upper region 22-T is formed by counter doping, the n-type impurity concentration of the upper region 22-T may be higher than the n-type impurity concentration of the lower region 22-B. That is, n-type impurities may be further added to the upper region 22-T by counter doping in addition to the n-type impurity concentration at the time of epitaxial formation. As a result, the drift region 22 in contact with the channel formation region 24 is secured, so that an increase in on-resistance can be prevented as compared with the case where no counter-doping is performed.

  When the n-type upper region 22-T is formed by counter doping, the n-type impurity concentration distribution of the upper region 22-T is a BOX type profile having a region where the n-type impurity concentration distribution is flat in the depth direction. It's okay.

  Instead, the n-type impurity concentration distribution in the upper region 22-T may have a peak in the depth direction. The depth position of the peak may be located at a specific depth within the depth range where the buried region 28 is provided. The depth range in which the buried region 28 is provided is considered to be relatively high in p-type impurities in the upper region 22-T. In the example in which the peak is provided, the peak of the n-type impurity concentration distribution is provided in the depth range in which the buried region 28 is provided, as compared with the case where the upper region 22-T is made relatively high in the entire depth direction. As a result, the substantial carrier concentration in the depth direction of the buried region 28 can be made constant.

  In this example, the side diffusion region 27 remains, but in another example, the side diffusion region 27 may be extinguished by expanding the opening of the mask 80-6 as compared with this example and performing ion implantation. In still another example, by performing the ion implantation in step S268 before step S250, the n-type impurity concentration in the region corresponding to the upper region 22-T may be increased in advance before the heat treatment. Good.

  In the second embodiment, n-type impurities are ion-implanted into the upper region 22-T after the step of heat-treating the stacked body 90-1 (S250) (S268). However, n-type impurities may be ion-implanted into a region corresponding to the upper region 22-T “before” the step of heat-treating the stacked body 90-1 (S250). That is, an n-type impurity having a predetermined concentration may be ion-implanted into a region corresponding to the upper region 22-T before the heat treatment step (S250). The predetermined concentration may be determined in consideration of the degree of diffusion of the p-type impurity. By making the n-type impurity concentration in the region corresponding to the upper region 22-T relatively high in advance, it is possible to prevent the upper region 22-T from disappearing immediately after the heat treatment step (S250).

  As described in the first embodiment, in other examples of the second embodiment, the heat treatment is not divided into two steps, S250 and S280, and the heat treatment in steps S250 and S280 is performed by a single heat treatment. May be executed. In the other example, step S230, step S260, step S265, and step S268 of this example are executed, and thereafter step S240 and step S250 are executed. Thereby, step S270 and step S280 of this example can be omitted, which is advantageous in terms of the number of manufacturing steps, manufacturing time, and manufacturing cost.

  As mentioned above, although this invention was demonstrated using embodiment, the technical scope of this invention is not limited to the range as described in the said embodiment. It will be apparent to those skilled in the art that various modifications or improvements can be added to the above embodiment. It is apparent from the description of the scope of claims that embodiments with such changes or improvements can be included in the technical scope of the present invention.

  The order of execution of each process such as operations, procedures, steps, and stages in the apparatus, system, program, and method shown in the claims, the description, and the drawings is particularly “before” or “prior to”. It should be noted that the output can be realized in any order unless the output of the previous process is used in the subsequent process. Even if the operation flow in the claims, the description, and the drawings is described using “first”, “next”, etc. for convenience, it means that it is essential to carry out in this order. It is not a thing.

  10 .. GaN substrate, 12 .. boundary, 14 .. surface, 16 .. GaN layer, 17 .. boundary, 18 .. back surface, 22 .. drift region, 22-T. -Lower region, 23-Base region, 24-Channel formation region, 25-Contact region, 26-Source region, 27-Side diffusion region, 28-Buried region, 29-Lower diffusion region 34 .. Upper diffusion region 35 .. First doped region 36 .. Second doped region 37 .. Side diffusion region 38 .. Buried region 39 .. Lower diffusion region 42 .. Gate Insulating film, 44..Gate electrode, 54..Source electrode, 56..Drain electrode, 58..Electrode, 60..Axis of symmetry, 70..Protective film, 74..Guard ring structure, ..JTE Structure, 80 ... Mask, 85 ... Cap layer, 90 ... Layer body, 100 ... Vertical MOSFET, 110 ... Active region, 112 ... Gate pad, 114 ... Source pad, 130 ... Edge termination region, 150 ... Heat treatment device, 160 ... Control unit, 170 ... Power supply unit, 180 ... drive unit, 182 ... stage, 184 ... tray, 200 ... heat treatment furnace, 210 ... shutter unit, 212 ... drive unit, 214 ... shutter, 220 ... lift unit

Claims (11)

A planar gate type gallium nitride semiconductor device,
The gallium nitride semiconductor device has an active region and an edge termination region provided to surround the active region in a top view of the gallium nitride semiconductor device,
The active region is
A gallium nitride single crystal substrate;
A gallium nitride layer on the gallium nitride single crystal substrate;
A first source region of a first conductivity type provided in the gallium nitride layer and exposed at least partially on the surface of the gallium nitride layer;
A first buried region provided in the gallium nitride layer below the bottom of the first source region and having a second conductivity type impurity;
A first base region of a second conductivity type adjacent to the first source region in a direction parallel to the surface, provided on the first buried region, and at least partially exposed to the surface;
A gate electrode provided above the first base region,
The edge termination region comprises the gallium nitride single crystal substrate and the gallium nitride layer,
The edge termination region has a third buried region and an upper diffusion region provided on and in contact with the third buried region in the gallium nitride layer,
In the depth direction parallel to the direction of the gallium nitride layer, wherein the first second-conductivity-type impurity concentration in the base region of the is an monotonically decreasing gradually decreases from the upper end of the first buried region to said surface ,
In the depth direction parallel to the direction of the gallium nitride layer, a second conductivity type impurity concentration of the upper diffusion region is a monotonically decreasing gradually decreases from the upper end of the third buried region to the surface <br A gallium nitride semiconductor device. The gallium nitride semiconductor device according to claim 1, wherein the first buried region has a peak of a second conductivity type impurity concentration distribution at a predetermined depth position. A second conductivity type impurity concentration that is in direct contact with the first buried region and is provided between the first buried region and the gallium nitride single crystal substrate and is lower than the first buried region; Further comprising a first lower diffusion region having
In a direction parallel to the depth direction of the gallium nitride layer, the second conductivity type impurity concentration in the first lower diffusion region is from the lower end of the first buried region toward the gallium nitride single crystal substrate. The gallium nitride semiconductor device according to claim 1, which gradually decreases. The residual defect concentration in the first base region gradually decreases from the upper end of the first buried region toward the surface in a direction parallel to the depth direction of the gallium nitride layer. The gallium nitride semiconductor device according to any one of the above. 5. The gallium nitride semiconductor device according to claim 1, wherein the first buried region has a peak of residual defect concentration at a predetermined depth position. 6. In a cross-sectional view of the gallium nitride semiconductor device, the gallium nitride layer is
A second buried region corresponding to the first buried region with respect to a line symmetry axis extending in a direction parallel to the depth direction;
A second base region corresponding to the first base region with respect to the line symmetry axis;
An upper region of a first conductivity type provided between the first base region and the first buried region and the second base region and the second buried region; the upper region; A drift region including a lower region of the first conductivity type provided between the gallium nitride single crystal substrate,
6. The gallium nitride semiconductor device according to claim 1, wherein a first conductivity type impurity concentration of the upper region is higher than a first conductivity type impurity concentration of the lower region. The surface includes an upper end of the first source region, an upper end of the first base region, and an upper end of the upper region in the drift region;
The gallium nitride semiconductor according to claim 6, wherein the upper end of the first source region, the upper end of the first base region, and the upper end of the upper region in the drift region form one plane. apparatus. The gallium nitride semiconductor device according to claim 1, wherein the gallium nitride single crystal substrate is a low dislocation self-standing substrate. A method of manufacturing a planar gate type gallium nitride semiconductor device having an active region and an edge termination region provided surrounding the active region in a top view,
Forming a gallium nitride layer on the gallium nitride single crystal substrate;
A second conductivity type impurity is ion-implanted to form a first buried region in the active region and a third buried region in the edge termination region at a predetermined depth position of the gallium nitride layer. Stages,
Forming a second conductivity type first base region and a second conductivity type upper diffusion region by heat-treating the gallium nitride single crystal substrate and the gallium nitride layer;
Ion-implanting a first conductivity type impurity into the gallium nitride layer to form a first source region in a region of the gallium nitride layer above the predetermined depth position;
Forming a gate electrode above the first base region;
With
After the step of forming the first base region,
The first base region is adjacent to the first source region in a direction parallel to the surface of the gallium nitride layer, is located on the first buried region, and at least a part of the first base region is exposed to the surface. And
In a direction parallel to the depth direction of the gallium nitride layer, the second conductivity type impurity concentration in the first base region gradually decreases from the upper end of the first buried region toward the surface. ,
The upper diffusion region is provided in contact with the third buried region;
In a direction parallel to the depth direction of the gallium nitride layer, the second conductivity type impurity concentration in the upper diffusion region gradually decreases from the upper end of the third buried region toward the surface,
The heat treatment is performed by heating the gallium nitride layer at a heating rate of several hundred degrees C / min until the predetermined temperature is reached, and at a predetermined temperature of 1300 ° C. or more for a time of less than 10 minutes, It is a rapid heat treatment that heats the gallium nitride layer.
Method for producing a gallium nitride semiconductor device. In a cross-sectional view of the gallium nitride semiconductor device, the gallium nitride semiconductor device is
A second buried region corresponding to the first buried region with respect to a line symmetry axis extending in a direction parallel to the depth direction;
A second base region corresponding to the first base region with respect to the line symmetry axis;
An upper region of a first conductivity type provided between the first base region and the first buried region and the second base region and the second buried region; the upper region; A drift region including a lower region of the first conductivity type provided between the gallium nitride single crystal substrate,
The method for manufacturing the gallium nitride semiconductor device includes:
10. The method of claim 9 , further comprising ion-implanting a first conductivity type impurity in the upper region such that a first conductivity type impurity concentration in the upper region is higher than a first conductivity type impurity concentration in the lower region. The manufacturing method of the gallium nitride semiconductor device of description. The step of ion-implanting the first conductivity type impurity into the upper region includes forming the first base region and the second base region by heat-treating the gallium nitride single crystal substrate and the gallium nitride layer. The method of manufacturing a gallium nitride semiconductor device according to claim 10 , before or after the step.

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