JP2020047655A - Gallium nitride semiconductor device and manufacturing method of gallium nitride semiconductor device - Google Patents

Abstract

To provide a gallium nitride semiconductor device capable of improving the characteristics while restraining reduction of withstand voltage, and to provide a manufacturing method of the gallium nitride semiconductor device.SOLUTION: A gallium nitride semiconductor device includes a GaN layer 16, an N-type source region 26 provided in the GaN layer 16, and a P-type impurity region 2 provided in the GaN layer 16, and adjoining the source region 26 in an X-axis direction and a Y-axis direction parallel with a surface 16a of the GaN layer 16, and in a Z-axis direction intersecting the surface 16a. In the Z-axis direction, the impurity region 2 has an Mg peak position 28P where the density of Mg is highest. An Mg peak depth D1 is 200 nm or more and 1,500 nm or less. An Mg peak density is 1×10cmor more and 1×10cmor less. A surface Mg concentration is 1×10cmor more and 3×10cmor less.SELECTED DRAWING: Figure 2

Description

  The present invention relates to a gallium nitride semiconductor device and a method for manufacturing a gallium nitride semiconductor device.

Conventionally, it has been known to provide a gate trench portion by partially removing an epitaxially formed P ⁻ -type gallium nitride (hereinafter, GaN) layer (for example, see Non-Patent Document 1). It is also known that a P ^- type GaN layer is partially removed to form a mesa portion of the GaN layer, and a field plate is formed on a side portion and a bottom portion of the mesa portion (for example, see Non-Patent Documents). 1). Patent Documents 1 and 2 disclose that magnesium (hereinafter, Mg) is partially ion-implanted into a GaN layer, and then the diffusion region is made P-type by thermally diffusing Mg. Further, Patent Document 2 describes that by not providing a gate trench portion and a mesa portion in a GaN layer, an electric field is prevented from being concentrated on a corner portion and a withstand voltage is prevented from being reduced. I have.

JP 2007-258578 A Japanese Patent No. 6327379

Tohru Oka et al. , "Vertical GaN-based trench metal oxide semiconductor field-effect transistors on a free-standing GaN substrate with blocking voltage of 1.6 kV", Applied Physics Express, published 28 January 2014, Volume 7, Number 2,021002

  A gallium nitride semiconductor device capable of improving characteristics while suppressing a decrease in withstand voltage has been desired.

  The present invention has been made in view of the above problems, and has as its object to provide a gallium nitride semiconductor device and a method for manufacturing a gallium nitride semiconductor device capable of improving characteristics while suppressing a decrease in breakdown voltage. And

To solve the above problem, a gallium nitride semiconductor device according to one embodiment of the present invention includes a gallium nitride layer, a first conductivity type source region provided in the gallium nitride layer, and a first gallium nitride layer provided in the gallium nitride layer. And a second conductivity type impurity region adjacent to the source region in the second direction and the second direction. The first direction is a direction parallel to the surface of the gallium nitride layer. The second direction is a direction that intersects the first direction and the surface of the gallium nitride layer. In the second direction, the impurity region has a peak position where the concentration of the impurity of the second conductivity type is the highest. The depth from the surface of the gallium nitride layer to the peak position is 200 nm or more and 1500 nm or less. The concentration of the impurity of the second conductivity type at the peak position is from 1 × 10 ¹⁷ cm ^{−3 to} 1 × 10 ¹⁹ cm ⁻³ . The concentration of the second conductivity type impurity on the surface of the impurity region is 1 × 10 ¹⁶ cm ⁻³ or more and 3 × 10 ¹⁸ cm ⁻³ or less.

A method for manufacturing a gallium nitride semiconductor device according to one embodiment of the present invention includes a gallium nitride layer, a first conductivity type source region provided in the gallium nitride layer, and a first direction and a second direction provided in the gallium nitride layer. And a second conductivity type impurity region adjacent to the source region. The method for manufacturing a gallium nitride semiconductor device includes a step of ion-implanting a second conductivity type impurity into a gallium nitride layer, and performing a heat treatment on the gallium nitride layer into which the second conductivity type impurity is implanted. Forming an impurity region. In the step of ion-implanting the impurity of the second conductivity type, the implantation peak position of the impurity of the second conductivity type has a depth of 200 nm or more and 1500 nm or less from the surface of the gallium nitride layer, and the implantation concentration at the implantation peak position is 1 × 10 5. ^The ion implantation conditions are set so as to be ¹⁷ or more and 1 × 10 ¹⁹ cm ⁻³ or less.

  According to the present invention, it is possible to provide a gallium nitride semiconductor device and a method for manufacturing the gallium nitride semiconductor device, which are capable of improving the characteristics of an element while suppressing a decrease in breakdown voltage.

FIG. 1 is a plan view showing a configuration example of a gallium nitride semiconductor device according to an embodiment of the present invention. FIG. 2 is a cross-sectional view illustrating a configuration example of the vertical MOSFET according to the embodiment of the present invention. FIG. 3 is a cross-sectional view illustrating a configuration example of the edge termination region of the GaN semiconductor device according to the embodiment of the present invention. FIG. 4 is a cross-sectional view illustrating a method of manufacturing the vertical MOSFET according to the embodiment of the present invention in the order of steps. FIG. 5 is a cross-sectional view illustrating a method of manufacturing the vertical MOSFET according to the embodiment of the present invention in the order of steps. FIG. 6 is a cross-sectional view illustrating a method of manufacturing the vertical MOSFET according to the embodiment of the present invention in the order of steps. FIG. 7 is a cross-sectional view illustrating a method of manufacturing the vertical MOSFET according to the embodiment of the present invention in the order of steps. FIG. 8 is a cross-sectional view illustrating a method of manufacturing the vertical MOSFET according to the embodiment of the present invention in the order of steps. FIG. 9 is a cross-sectional view illustrating a method of manufacturing the vertical MOSFET according to the embodiment of the present invention in the order of steps. FIG. 10 is a graph showing the distribution of Mg concentration in the depth direction of the GaN layer (before heat treatment). FIG. 11 is a graph showing the distribution of Mg concentration in the depth direction of the GaN layer (after heat treatment). FIG. 12 is a graph showing the relationship between the surface Mg concentration of the GaN layer and the threshold. FIG. 13 is a cross-sectional view illustrating a configuration of a vertical MOSFET according to a modification of the embodiment of the present invention. FIG. 14 is a cross-sectional view illustrating a method for manufacturing a vertical MOSFET according to a modification of the embodiment of the present invention. FIG. 15 is a graph schematically showing the distribution of Mg concentration (before and after heat treatment) in the depth direction of the GaN layer into which Mg has been injected in multiple stages.

  Hereinafter, embodiments of the present invention will be described. In the following description of the drawings, the same or similar parts are denoted by the same or similar reference numerals. However, it should be noted that the drawings are schematic, and the relationship between the thickness and the planar dimension, the ratio of the thickness of each device and each member, and the like are different from actual ones. Therefore, specific thicknesses and dimensions should be determined in consideration of the following description. In addition, it is needless to say that dimensional relationships and ratios are different between drawings.

  In the following description, the positive direction of the Z axis may be referred to as “up”, and the negative direction of the Z axis may be referred to as “down”. “Up” and “down” do not necessarily mean a direction perpendicular to the ground. That is, the directions “up” and “down” are not limited to the direction of gravity. The terms “above” and “below” are merely convenient expressions for specifying a relative positional relationship in a region, a layer, a film, a substrate, and the like, and do not limit the technical idea of the present invention. For example, if the paper is rotated by 180 degrees, it is needless to say that “upper” becomes “lower” and “lower” becomes “upper”.

  In the following description, a case where the first conductivity type is N-type and the second conductivity type is P-type will be exemplified. However, the conductivity types may be selected in the opposite relationship, and the first conductivity type may be P-type and the second conductivity type may be N-type. In addition, + or-added to P or N means that the semiconductor region has a relatively higher or lower impurity concentration than a semiconductor region to which + or-is not added. However, even if the semiconductor regions have the same P and P, this does not mean that the impurity concentration of each semiconductor region is exactly the same.

(Configuration example of GaN semiconductor device)
FIG. 1 is a plan view showing a configuration example of a gallium nitride semiconductor device (hereinafter, a GaN semiconductor device) according to an embodiment of the present invention. FIG. 1 is an XY plan view. For example, the first direction (the X-axis direction and the Y-axis direction) is a direction parallel to a first main surface 10a of the GaN substrate 10 described later. The second direction (Z-axis direction) is a direction orthogonal to the first main surface 10a, and is a thickness direction of the GaN semiconductor device 100. The X-axis direction, the Y-axis direction, and the Z-axis direction are orthogonal to each other.

  As shown in FIG. 1, the GaN semiconductor device 100 has an active region 110 and an edge termination region 130. The active region 110 has a gate pad 112 and a source pad 114. The gate pad 112 and the source pad 114 are electrode pads electrically connected to a gate electrode 44 and a source electrode 54, respectively, which will be described later.

  The edge termination region 130 surrounds the periphery of the active region 110 in a plan view from the Z-axis direction. The edge termination region 130 may have at least one of a guard ring structure, a field plate structure, and a JTE (Junction Termination Extension) structure. The edge termination region 130 may have a function of preventing a concentration of an electric field in the active region 110 by expanding a depletion layer generated in the active region 110 to the edge termination region 130.

(Configuration example of vertical MOSFET)
FIG. 2 is a cross-sectional view illustrating a configuration example of the vertical MOSFET according to the embodiment of the present invention. FIG. 2 is a cross-sectional view of the active region 110 shown in FIG. 1 taken along the line II-II ′, and shows a repeated unit structure of the vertical MOSFET 1. The GaN semiconductor device 100 includes a plurality of vertical MOSFETs (Metal Oxide Semiconductor Field Effect Transistors) 1 shown in FIG. In the GaN semiconductor device 100, the vertical MOSFET 1 is provided repeatedly in the Y-axis direction. In FIG. 2, a virtual line CL is illustrated for convenience of describing the structure of the vertical MOSFET 1. The virtual line CL is a straight line parallel to the Z-axis direction. The virtual line CL passes through the center of the unit structure shown in FIG. 2 in the Y-axis direction.

  As shown in FIG. 2, the vertical MOSFET 1 has a gallium nitride substrate (hereinafter, GaN substrate) 10, a GaN layer 16, a gate insulating film 42, a gate electrode 44, a source electrode 54, and a drain electrode 56.

The GaN substrate 10 is a GaN single crystal substrate. The GaN substrate 10 is a substrate of the first conductivity type (N type), for example, an N ⁺ type substrate. The GaN substrate 10 has a first main surface 10a and a second main surface 10b located on the opposite side of the first main surface 10a. For example, the GaN substrate 10 is a low-dislocation self-standing substrate having a dislocation density of less than 1 × 10 ⁷ cm ⁻² . Since the GaN substrate 10 is a low-dislocation self-supporting substrate, the dislocation density of the GaN layer 16 formed on the GaN substrate 10 also decreases.

  Further, by using a low dislocation substrate for the GaN substrate 10, even when a large-area power device is formed on the GaN substrate 10, the leakage current in the power device can be reduced. Thus, the manufacturing apparatus can manufacture the power device at a high yield rate. Further, in the heat treatment, it is possible to prevent the ion-implanted impurity from deeply diffusing along the dislocation.

The GaN layer 16 is provided on the first main surface 10a of the GaN substrate 10. The GaN layer 16 is formed epitaxially on the GaN substrate 10. The GaN layer 16 is an N-type layer, for example, an N ^- type layer. The N-type impurities contained in the GaN layer 16 may be one or more elements of Si (silicon), Ge (germanium), and O (oxygen). In the embodiment of the present invention, Si is used as an example of an N-type impurity. The second conductivity type (P-type) impurity for the GaN layer 16 may be one or more elements of Mg (magnesium), Ca (calcium), Be (beryllium), and Zn (zinc). In the embodiment of the present invention, Mg is used as an example of a P-type impurity.

  In the vertical MOSFET 1, the semiconductor material is GaN, but the semiconductor material may include one or more elements of aluminum (Al) and indium (In). The semiconductor material may be a mixed crystal semiconductor containing trace amounts of Al and In, that is, AlxInyGa1-xyN (0 ≦ x <1, 0 ≦ y <1). GaN is the case where x = y = 0 in AlxInyGa1-x-yN.

  The GaN layer 16 has a drift region 22, a base region 23, a contact region 25, a source region 26, and a buried region 28. The base region 23, the contact region 25, the source region 26, and the buried region 28 are regions formed by implanting impurities to a predetermined depth from the surface 16a of the GaN layer 16 and performing a heat treatment.

The base region 23, the contact region 25, and the buried region 28 are P-type regions. The base region 23, the contact region 25, and the buried region 28 include, for example, Mg as a P-type impurity. The base region 23, the contact region 25, and the buried region 28 are formed by implanting Mg into the GaN layer 16 and performing a heat treatment for activating Mg. The base region 23 is P type or P ⁻ type, and the contact region 25 and the buried region 28 are P ⁺ type. The contact region 25 and the buried region 28 have a higher P-type impurity concentration than the base region 23.

  The base region 23 and the buried region 28 constitute a P-type impurity region 2. In the P-type impurity region 2, the side closer to the surface 16a of the GaN layer 16 is the base region 23, and the side farther from the surface 16a of the GaN layer 16 is the buried region 28. Between the base region 23 and the buried region 28, the P-type impurity concentration changes continuously.

The drift region 22 and the source region 26 are N-type regions. The drift region 22 and the source region 26 include, for example, Si as an N-type impurity. The source region 26 is formed by implanting Si into the GaN layer 16 and performing heat treatment. Source region 26 is of the N ⁺ type. The drift region 22 is an N-type or N ^- type region. The drift region 22 has a lower N-type impurity concentration than the source region 26. For example, in the manufacturing process of the vertical MOSFET 1, N-type impurities are not ion-implanted into the drift region 22. The N-type impurity concentration of drift region 22 is the same as the N-type impurity concentration of GaN layer 16.

  As shown in FIG. 2, the upper portion of the source region 26 is exposed on the surface 16a of the GaN layer 16. The source region 26 has a bottom portion and an inner side portion in contact with the base region 23, and an outer side portion in contact with the contact region 25. The inner side of the source region 26 is a side closer to the virtual line CL. The outer side of the source region 26 is a side farther from the virtual line CL. In the unit structure shown in FIG. 2, the source region 26 has a first source region 26-1 and a second source region 26-2. The first source region 26-1 and the second source region 26-2 are arranged symmetrically about the virtual line CL.

  The buried region 28 is located below the bottom of the source region 26 (that is, on the GaN substrate 10 side). Base region 23 is located between the bottom of source region 26 and the top of buried region 28. Further, an inner side portion of the buried region 28 is in contact with the drift region 22. The inner side portion of the embedded region 28 is a side portion closer to the virtual line CL. In the unit structure shown in FIG. 2, the embedded region 28 has a first embedded region 28-1 and a second embedded region 28-2. The first embedding region 28-1 and the second embedding region 28-2 are arranged symmetrically about the virtual line CL.

  The base region 23 is provided on the buried region 28. The upper part of the base region 23 is exposed on the surface 16 a of the GaN layer 16. The upper part of the base region 23 is a channel region 231 of the vertical MOSFET 1. Channel region 231 is in contact with gate insulating film 42 on surface 16a. The lower part of the base region 23 is in contact with the buried region 28. Further, an inner side portion of the base region 23 is in contact with the drift region 22. The inner side of the base region 23 is a side closer to the virtual line CL. In the unit structure shown in FIG. 2, the base region 23 has a first base region 23-1 and a second base region 23-2. The first base region 23-1 and the second base region 23-2 are arranged symmetrically about the virtual line CL.

Contact region 25 is provided on buried region 28. The upper part of the contact region 25 is exposed on the surface 16a of the GaN layer 16. The contact region 25 has an inner side portion in contact with the source region 26 and the base region 23 and a bottom portion in contact with the buried region 28. The inner side of the contact region 25 is a side closer to the virtual line CL. In the unit structure shown in FIG. 2, the contact region 25 has a first contact region 25-1 and a second contact region 25-2. The first contact region 25-1 and the second contact region 25-2 are arranged symmetrically with respect to the virtual line CL.
The base region 23, the contact region 25, the source region 26, and the buried region 28 have a stripe shape extending in the X-axis direction.

  An upper portion (hereinafter, upper region) 221 of drift region 22 is exposed on surface 16 a of GaN layer 16. Upper region 221 is in contact with gate insulating film 42 on surface 16a. Further, a lower part (hereinafter, lower part) 222 of drift region 22 is in contact with first main surface 10 a of GaN substrate 10. The upper region 221 is located between the first base region 23-1 and the second base region 23-2 and between the first buried region 28-1 and the second buried region 28-2, respectively.

  The lower region 222 is located between the upper region 221 and the GaN substrate 10, between the first buried region 28-1 and the GaN substrate 10, and between the second buried region 28-2 and the GaN substrate 10, respectively. I do. The lower region 222 may be provided continuously in the Y-axis direction between a plurality of vertical MOSFETs 1 (that is, a plurality of unit structures) repeated in the Y-axis direction.

  Drift region 22 functions as a current path between channel region 231 and GaN substrate 10. The contact region 25 has a function of reducing contact resistance with the source electrode 54. The contact region 25 also functions as a hole extraction path when the gate is off.

  The buried region 28 functions as a breakdown voltage structure. For example, when the buried region 28 is not provided in the GaN layer 16, the depletion layer formed by the PN junction between the base region 23 and the drift region 22 reaches the upper end of the base region 23, so that the withstand voltage at the time of gate-off is reduced. May decrease. In contrast, the vertical MOSFET 1 according to the embodiment of the present invention can prevent the depletion layer from reaching the upper end of the base region 23 by having the buried region 28 having a high P-type impurity concentration. Further, since the vertical MOSFET 1 has the buried region 28 having a high P-type impurity concentration, the depletion layer formed by the PN junction between the buried region 28 and the drift region 22 can be expanded toward the lower region 222. . Thus, the vertical MOSFET 1 can improve the breakdown voltage at the time of gate-off as compared with the case where the buried region 28 is not provided.

The gate insulating film 42 is, for example, a silicon oxide film (SiO ₂ film). Gate insulating film 42 is provided on flat surface 16a. In the embodiment of the present invention, the flat surface means a surface on which intentional unevenness is not provided by etching for providing a gate trench portion or a mesa structure. However, the flat surface is not limited to a completely flat surface, and may be a substantially flat surface. In the embodiment of the present invention, the flat surface may have, for example, irregularities of about 10 nm. The unevenness may be evaluated by, for example, the maximum height roughness Rz. The maximum height roughness Rz is defined as a graph obtained by extracting a contour curve by the reference length L in the direction of the average line of the contour curve indicating the unevenness, from the height Rp from the average line to the highest peak to the lowest valley. Means the difference from the depth Rv.

  In active region 110, surface 16 a of GaN layer 16 includes the surface of contact region 25, the surface of source region 26, the surface of channel region 231, and the surface of upper region 221. The surface of the contact region 25, the surface of the source region 26, the surface of the channel region 231, and the surface of the upper region 221 form one plane parallel or substantially parallel to the first main surface 10a of the GaN substrate 10. In the active region 110, the surface 16a of the GaN layer 16 has no steps such as a gate trench and a mesa. Therefore, in the active region 110, the electric field does not concentrate on the corner at the bottom of the step. Thereby, the GaN semiconductor device 100 can reduce the possibility that the withstand voltage is reduced due to the electric field concentration on the corners.

  The gate electrode 44 is provided above the channel region 231 via the gate insulating film 42. For example, the gate electrode 44 is provided continuously from above the channel region 231 to above the source region 26 via the gate insulating film 42. The gate electrode 44 is of a planar type provided on a flat gate insulating film 42. By forming the gate electrode 44 on the flat gate insulating film 42, the gate electrode 44 is also formed flat. Gate electrode 44 is formed of a material different from that of gate pad 112. The gate electrode 44 is formed of polysilicon doped with impurities, and the gate pad 112 is formed of Al or an Al-Si alloy.

  Source electrode 54 is provided on surface 16 a of GaN layer 16. Source electrode 54 is in contact with a part of source region 26 and contact region 25. The source electrode 54 may be provided on the gate electrode 44 via an interlayer insulating film (not shown). The interlayer insulating film may cover the upper and side portions of the gate electrode 44 so that the gate electrode 44 and the source electrode 54 are not electrically connected.

  Source electrode 54 is formed of the same material as source pad 114. For example, the source electrode 54 made of an alloy of Al or Al—Si also serves as the source pad 114. The source electrode 54 may have a barrier metal layer between the surface 16a of the GaN layer 16 and the Al layer (or Al-Si layer). Titanium (Ti) may be used as a material for the barrier metal layer. That is, the source electrode 54 may be a stacked layer of a Ti layer and an Al layer, or a stacked layer of a Ti layer and an Al-Si alloy layer. The drain electrode 56 is provided on the second main surface 10b side of the GaN substrate 10, and is in contact with the second main surface 10b. The drain electrode 56 is also made of the same material as the source electrode 54.

  In FIG. 2, a gate terminal, a source terminal, and a drain terminal are denoted by G, D, and S, respectively. For example, when a potential higher than the threshold voltage is applied to the gate electrode 44 through the gate terminal G, an inversion layer is formed in the channel region 231. When a predetermined high potential is applied to the drain electrode 56 and a low potential (for example, ground potential) is applied to the source electrode 54 in a state where the inversion layer is formed in the channel region 231, the source from the drain terminal D A current flows to the terminal S. When a potential lower than the threshold voltage is applied to the gate electrode 44, no inversion layer is formed in the channel region 231 and the current is shut off. Thereby, the vertical MOSFET 1 can switch the current between the source terminal S and the drain terminal D.

Incidentally, in the Z-axis direction, the impurity region 2 has an Mg peak position 28P where the concentration of the P-type impurity (eg, Mg) is the highest. In the impurity region 2, the Mg peak position 28P exists in the buried region 28. The depth (hereinafter, Mg peak depth) D1 from the surface 16a of the GaN layer 16 to the Mg peak position 28P is 200 nm or more and 1500 nm or less, more preferably 300 nm or more and 1000 nm or less, and still more preferably 400 nm or more. It is 800 nm or less. Further, the Mg concentration at the Mg peak position 28P (hereinafter, Mg peak concentration) is 1 × 10 ¹⁷ cm ⁻³ or more and 1 × 10 ¹⁹ cm ⁻³ or less, more preferably 1 × 10 ¹⁸ cm ⁻³ or more. It is 1 × 10 ¹⁹ cm ⁻³ or less. Thereby, the vertical MOSFET 1 can improve the withstand voltage at the time of gate off.

The concentration of Mg on the surface of the base region 23 (hereinafter, surface Mg concentration) is 1 × 10 ¹⁶ cm ⁻³ or more and 3 × 10 ¹⁸ cm ⁻³ or less, and more preferably 1 × 10 ¹⁷ cm ^−3. It is at least 1 × 10 ¹⁸ cm ⁻³ . Thereby, the vertical MOSFET 1 can have a threshold and mobility within an appropriate range while suppressing a decrease in withstand voltage at the time of gate-off, and can improve characteristics thereof. In the embodiment of the present invention, the surface Mg concentration means, for example, the Mg concentration in a range from the outermost surface of the base region 23 to a depth of 100 nm.

(Configuration example of edge termination area)
3A and 3B are cross-sectional views illustrating a configuration example of the edge termination region of the GaN semiconductor device according to the embodiment of the present invention. FIGS. 3A and 3B show two examples of a cross section of FIG. 1 taken along the line III-III ′. Specifically, FIG. 3A shows a case where the edge termination region 130 has the guard ring structure 74. FIG. 3B shows a case where the edge termination region 130 has a JTE (Junction Termination Extension) structure 78.
As shown in FIGS. 3A and 3B, in the active region 110 and the edge termination region 130, the GaN substrate 10, the GaN layer 16, and the drain electrode 56 are provided in common. However, as shown in FIGS. 3A and 3B, the structure inside the GaN layer 16 in the edge termination region 130 is different from the structure inside the GaN layer 16 in the active region 110. Further, the edge termination region 130 includes the electrode 58 provided on the GaN layer 16 and the protective film 70 provided on the GaN layer 16.

The GaN layer 16 in the edge termination region 130 has a drift region 22, a base region 23, a first doped region 35, a second doped region 36, and a buried region 28. The base region 23, the first doped region 35, the second doped region 36, and the buried region 28 are P-type regions. The base region 23, the first doped region 35, the second doped region 36, and the buried region 28 contain Mg as a P-type impurity. The base region 23, the first doped region 35, the second doped region 36, and the buried region 28 are formed by ion-implanting Mg into the GaN layer 16 and performing a heat treatment. The buried region 28 is of a P ⁺ type. The base region 23, the first doped region 35, and the second doped region 36 are P-type or P ^- type.

  The base region 23 is provided on the buried region 28. In the XY plane, the first doped region 35 is located between the second doped region 36 and the base region 23. The base region 23 is located closer to the active region 110, and the second doped region 36 is located farther from the active region 110.

  As shown in FIG. 3A, the edge termination region 130 has, for example, a plurality of guard ring structures 74 separated from each other. The guard ring structure 74 is a structure surrounding the active region in a ring shape with a plurality of thin p-type layers. Alternatively, the edge termination region 130 may have one guard ring structure 74 instead of a plurality. The guard ring structure 74 may be composed of the base region 23 or the buried region 28, and is not limited to this, and may have another configuration. For example, the guard ring structure 74 may be formed of an impurity region having a different concentration or implantation peak depth from the base region 23 and the buried region 28.

  Since the GaN semiconductor device 100 has the guard ring structure 74, the depletion layer in the gate-off state can easily spread to the outer edge of the GaN layer 16. Thereby, the GaN semiconductor device 100 can improve the breakdown voltage of the vertical MOSFET 1 as compared with the case where the guard ring structure 74 is not provided.

As shown in FIG. 3B, the edge termination region 130 may have the JTE structure 78. JTE structure 78 may be composed of one impurity region, or may be composed of two or more impurity regions having different concentrations. In any case, an appropriate configuration may be selected.
For example, the JTE structure 78 includes a first doped region 35 and a second doped region 36. The P-type impurity concentration in the second doped region 36 is lower than the P-type impurity concentration in the first doped region 35. By making the P-type impurity concentration of the second doped region 36 relatively lower than that of the first doped region 35, the depletion layer in the gate-off state can easily spread to the outer peripheral end of the GaN layer 16. Thereby, the GaN semiconductor device 100 can improve the breakdown voltage of the vertical MOSFET 1 as compared with the case where the JTE structure 78 is not provided.
Further, the edge termination region 130 may have both the guard ring structure 74 and the JTE structure 78. Even when both the guard ring structure 74 and the JTE structure 78 are combined, the GaN semiconductor device 100 can improve the breakdown voltage of the vertical MOSFET 1.

  In the edge termination region 130, the surface 16a of the GaN layer 16 includes the surface of the base region 23, the surface of the first doped region 35, and the surface of the second doped region 36. In the embodiment of the present invention, the surface of the base region 23, the surface of the first doped region 35, and the surface of the second doped region 36 are one plane parallel or almost parallel to the first main surface 10a of the GaN substrate 10. Is configured. The GaN layer 16 in the edge termination region 130 has no steps such as a gate trench or a mesa. In the active region 110 and the edge termination region 130, the thickness of the GaN layer 16 is the same. Even at the boundary between the active region 110 and the edge termination region 130, the GaN layer 16 has no steps such as a gate trench or a mesa. For this reason, the electric field does not concentrate on the edge of the edge termination region 130 or the corner between the active region 110 and the edge termination region 130 at the bottom of the step. The GaN semiconductor device 100 can reduce the possibility that the withstand voltage is reduced due to the electric field concentration on the corners.

The protection film 70 is a passivation film, for example, a SiO ₂ film. The protective film 70 covers the surface 16a of the GaN layer 16 in the edge termination region 130. This can prevent impurities from entering the inside from the surface 16a of the GaN layer 16.

(Method of manufacturing vertical MOSFET)
Next, a method for manufacturing the vertical MOSFET 1 according to the embodiment of the present invention will be described. 4 to 9 are cross-sectional views illustrating a method of manufacturing the vertical MOSFET according to the embodiment of the present invention in the order of steps. The vertical MOSFET 1 is manufactured by various manufacturing apparatuses such as a film forming apparatus, an exposure apparatus, and an etching apparatus.

As shown in FIG. 4, the manufacturing apparatus forms the GaN layer 16 on the GaN substrate 10. For example, the manufacturing apparatus epitaxially forms the N-type GaN layer 16 on the N ⁺ -type GaN substrate 10 by metal organic chemical vapor deposition (MOCVD) or halide vapor phase epitaxy (HVPE). The epitaxially formed GaN layer 16 may have Si as an N-type impurity. The concentration of Si in the GaN layer 16 is, for example, not less than 1 × 10 ¹⁵ cm ^{−3 and not} more than 5 × 10 ¹⁶ cm ⁻³ . The thickness of the GaN layer 16 (that is, the distance from the first main surface 10a of the GaN substrate 10 to the surface 16a of the GaN layer 16) may be changed according to a desired breakdown voltage. is there.

Next, in the manufacturing apparatus, the GaN layer 16 includes a region (hereinafter, base forming region) 23 ′ where the base region 23 (see FIG. 2) is formed, and a region (hereinafter, referred to as the buried region 28 (see FIG. 2)). Hereinafter, Mg is ion-implanted into the buried formation region ′ ′ as an N-type impurity. For example, the manufacturing apparatus forms the mask M1 on the GaN layer 16. The mask M1 is a SiO ₂ film or a photoresist that can be selectively removed from the GaN layer 16. In the active region 110 (see FIG. 1), the mask M1 has a shape that opens above the base formation region 23 ′ and above the buried formation region 28 ′ and covers above other regions. The manufacturing apparatus ion-implants Mg into the GaN layer 16 on which the mask M1 is formed.

In the step of ion-implanting Mg into the base formation region 23 'and the buried formation region 28' (hereinafter, Mg injection step), the depth from the surface 16a of the GaN layer 16 to the implantation peak position 28P '(hereinafter, implantation peak depth). (3) The implantation energy (acceleration voltage) is set so that D1 ′ is 200 nm or more and 1500 nm or less, more preferably 300 nm or more and 1000 nm or less, and still more preferably 400 nm or more and 800 nm or less.
In the Mg implantation step, the concentration of Mg at the implantation peak position 28P '(hereinafter, implantation peak concentration) is 1 × 10 ¹⁷ or more and 1 × 10 ¹⁹ cm ⁻³ or less, more preferably 1 × 10 ¹⁸ cm ^−. The dose of Mg is set so as to be ³ or more and 1 × 10 ¹⁹ cm ⁻³ or less.

In the Mg implantation step, in order to realize the above-described implantation peak depth D1 ′ and implantation peak concentration, the manufacturing apparatus uses, for example, a single-stage implantation of an acceleration voltage of 700 KeV and a dose of 4.2 × 10 ¹⁴ cm ^−2. Is ion-implanted into the GaN layer 16. After the ion implantation, the manufacturing apparatus removes the mask M1 from the GaN layer 16. It should be noted that one-stage injection means that the acceleration voltage is one condition.

Next, as shown in FIG. 5, the manufacturing apparatus forms an insulating film 31 on the GaN layer 16. For example, the insulating film 31 is a SiO ₂ film. The manufacturing apparatus forms the insulating film 31 by chemical vapor deposition (CVD). Next, the manufacturing apparatus ion-implants Si as an N-type impurity into a region (hereinafter, a source forming region) 26 'in the GaN layer 16 where a source region is formed. For example, the manufacturing apparatus forms the mask M2 on the GaN layer 16. The mask M2 is a SiO ₂ film or a photoresist. In the active region 110, the mask M2 has a shape that opens above the source forming region 26 'and covers above other regions. The manufacturing apparatus ion-implants Si into the GaN layer 16 on which the mask M2 is formed. After the ion implantation, the manufacturing apparatus removes the mask M2 from above the GaN layer 16.

Next, as shown in FIG. 6, the manufacturing apparatus ion-implants Mg as a P-type impurity into a region (hereinafter, a contact formation region) 25 'in the GaN layer 16 where a contact region is formed. For example, the manufacturing apparatus forms the mask M3 on the GaN layer 16. The mask M3 is a SiO ₂ film or a photoresist. In the active region 110, the mask M3 has a shape that opens above the contact formation region 25 ′ and covers above other regions. The manufacturing apparatus ion-implants Mg into the GaN layer 16 on which the mask M3 is formed. After the ion implantation, the manufacturing apparatus removes the mask M3 from above the GaN layer 16.

  Next, as shown in FIG. 7, the manufacturing apparatus forms a protective film 33 on the insulating film 31. The protective film 33 has a function of preventing nitrogen atoms from being released from the GaN layer 16 during the heat treatment. Nitrogen vacancies are formed at positions where nitrogen atoms are released from the GaN layer 16. Nitrogen vacancies can function as donor-type defects, which can inhibit the development of P-type properties. In order to prevent this, the manufacturing apparatus provides a protective film 33 on the GaN layer 16 with an insulating film 31 interposed therebetween.

The protective film 33 has high heat resistance, has good adhesion to the insulating film 31, does not diffuse impurities from the protective film 33 to the GaN layer 16 side, and can be selectively removed from the GaN layer 16. It is preferred that High heat resistance means that the protective film 33 is not substantially decomposed to such an extent that no pits (through openings) are formed in the protective film 33 even when heat treatment is performed at a temperature of 800 ° C. or more and 2000 ° C. or less. means.
The protection film 33 is an aluminum nitride (AlN) film, a SiO ₂ film, or a silicon nitride (SiN) film. Note that the protective film 33 may be a laminated film in which another film is laminated on the AlN film. As another film, one or more of a SiO ₂ film, a SiN film, and a GaN film are exemplified.

Next, the manufacturing apparatus performs a heat treatment at a maximum temperature of 800 ° C. or more and 2000 ° C. or less on the stacked body including the GaN substrate 10, the GaN layer 16, the insulating film 31, and the protective film 33. This heat treatment is, for example, a rapid heating process. By this heat treatment, Mg and Si introduced into the GaN layer 16 are activated. Thus, a P-type or P ⁻ -type base region 23, a P ⁺ -type contact region 25, an N ⁺ -type source region 26, and a P ⁺ -type buried region 28 are formed in the GaN layer 16. At the same time, the drift region 22 is defined. Further, by this heat treatment, defects caused by ion implantation in the GaN layer 16 can be recovered to some extent. After the heat treatment, the manufacturing apparatus removes the protective film 33 and the insulating film 31 from the GaN layer 16.

Next, as shown in FIG. 8, the manufacturing apparatus forms a gate insulating film 42 on the GaN layer 16. For example, the manufacturing apparatus forms an insulating film by a CVD method, and then shapes the insulating film into a predetermined shape by using photolithography and an etching technique. Thereby, the manufacturing apparatus forms the gate insulating film 42. The gate insulating film 42 is a SiO ₂ film, and its thickness is 100 nm.
Next, as shown in FIG. 9, the manufacturing apparatus forms the gate electrode 44, the source electrode 54, and the drain electrode 56. Next, the manufacturing apparatus forms an interlayer insulating film (see FIG. 1) on the gate electrode 44. The interlayer insulating film is, for example, a SiO ₂ film. Next, the manufacturing apparatus forms a gate pad 112 electrically connected to the gate electrode 44 and a source pad 114 electrically connected to the source electrode 54. Thus, the vertical MOSFET 1 is completed.

(Experimental result)
Experimental results are shown for the distribution of Mg concentration in the depth direction of the GaN layer. FIG. 10 is a graph showing the distribution of Mg concentration in the depth direction of the GaN layer (before heat treatment). FIG. 11 is a graph showing the distribution of Mg concentration in the depth direction of the GaN layer (after heat treatment). The horizontal axis in FIGS. 10 and 11 indicates the depth [nm] from the surface of the GaN layer. The vertical axis in FIGS. 10 and 11 indicates the Mg concentration [cm ⁻³ ] in the GaN layer.

As shown in FIG. 10, the present inventor performed the Mg implantation step under three different conditions (A), (B), and (C), respectively, and adjusted the Mg concentration in the depth direction of the GaN layer by SIMS (Secondary Ion Mass). (Spectrometry; secondary ion mass spectrometry). Condition (A) is such that the acceleration voltage is 700 keV (single-stage implantation) and the dose of Mg is 4.2 × 10 ¹⁴ cm ⁻² .
In the GaN layer under the condition (A), the Mg implantation peak depth was 650 nm, and the Mg implantation peak concentration was 1 × 10 ¹⁹ cm ⁻³ .
Condition (B) is such that the acceleration voltage is 700 keV (single-stage implantation) and the dose of Mg is 1.3 × 10 ¹⁴ cm ⁻² . In the GaN layer under the condition (B), the Mg implantation peak depth was 600 nm, and the Mg implantation peak concentration was 3 × 10 ¹⁸ cm ⁻³ .
The condition (C) is such that the acceleration voltage is 700 keV (single-step implantation) and the dose of Mg is (4.2 × 10 ¹³ ) cm ⁻² . In the GaN layer under the condition (C), the Mg implantation peak depth was 600 nm, and the Mg implantation peak concentration was 1 × 10 ¹⁸ cm ⁻³ .

Next, the present inventors performed a heat treatment for activating Mg on each of the GaN layers into which Mg was implanted under the conditions (A), (B), and (C). The condition of the heat treatment is 1300 ° C. for 5 minutes. Then, as shown in FIG. 11, the present inventors measured the Mg concentration in the depth direction of the GaN layer after the heat treatment by SIMS.
In the GaN layer under the condition (A), the Mg peak depth after the heat treatment was 700 nm, the Mg peak concentration was 7.5 × 10 ¹⁸ cm ⁻³ , and the surface Mg concentration was 3 × 10 ¹⁸ cm ⁻³ .
In the GaN layer under the condition (B), the Mg peak depth after the heat treatment was 450 nm, the Mg peak concentration was 3 × 10 ¹⁸ cm ⁻³ , and the surface Mg concentration was 8 × 10 ¹⁶ cm ⁻³ .
In the GaN layer under the condition (C), the Mg peak depth after the heat treatment was 600 nm, the Mg peak concentration was 1 × 10 ¹⁸ cm ⁻³ , and the surface Mg concentration was 3 × 10 ¹⁶ cm ⁻³ .

As can be seen from a comparison between FIG. 10 and FIG. 11, it was found that in the GaN layer under the condition (A), Mg tends to diffuse to the surface side of the GaN layer by the above heat treatment. That is, it was found that when the injection peak concentration approaches 1 × 10 ¹⁹ cm ⁻³ in the Mg injection step, Mg diffuses to the surface side of the GaN layer due to the heat treatment, and the surface Mg concentration tends to increase. Further, in each of the GaN layers under the conditions (B) and (C), even if the above heat treatment is performed, diffusion of Mg to the surface side of the GaN layer is hardly observed, and the surface Mg concentration hardly changes. Do you get it. From this result, when the implantation peak depth is around 500 nm in the Mg implantation step and the implantation peak concentration exceeds 1 × 10 ¹⁹ cm ⁻³ , the diffusion of Mg to the surface side of the GaN layer is remarkable during the above heat treatment. It is considered that the increase in the surface Mg concentration becomes remarkable.

  Here, the higher the surface Mg concentration, the higher the threshold value of the vertical MOSFET. In order to operate the vertical MOSFET in a normally-off state, a threshold value of, for example, 3 V or more is required. However, as the threshold value increases, the mobility decreases. The threshold and the mobility are in a trade-off relationship. The decrease in mobility is not preferable in terms of the characteristics of the vertical MOSFET.

FIG. 12 is a graph showing the relationship between the surface Mg concentration of the GaN layer and the threshold. FIG. 12 shows the results of an experiment performed by the present inventors. The horizontal axis in FIG. 12 indicates the surface Mg concentration [cm ⁻³ ]. The vertical axis in FIG. 12 indicates the threshold value Vth [V] of the vertical MOSFET. As shown in FIG. 12, the higher the surface Mg concentration, the higher the threshold value Vth. Therefore, in order to set the threshold value Vth to a desired value, it is necessary to control the surface Mg concentration. For example, it is desirable that Vth of the vertical MOSFET be 3 V or more and 10 V or less in relation to mobility. In order to realize this, it turned out that the surface Mg concentration needs to be 1 × 10 ¹⁶ cm ⁻³ or more and 3 × 10 ¹⁸ cm ⁻³ or less. In addition, it was found that the more preferable range P1 for the surface Mg concentration was 1 × 10 ¹⁷ cm ⁻³ or more and 1 × 10 ¹⁸ cm ⁻³ or less.

  As described above, the GaN semiconductor device 100 according to the embodiment of the present invention includes the GaN layer 16, the N-type source region 26 provided in the GaN layer 16, and the surface of the GaN layer 16 provided in the GaN layer 16. A P-type impurity region 2 adjacent to the source region 26 in a first direction (X-axis direction and Y-axis direction) parallel to the surface 16a and in a second direction (Z-axis direction) crossing the surface 16a. In the second direction, the impurity region 2 has a Mg peak position 28P where the concentration of the P-type impurity (eg, Mg) is the highest.

  For example, the impurity region 2 has a base region 23 adjacent to the source region 26 in the first direction and the second direction, and a buried region 28 located farther from the surface 16a of the GaN layer 16 than the base region 23. . The buried region 28 has a higher Mg concentration than the base region 23. The Mg peak position 28P exists in the buried region 28.

The depth (Mg peak depth) D1 from the surface 16a of the GaN layer 16 to the Mg peak position 28P is 200 nm or more and 1500 nm or less, more preferably 300 nm or more and 1000 nm or less, and still more preferably 400 nm or more and 800 nm or less. It is. The Mg concentration (Mg peak concentration) at the Mg peak position 28P is 1 × 10 ¹⁷ cm ⁻³ or more and 1 × 10 ¹⁹ cm ⁻³ or less, more preferably 1 × 10 ¹⁸ cm ⁻³ or more and 1 × 10 ^19. cm ⁻³ or less. The concentration of Mg (surface Mg concentration) on the surface 16a of the impurity region 2 is 1 × 10 ¹⁶ cm ⁻³ or more and 3 × 10 ¹⁸ cm ⁻³ or less.

  With such a configuration, the GaN semiconductor device 100 can set the threshold value of the vertical MOSFET 1 to a value suitable for the normally-off operation without excessively lowering the mobility. Thereby, the GaN semiconductor device 100 can improve the characteristics of the vertical MOSFET. Further, an Mg peak position 28P is located in the buried region 28 existing at a deep position when viewed from the surface 16a of the GaN layer 16. As a result, a depletion layer formed between the P-type buried region 28 and the N-type GaN layer 16 (for example, the drift region 22) spreads closer to the GaN substrate 10. Thereby, the GaN semiconductor device 100 can improve the withstand voltage when the gate of the vertical MOSFET 1 is turned off.

Further, in the method for manufacturing the GaN semiconductor device 100 according to the embodiment of the present invention, the step of ion-implanting Mg into the GaN layer 16 (Mg implantation step) and the step of performing a heat treatment on the GaN layer 16 into which Mg has been implanted, Forming the region 2. In the Mg injection step, the injection peak position of Mg is 200 nm or more and 1500 nm or less, more preferably 300 nm or more and 1000 nm or less, more preferably 400 nm or more and 800 nm or less in depth from the surface 16a of the GaN layer 16, The concentration of Mg at the injection peak position (injection peak concentration) is 1 × 10 ¹⁷ cm ⁻³ or more and 1 × 10 ¹⁹ cm ⁻³ or less, more preferably 1 × 10 ¹⁸ cm ⁻³ or more and 1 × 10 ¹⁹ cm ^{−. The} ion implantation conditions are set so as to be ³ or less.

According to this, in the heat treatment for activating Mg, diffusion of Mg to the surface 16a side of GaN layer 16 is suppressed. Therefore, the Mg peak depth D1 is 200 nm or more and 1500 nm or less, more preferably 300 nm or more and 1000 nm or less, even more preferably 400 nm or more and 800 nm or less, and the Mg peak concentration is 1 × 10 ¹⁷ cm ⁻³ or more and 1 or more. × 10 ¹⁹ cm ⁻³ or less, more preferably 1 × 10 ¹⁸ cm ⁻³ or more and 1 × 10 ¹⁹ cm ⁻³ or less, and a surface Mg concentration of 1 × 10 ¹⁶ cm ⁻³ or more and 3 × 10 ¹⁸ cm ⁻³ or less, the vertical MOSFET 1 can be manufactured.

(Modification 1)
In the embodiment of the present invention, the drift region 22 may be doped to increase the N-type impurity concentration.

FIG. 13 is a cross-sectional view illustrating a configuration of a vertical MOSFET according to a modification of the embodiment of the present invention. As shown in FIG. 13, the vertical MOSFET 1A according to the modification of the embodiment includes an N-type doped region cd provided in the N ⁻ -type drift region 22. The doped region cd is a region doped with an N-type impurity (for example, Si). In the drift region 22, a region other than the doped region cd is an undoped region ucd. The doped region cd has a higher N-type impurity (eg, Si) concentration than the undoped region ucd.

  The doped region cd is located closer to the surface 16a of the GaN layer 16 than the undoped region ucd. For example, the doped region cd is provided continuously over the entire upper region 221 and the end of the lower region 222 that is in contact with the upper region 221. According to this, in the drift region 22, the N-type impurity concentration in a region adjacent to the channel region 231 can be increased. This makes it possible to reduce the on-resistance of the vertical MOSFET 1 while suppressing a decrease in breakdown voltage.

FIG. 14 is a cross-sectional view illustrating a method for manufacturing a vertical MOSFET according to a modification of the embodiment of the present invention. FIG. 14 shows a step for forming a doped region cd. As shown in FIG. 14, the manufacturing apparatus ion-implants an N-type impurity into a region (hereinafter referred to as a doped region) cd ′ in the GaN layer 16 where the doped region cd is formed. For example, the manufacturing apparatus forms the mask M4 on the GaN layer 16. The mask M4 is a SiO ₂ film or a photoresist. In the active region 110 (see FIG. 1), the mask M4 has a shape that opens above the doped region cd ′ and covers above other regions. The manufacturing apparatus ion-implants Si into the GaN layer 16 on which the mask M4 is formed. After the ion implantation, the manufacturing apparatus removes the mask M4 from above the GaN layer 16.

  Next, the manufacturing apparatus performs a heat treatment on the GaN layer 16. Thereby, the Si ion-implanted into the doped region cd 'is activated, and an N-type doped region cd is formed in the GaN layer 16. This heat treatment is performed in combination with the above-described heat treatment for forming the base region 23, the contact region 25, the source region 26, and the buried region 28 (for activating Mg).

(Modification 2)
In the above embodiment, it has been described that the Mg implantation process is a single-stage implantation. However, embodiments of the present invention are not limited to this. The Mg injection step may be a multi-step injection in which the acceleration voltage is switched midway. In the multi-stage implantation, Mg is implanted into the GaN layer at different depths by dividing the acceleration voltage into several stages. Even in such a method, the Mg peak depth D1 after the heat treatment (for example, see FIG. 2) is 200 nm or more and 1500 nm or less, more preferably 300 nm or more and 1000 nm or less, and still more preferably 400 nm or more and 800 nm or less. It can be: Further, the Mg concentration (Mg peak concentration) at the Mg peak position 28P (for example, see FIG. 2) after the heat treatment is set to 1 × 10 ¹⁷ cm ⁻³ or more and 1 × 10 ¹⁹ cm ⁻³ or less, more preferably 1 × 10 ¹⁹ cm ^−3. It can be set to 10 ¹⁸ cm ⁻³ or more and 1 × 10 ¹⁹ cm ⁻³ or less. Furthermore, the surface Mg concentration after the heat treatment is set to 1 × 10 ¹⁶ cm ⁻³ or more and 3 × 10 ¹⁸ cm ⁻³ or less, more preferably 1 × 10 ¹⁷ cm ⁻³ or more and 1 × 10 ¹⁸ cm ⁻³ or less. be able to.

FIG. 15 is a graph schematically showing the distribution of Mg concentration (before and after heat treatment) in the depth direction of the GaN layer into which Mg has been injected in multiple stages. The horizontal axis in FIG. 15 indicates the depth [nm] from the surface of the GaN layer. The vertical axis in FIG. 15 indicates the Mg concentration [cm ⁻³ ] in the GaN layer. D1 in FIG. 15 indicates the Mg concentration before the heat treatment. D2 in FIG. 15 indicates the Mg concentration after the heat treatment.
When the Mg implantation step is performed by multi-stage implantation, as shown in D1 of FIG. 15, the Mg concentration is increased near the surface of the GaN layer so that the Mg concentration distribution is uniform (flat). It is preferable to set the acceleration voltage in multiple stages.

According to this, as shown by D2 in FIG. 15, near the surface of the GaN layer, the surface Mg concentration after the heat treatment can be increased, and the distribution of the Mg concentration after the heat treatment can be made flat. This makes it possible to reduce the variation in the threshold value between the plurality of vertical MOSFETs.
Further, even when the Mg implantation step is performed by multi-stage implantation, if the Mg implantation peak depth and the Mg implantation peak concentration are set in the same manner as in the case of single-stage implantation, the diffusion of Mg to the surface side of the GaN layer is suppressed. be able to.

(Modification 3)
In the above embodiment, the GaN layer 16 is epitaxially formed on the GaN substrate 10. Then, the formation of the drift region 22, the base region 23, the contact region 25, the source region 26, and the buried region 28 in the GaN layer 16 has been described. However, in the embodiment of the present invention, the formation of the GaN layer 16 is not essential. In the embodiment of the present invention, the drift region 22, the base region 23, the contact region 25, the source region 26, and the buried region 28 may be formed on the GaN substrate 10 instead of the GaN layer 16. In this case, the GaN substrate 10 is an example of the “gallium nitride layer” of the present invention.

(Other embodiments)
As described above, the present invention has been described by the embodiments and the modified examples. However, it should not be understood that the description and the drawings forming part of the present disclosure limit the present invention. From this disclosure, various alternative embodiments and modifications will be apparent to those skilled in the art.
For example, the gate insulating film 42 is not limited to the SiO ₂ film, but may be another insulating film. As the gate insulating film 42, a silicon oxynitride (SiON) film, a strontium oxide (SrO) film, a silicon nitride (Si ₃ N ₄ ) film, and an aluminum oxide (Al ₂ O ₃ ) film can be used. Further, as the gate insulating film 42, a composite film in which several single-layer insulating films are stacked can be used. A vertical MOSFET using an insulating film other than the SiO ₂ film as the gate insulating film 42 may be referred to as a vertical MISFET. MISFET means a more comprehensive insulated gate transistor including MOSFET.

  As an example of the manufacturing method, in the Mg implantation step in FIG. 4, Mg may be ion-implanted in a state where an insulating film is formed on the surface 16a of the GaN layer 16. This insulating film may be the insulating film 31 shown in FIG. Even with such a method, the vertical MOSFET 1 can be manufactured.

1,1A Vertical MOSFET
2 Impurity region 10 GaN substrate 10a First main surface 10b Second main surface 10V or more 16 GaN layer 16a Surface 22 Drift region 23 Base region 23 'Base formation region 25 Contact region 25' Contact formation region 26 Source region 26 'Source formation region 28 buried region 28 'buried formation region 28P peak position 28P' injection peak position 31 insulating film 33 protective film 35 first doped region 36 second doped region 42 gate insulating film 44 gate electrode 54 source electrode 56 drain electrode 58 electrode 70 protective film 74 guard ring structure 78 JTE structure 100 GaN semiconductor device 110 active region 112 gate pad 114 source pad 130 edge termination region 221 upper region 222 lower region 231 channel region

Claims (11)

A gallium nitride layer,
A first conductivity type source region provided in the gallium nitride layer;
A second conductivity type impurity region provided in the gallium nitride layer and adjacent to the source region in a first direction parallel to a surface of the gallium nitride layer and a second direction intersecting the surface.
In the second direction, the impurity region has a peak position where the concentration of the impurity of the second conductivity type is highest,
A depth from the surface of the gallium nitride layer to the peak position is 200 nm or more and 1500 nm or less;
A concentration of the second conductivity type impurity at the peak position is 1 × 10 ¹⁷ cm ⁻³ or more and 1 × 10 ¹⁹ cm ⁻³ or less;
The gallium nitride semiconductor device, wherein a concentration of the second conductivity type impurity on a surface of the impurity region is 1 × 10 ¹⁶ cm ⁻³ or more and 3 × 10 ¹⁸ cm ⁻³ or less.   The gallium nitride semiconductor device according to claim 1, wherein the impurity region includes at least one of magnesium and beryllium as the second conductivity type impurity. The impurity region is
A base region adjacent to the source region in the first direction and the second direction;
A buried region located on a side farther from the surface of the gallium nitride layer than the base region,
The buried region has a higher impurity concentration of the second conductivity type than the base region;
The gallium nitride semiconductor device according to claim 1, wherein the peak position exists in the buried region. A gate insulating film provided on the impurity region;
A gate electrode provided on the gate insulating film;
A source electrode provided on the source region;
The gallium nitride semiconductor device according to any one of claims 1 to 3, further comprising: a drain electrode provided on a back surface side opposite to a front surface of the gallium nitride layer.   The gallium nitride semiconductor device according to claim 4, wherein said gate insulating film is a silicon oxide film. A first conductivity type drift region provided in the gallium nitride layer and adjacent to the impurity region;
The gallium nitride semiconductor device according to claim 1, wherein the drift region has a lower concentration of a first conductivity type impurity than the source region. The drift region is
A doped region;
An undoped region adjacent to the doped region,
The doped region is closer to the surface of the gallium nitride layer than the undoped region,
The gallium nitride semiconductor device according to claim 6, wherein the doped region has a higher concentration of the first conductivity type impurity than the undoped region.   The gallium nitride semiconductor device according to claim 7, wherein the doped region includes at least one of silicon, oxygen, and germanium as the first conductivity type impurity.   The gallium nitride semiconductor device according to any one of claims 1 to 8, further comprising a gallium nitride single crystal substrate adjacent to a back surface opposite to a front surface of the gallium nitride layer. A gallium nitride layer,
A first conductivity type source region provided in the gallium nitride layer;
A gallium nitride semiconductor, provided in the gallium nitride layer, comprising a second conductivity type impurity region adjacent to the source region in a first direction parallel to a surface of the gallium nitride layer and in a second direction intersecting the surface. A method of manufacturing a device,
Ion-implanting a second conductivity type impurity into the gallium nitride layer;
Performing a heat treatment on the gallium nitride layer into which the impurity of the second conductivity type is implanted to form the impurity region,
In the step of ion implantation,
An implantation peak position of the impurity of the second conductivity type has a depth of 200 nm or more and 1500 nm or less from the surface of the gallium nitride layer;
The concentration of the impurity of the second conductivity type at the injection peak position is 1 × 10 ¹⁷ or more and 1 × 10 ¹⁹ cm ⁻³ or less.
A method for manufacturing a gallium nitride semiconductor device, wherein conditions for the ion implantation are set.   The method of manufacturing a gallium nitride semiconductor device according to claim 10, wherein, in the step of performing the heat treatment, a maximum temperature of the heat treatment is set to 800 ° C. or more and 2000 ° C. or less.

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