JP7404710B2 - Nitride semiconductor device and method for manufacturing nitride semiconductor device - Google Patents

Description

The present invention relates to a nitride semiconductor device and a method for manufacturing a nitride semiconductor device.

As an impurity concentration distribution in a semiconductor layer, for example, a retrograde profile is known in which the concentration is low on the surface side and high in the deep region (see, for example, Patent Document 1). Patent Document 1 discloses that after forming an impurity concentration distribution with a retrograde profile in a semiconductor layer, the activation rate of impurities is calculated, and the surface of the semiconductor layer is removed based on the calculated activation rate, thereby improving electrical performance. It is disclosed that variations in characteristics (threshold voltage and associated channel mobility, on-resistance, etc.) are suppressed. Patent Document 1 discloses sacrificial oxidation treatment and dry etching as methods for removing the surface of a semiconductor layer.

JP2015-60841A

The technique disclosed in Patent Document 1 requires a large number of steps, such as a step of calculating the activation rate of impurities, a sacrificial oxidation treatment step, and a dry etching step, in order to suppress variations in electrical characteristics.

The present invention has been made in view of the above circumstances, and provides a nitride semiconductor device that can achieve both good channel characteristics and good breakdown voltage, and a method for manufacturing this nitride semiconductor device while suppressing an increase in the number of manufacturing steps. It is an object of the present invention to provide a method for manufacturing a nitride semiconductor device that can be manufactured at the same time.

In order to solve the above problems, a nitride semiconductor device according to one embodiment of the present invention includes a nitride semiconductor layer, a first conductivity type well region provided in the nitride semiconductor layer, and a surface side of the well region. The semiconductor device includes a second conductivity type source region provided, a gate insulating film provided on the well region, and a gate electrode provided on the gate insulating film. The well region has a first end located on the source region side and a second end located on the opposite side of the first end in the surface direction of the well region. The impurity concentration of the first conductivity type on the surface of the well region has a distribution that changes from the first end toward the second end and has a maximum value between the first end and the second end. have The impurity concentration of the first conductivity type in the depth direction of the well region changes from the surface of the well region toward the bottom of the well region, and has a distribution in which the maximum value exists between the surface and the bottom of the well region. .

A method for manufacturing a nitride semiconductor device according to one embodiment of the present invention includes a step of forming a first conductivity type well region in a nitride semiconductor layer, and a step of forming a second conductivity type source region on the surface side of the well region. The method includes the steps of: forming a gate insulating film on the well region; and forming a gate electrode on the gate insulating film. The step of forming the well region includes a step of forming a mask having an inclined surface inclined with respect to the surface direction of the well region on the nitride semiconductor layer, and a step of forming a mask on the nitride semiconductor layer with the mask formed thereon from the mask side. and a step of ion-implanting impurities of one conductivity type. In the step of forming the mask, a sloped surface is placed on a region of the nitride semiconductor layer where a well region is to be formed.

According to the present invention, it is possible to provide a nitride semiconductor device and a method for manufacturing the nitride semiconductor device that can easily suppress variations in threshold voltage.

FIG. 1 is a cross-sectional view showing a configuration example of a GaN semiconductor device according to Embodiment 1 of the present invention. FIG. 2 is a graph showing an example of the Mg concentration distribution in the depth direction of the well region in the GaN semiconductor device according to the first embodiment of the present invention. FIG. 3 is a graph showing an example of the distribution of surface Mg concentration in the well region in the GaN semiconductor device according to the first embodiment of the present invention. FIG. 4 is a cross-sectional view showing a method for manufacturing a GaN semiconductor device according to Embodiment 1 of the present invention in order of steps. FIG. 5 is a cross-sectional view showing a method for manufacturing a GaN semiconductor device according to Embodiment 1 of the present invention in order of steps. FIG. 6 is a cross-sectional view showing a method for manufacturing a GaN semiconductor device according to Embodiment 1 of the present invention in order of steps. FIG. 7 is a cross-sectional view showing a method for manufacturing a GaN semiconductor device according to Embodiment 1 of the present invention in order of steps. FIG. 8 is a cross-sectional view showing a method for manufacturing a GaN semiconductor device according to Embodiment 1 of the present invention in order of steps. FIG. 9 is a cross-sectional view showing a method for manufacturing a GaN semiconductor device according to Embodiment 1 of the present invention in order of steps. FIG. 10 is a cross-sectional view showing a method for manufacturing a GaN semiconductor device according to Embodiment 1 of the present invention in order of steps. FIG. 11 is a cross-sectional view showing a method for manufacturing a GaN semiconductor device according to Embodiment 1 of the present invention in order of steps. FIG. 12 is a cross-sectional view showing a method for manufacturing a GaN semiconductor device according to Embodiment 1 of the present invention in order of steps. FIG. 13 is a graph showing an example of the Mg concentration distribution in the depth direction of the well region according to the second embodiment of the present invention. FIG. 14 is a graph showing an example of the distribution of surface Mg concentration in the well region according to Embodiment 2 of the present invention. FIG. 15 is a graph showing an example (Modification 1) of Mg concentration distribution in the depth direction of the well region according to Embodiment 2 of the present invention. FIG. 16 is a graph showing an example (Modification 1) of the distribution of surface Mg concentration in the well region according to Embodiment 2 of the present invention. FIG. 17 is a graph showing an example (modification example 2) of the Mg concentration distribution in the depth direction of the well region according to the second embodiment of the present invention. FIG. 18 is a graph showing an example (modified example 2) of the distribution of the surface Mg concentration in the well region according to the second embodiment of the present invention. FIG. 19 is a graph showing an example (modified example 3) of the Mg concentration distribution in the depth direction of the well region according to the second embodiment of the present invention. FIG. 20 is a graph showing an example (modified example 3) of the distribution of surface Mg concentration in the well region according to the second embodiment of the present invention. FIG. 21 is a graph showing an example (modified example 4) of the Mg concentration distribution in the depth direction of the well region according to the second embodiment of the present invention. FIG. 22 is a graph showing an example (modified example 4) of the distribution of the surface Mg concentration in the well region according to the second embodiment of the present invention. FIG. 23 is a graph showing an example (modified example 5) of the Mg concentration distribution in the depth direction of the well region according to the second embodiment of the present invention. FIG. 24 is a graph showing an example (modified example 5) of the distribution of surface Mg concentration in the well region according to the second embodiment of the present invention. FIG. 25 is a cross-sectional view showing a configuration example of a GaN semiconductor device according to Embodiment 3 of the present invention. FIG. 26 is a cross-sectional view showing a part of the manufacturing process of a GaN semiconductor device according to a comparative example of the present invention. FIG. 27 is a graph showing the Mg concentration distribution in the depth direction of the well region according to the comparative example of the present invention. FIG. 28 is a graph showing the distribution of surface Mg concentration in a well region according to a comparative example of the present invention.

Embodiments of the present invention will be described below. In the description of the drawings below, the same or similar parts are designated by the same or similar symbols. However, it should be noted that the drawings are schematic and the relationship between thickness and planar dimension, the ratio of the thickness of each device and each member, etc. may differ from reality. Therefore, specific thickness and dimensions should be determined with reference to the following explanation. Furthermore, it goes without saying that the drawings include portions with different dimensional relationships and ratios.

Furthermore, in the following description, directions may be explained using terms such as the X-axis direction, the Y-axis direction, and the Z-axis direction. For example, the X-axis direction or the Y-axis direction is the surface direction of the well region 3, which will be described later. The Z-axis direction is the depth direction of the well region 3, which will be described later. The X-axis direction, Y-axis direction, and Z-axis direction are orthogonal to each other.

Furthermore, in the following description, the direction of the arrow on the Z-axis may be referred to as "up", and the direction opposite to the arrow on the Z-axis may be referred to as "down". "Above" and "below" do not necessarily mean a direction perpendicular to the ground. That is, the "up" and "down" directions are not limited to the direction of gravity. "Top" and "bottom" are merely convenient expressions for specifying relative positional relationships among regions, layers, films, substrates, etc., and do not limit the technical idea of the present invention. For example, if the page is rotated 180 degrees, "top" becomes "bottom" and "bottom" becomes "top".

In the following description, a case will be exemplified in which the first conductivity type is p type and the second conductivity type is n type. However, the conductivity types may be selected in a reverse relationship, with the first conductivity type being n type and the second conductivity type being p type. Further, + or - added to p or n means that the semiconductor region has a relatively high or low impurity concentration, respectively, compared to a semiconductor region without + or -. However, even if the semiconductor regions are labeled with the same p and p, this does not mean that the impurity concentrations of the respective semiconductor regions are strictly the same.

<Embodiment 1>
(structure)
FIG. 1 is a cross-sectional view showing a configuration example of a gallium nitride semiconductor device (hereinafter referred to as a GaN semiconductor device) 100 according to Embodiment 1 of the present invention. The GaN semiconductor device 100 is an example of a nitride semiconductor device of the present invention, and is a planar gate vertical MOSFET (Metal Oxide Semiconductor Field Effect Transistor). As shown in FIG. 1, a GaN semiconductor device 100 includes a gallium nitride substrate (an example of the "first nitride semiconductor layer" of the present invention; hereinafter referred to as a GaN substrate) 1 and a GaN layer 2 (an example of the "second nitride semiconductor layer" of the present invention). a semiconductor layer (an example of a semiconductor layer), a gate insulating film 5, a gate electrode 6, a source electrode 7, and a drain electrode 8.

GaN substrate 1 is a GaN single crystal substrate. The GaN substrate 1 is a first conductivity type (n type) substrate, for example, an n ⁺ type substrate. The n-type impurity contained in the GaN substrate 1 is one or more elements of Si (silicon), O (oxygen), and Ge (germanium). For example, the n-type impurity contained in the GaN substrate 1 is Si or O. The impurity concentration of Si or O in the GaN substrate 1 is 2×10 ¹⁸ cm ⁻³ or more.

Note that the GaN substrate 1 may be a low-dislocation free-standing substrate with a dislocation density of less than 1×10 ⁷ cm ⁻² . Since the GaN substrate 1 is a low dislocation free-standing substrate, the dislocation density of the GaN layer 2 formed on the GaN substrate 1 is also low. Further, by using a low-dislocation free-standing substrate as the GaN substrate 1, even when a large-area power device is formed on the GaN substrate 1, leakage current in the power device can be reduced. Thereby, the manufacturing apparatus can manufacture power devices with a high rate of non-defective products. Further, in the heat treatment, it is possible to prevent ion-implanted impurities from deeply diffusing along dislocations.

GaN layer 2 is provided on surface 1a of GaN substrate 1. GaN layer 2 is provided on surface 1a of GaN substrate 1. GaN layer 2 is an n ⁻ type GaN single crystal layer, and is a layer epitaxially formed on surface 1 a of GaN substrate 1 . The GaN layer 2 is provided with a p-type well region 3 and an n ⁺ -type source region 4. In GaN layer 2, a region where well region 3 and source region 4 are not provided may be called a drift region. The drift region is a region that functions as a current path between the GaN substrate 1 and the well region 3.

The well region 3 is formed by ion-implanting p-type impurities from the surface 2a side of the GaN layer 2 and subjecting it to heat treatment. The p-type impurity is, for example, magnesium. The surface D1 of the well region 3 is the same surface as the surface 2a of the GaN layer 2 shown in FIG. Further, the well region 3 has a first end P1 located on the source region 4 side, and a second end P2 located on the opposite side of the source region 4 in the surface direction of the well region 3. In the well region 3, the surface D1 in contact with the gate insulating film 5 and its vicinity are the channel region 10 of the vertical MOSFET.

In addition, in FIG. 1, the concentration of magnesium (Mg) contained in the p-type well region 3 is schematically shown by a perfect circle. The larger the perfect circle, the higher the Mg concentration in the perfect circle and its vicinity, and the smaller the perfect circle, the lower the Mg concentration in the perfect circle and its vicinity.

The source region 4 is formed by ion-implanting n-type impurities from the surface 2a side of the GaN layer 2 and subjecting it to heat treatment. The n-type impurity is, for example, one or more elements among Si, O, and Ge. Source region 4 is provided on the surface 2 a side of GaN layer 2 and located inside well region 3 . The sides and bottom of the source region 4 are in contact with the well region 3 . The source region 4 and the well region 3 are in contact with each other in the X-axis direction, the Y-axis direction, and the Z-axis direction.

Gate insulating film 5 is provided on well region 3 . The gate insulating film 5 is, for example, a silicon oxide film (SiO ₂ film) or an aluminum oxide (Al ₂ O ₃ ) film. The thickness of the gate insulating film 5 is, for example, 50 nm or more and 100 nm or less. Gate electrode 6 is provided on gate insulating film 5 . The gate electrode 6 is a planar electrode provided on the flat gate insulating film 5. The gate electrode 6 is made of polysilicon doped with impurities, for example.

Source electrode 7 is provided on source region 4 and is electrically connected to source region 4 . Although not shown, the source electrode 7 may be provided so as to cover the gate electrode 6 via an interlayer insulating film. The source electrode 7 is made of, for example, Al or an Al-Si alloy. Further, the source electrode 7 may have a barrier metal layer between it and the surface 2a of the GaN layer 2. Titanium (Ti) may be used as a material for the barrier metal layer. The drain electrode 8 is provided on the back surface 1b side of the GaN substrate 1 and is electrically connected to the GaN substrate 1. The drain electrode 8 is made of, for example, Al or an Al-Si alloy.

FIG. 2 is a graph showing an example of the Mg concentration distribution in the depth direction of the well region 3 in the GaN semiconductor device 100 according to the first embodiment of the present invention. In FIG. 2, the horizontal axis indicates the position in the depth direction of the well region 3, and the vertical axis indicates the Mg concentration. FIG. 2 shows the Mg concentration distribution at the position of the virtual line VL shown in FIG. 1 as an example of the Mg concentration distribution. The virtual line VL is parallel to the depth direction of the well region 3.

As shown in FIG. 2, the Mg concentration in the well region 3 has a retrograde profile in the depth direction of the well region 3. A retrograde profile is a concentration distribution in which the concentration changes as the position changes in one direction. For example, the Mg concentration in the depth direction of the well region 3 continuously changes from the surface D1 of the well region 3 toward the bottom D2 of the well region 3. Between the surface D1 and the bottom D2 of the well region 3, there is a peak position D3 (an example of the "second peak position" of the present invention) where the Mg concentration reaches the maximum value C2.

The Mg concentration increases as it approaches the peak position D3 from the surface D1 of the well region 3. The Mg concentration decreases as it approaches the bottom D2 from the peak position D3. At the peak position D3, the Mg concentration becomes maximum and maximum. As shown in FIG. 2, in the depth direction of the well region 3, only one peak position D3 exists between the surface D1 and the bottom D2.

FIG. 3 is a graph showing an example of the distribution of Mg concentration (hereinafter referred to as surface Mg concentration) on the surface D1 of the well region 3 in the GaN semiconductor device 100 according to Embodiment 1 of the present invention. In FIG. 3, the horizontal axis indicates the position in the surface direction of the well region 3, and the vertical axis indicates the surface Mg concentration.

As shown in FIG. 3, the surface Mg concentration of the well region 3 has a retrograde profile in the surface direction of the well region 3. For example, the surface Mg concentration of the well region 3 continuously changes from the first end P1 to the second end P2 of the well region 3. Between the first end P1 and the second end P2 of the well region 3, there is a peak position P3 (an example of the "first peak position" of the present invention) where the Mg concentration reaches the maximum value C2.

The Mg concentration increases as the distance from the first end P1 of the well region 3 approaches the peak position P3. The Mg concentration decreases as it approaches the second end P2 from the peak position P3. At the peak position P3, the Mg concentration becomes maximum and maximum. As shown in FIG. 3, in the surface direction of the well region 3, only one peak position P3 exists between the first end P1 and the second end P2.

Note that the surface Mg concentration of the well region 3 and the Mg concentration in the depth direction of the well region 3 are preferably 1×10 ¹⁶ cm ⁻³ or more and 1×10 ²⁰ cm ⁻³ or less, respectively. This makes it possible to achieve both high breakdown voltage and on-characteristics. Further, the surface Mg concentration of the well region 3 and the Mg concentration in the depth direction of the well region 3 are more preferably 1×10 ¹⁷ cm ⁻³ or more and 1×10 ¹⁸ cm ⁻³ or less. This allows better control of breakdown voltage and on-characteristics.

(Production method)
Next, a method for manufacturing the GaN semiconductor device 100 according to Embodiment 1 of the present invention will be described. 4 to 12 are cross-sectional views showing the method for manufacturing the GaN semiconductor device 100 according to the first embodiment of the present invention in order of steps. The GaN semiconductor device 100 is manufactured using various manufacturing apparatuses such as a film forming apparatus, an exposure apparatus, an etching apparatus, and an ion implantation apparatus.

As shown in FIG. 4, the manufacturing apparatus forms a GaN layer 2 on a surface 1a of a GaN substrate 1. As shown in FIG. For example, the manufacturing apparatus epitaxially forms an n ⁻ type GaN layer 2 on an n ⁺ type GaN substrate 1 by metal organic CVD (MOCVD), halide vapor phase epitaxy (HVPE), or the like. Note that the GaN layer 2 includes a planned region 3' in which a well region will be formed in a later step, and a planned region 4' in which a source region will be formed in a later step.

Next, the manufacturing apparatus forms an insulating film 21 on the surface 2a of the GaN layer 2. The insulating film 21 is, for example, a silicon oxide film (SiO ₂ film). Next, as shown in FIG. 5, the manufacturing apparatus forms a resist mask 22 on the insulating film 21. The resist mask 22 has a shape that opens above the region 4' where the source is to be formed and covers the other region. Furthermore, the end of the resist mask 22 on the opening side has an inclined surface 22 a inclined with respect to the surface 2 a of the GaN layer 2 . The inclined surface 22a is inclined so that the thickness of the resist mask 22 gradually decreases as it approaches the opening side. The manufacturing apparatus forms the resist mask 22 so that the inclined surface 22a is located on the region 3' where the well region is to be formed. Note that the inclination angle of the inclined surface 22a can be adjusted to a desired value by arbitrarily selecting the type of resist, the type of photomask, the exposure conditions of the resist, and the like.

Next, as shown in FIG. 6, the manufacturing apparatus performs a dry etching process on the resist mask 22 and the insulating film 21. As a result, a mask 21M is formed from the insulating film 21. Since the insulating film 21 is dry-etched while being covered with the resist mask 22, the shape of the resist mask 22 is reflected on the mask 21M. The mask 21M is formed in a shape having an inclined surface 21a on a region 3' where a well region is to be formed.

Next, as shown in FIG. 7, the manufacturing apparatus removes the remaining resist mask 22 from above the mask 21M. Next, the manufacturing apparatus implants magnesium (Mg) ions into the GaN layer 2 covered with the mask 21M from the mask 21M side. As a result, a p-type well region 3 is formed in the GaN layer 2, as shown in FIG. In this ion implantation step, since the slope 21a of the mask 21M is located on the planned region 3', the Mg implantation peak position is along the slope 21a. The Mg concentration distribution in the depth direction of the well region 3 has a shape as shown in FIG. 2, and the Mg concentration distribution in the surface direction of the well region 3 has a shape as shown in FIG.

Next, as shown in FIG. 9, the manufacturing apparatus removes the mask 21M from above the GaN layer 2. Next, as shown in FIG. 10, the manufacturing apparatus forms a resist mask 23 on the GaN layer. The resist mask 23 has a shape that opens above the region 4' where the source is to be formed and covers the other region. Next, the manufacturing apparatus ion-implants an n-type impurity such as Si or O into the GaN layer 2 covered with the resist mask 23 from the resist mask 23 side. As a result, the source region 4 is formed in the planned region 4'. Next, the manufacturing apparatus removes the resist mask 23 from above the GaN layer 2.

Next, the manufacturing apparatus forms a protective film (not shown) on the GaN layer 2. The protective film is a film that has high heat resistance, prevents impurities from diffusing from the protective film toward the GaN layer 2, and can be selectively removed with respect to the GaN layer 2. High heat resistance means, for example, that the protective film does not substantially decompose to the extent that pits (through openings) are not formed in the protective film even when heat treated at a temperature of 1000°C or higher and 1200°C or lower. .

Next, the manufacturing apparatus performs heat treatment on the GaN layer 2 at a maximum temperature of 1000° C. or more and 1200° C. or less. This heat treatment is, for example, rapid heat treatment. By this heat treatment, p-type impurities such as Mg and n-type impurities such as Si and O introduced into the GaN layer 2 are activated. Next, the manufacturing apparatus removes the protective film from above the GaN layer.

Next, as shown in FIG. 11, the manufacturing apparatus forms a gate insulating film 5 on the GaN layer 2. Next, as shown in FIG. 12, the manufacturing apparatus forms a gate electrode 6 on the gate insulating film 5. Next, the manufacturing apparatus forms a source electrode 7 (see FIG. 1) on the source region 4. Through the above steps, the GaN semiconductor device 100 shown in FIG. 1 is completed.

As explained above, the GaN semiconductor device 100 according to the first embodiment of the present invention includes the GaN layer 2, the p-type well region 3 provided in the GaN layer 2, and the p-type well region 3 provided on the surface D1 side of the well region 3. The semiconductor device includes an n ⁺ type source region 4, a gate insulating film 5 provided on the well region 3, and a gate electrode 6 provided on the gate insulating film 5. The well region 3 has a first end P1 located on the source region 4 side, and a second end P2 located on the opposite side of the first end P1 in the surface direction of the well region 3. The surface Mg concentration of the well region 3 has a distribution that changes from the first end P1 to the second end P2 and has a maximum value C2 between the first end P1 and the second end P2. have The Mg concentration in the depth direction of the well region 3 changes from the surface D1 of the well region 3 toward the bottom D2, and has a distribution in which the maximum value C2 exists between the surface D1 and the bottom D2.

In the well region 3, the surface D1 of the portion located between the first end P1 and the second end P2 and the vicinity thereof become the channel region 10. The surface Mg concentration of the channel region 10 has a retrograde profile in the surface direction, and there is a peak position P3 in the channel region 10 where the surface Mg concentration has a maximum value C2. The channel characteristics (threshold voltage, mobility) of the GaN semiconductor device 100 depend on the maximum value C2 of the surface Mg concentration of the channel region 10. Since the peak position P3 exists in the channel region 10, the channel characteristics of the GaN semiconductor device 100 are stable.

Further, the Mg concentration in the well region 3 has a retrograde profile not only in the surface direction of the well region 3 but also in the depth direction of the well region 3. A peak position D3 exists between the surface D1 and the bottom D2 of the well region 3, where the Mg concentration reaches the maximum value C2. The breakdown voltage of the GaN semiconductor device 100 depends on the Mg concentration at a position deeper than the channel region 10 in the well region 3 . Since the peak position D3 exists deep in the well region 3, the breakdown voltage of the GaN semiconductor device 100 is high. Thereby, the GaN semiconductor device 100 has both good channel characteristics and good breakdown voltage.

The method for manufacturing the GaN semiconductor device 100 according to the first embodiment of the present invention includes the steps of forming a p-type well region 3 in the GaN layer 2, and forming an n ⁺ -type source region 4 on the surface D1 side of the well region 3. , a step of forming a gate insulating film 5 on the well region 3 , and a step of forming a gate electrode 6 on the gate insulating film 5 . The step of forming the well region 3 includes a step of forming a mask 21M having an inclined surface 21a inclined with respect to the surface direction of the well region 3 on the GaN layer 2, and a step of forming a mask on the GaN layer 2 on which the mask 21M is formed. and a step of ion-implanting Mg from the 21M side. In the step of forming the mask 21M, the inclined surface 21a is arranged on the GaN layer 2 on the planned region 3' where the well region 3 will be formed.

According to this manufacturing method, the GaN semiconductor device 100 can be easily and stably manufactured. For example, in the process of ion-implanting Mg, if variations occur in the Mg implantation energy or implantation angle, the peak position P3 of the surface Mg concentration will vary between the first end P1 and the second end P2. However, the Mg concentration at the peak position P3 (ie, the maximum value C2 of the surface Mg concentration) is constant. Therefore, in the GaN semiconductor device 100 manufactured by the above manufacturing method, variations in channel characteristics are suppressed. Similarly, in the process of ion-implanting Mg, if variations occur in the Mg implantation energy or implantation angle, the Mg concentration peak position D3 in the depth direction of the well region 3 will be located between the surface D1 and the bottom D2. Although it fluctuates, the Mg concentration at the peak position D3 (that is, the maximum value C2 of the Mg concentration) is constant. Therefore, in the GaN semiconductor device 100 manufactured by the above manufacturing method, variations in breakdown voltage are suppressed.

Further, in the above manufacturing method, the p-type well region 3 is formed by ion-implanting Mg into the GaN layer 2 through the mask 21M having the inclined surface 21a. Therefore, the shape of the well region 3 is curved to reflect the shape of the inclined surface 21a. This alleviates the electric field concentration at the end of the well region 3, and is expected to further improve the breakdown voltage.

According to the above manufacturing method, in order to suppress variations in channel characteristics and breakdown voltage, the activation rate of Mg is calculated, a sacrificial oxide film is formed on the GaN layer 2, and the sacrificial oxide film is dried. No need for etching. Therefore, the above manufacturing method can manufacture the GaN semiconductor device 100 that can have both good channel characteristics and good breakdown voltage while suppressing an increase in the number of steps.

<Embodiment 2>
In the first embodiment described above, as shown in FIGS. 2 and 3, there is a peak position D3 where the Mg concentration is maximum between the surface D1 and the bottom D2 of the well region 3, and A case has been described in which there is one peak position P3 at which the surface Mg concentration is maximum between the end P1 and the second end P2. However, embodiments of the present invention are not limited thereto. In the embodiment of the present invention, the same number of peak positions D3 and P3 may exist.

FIG. 13 is a graph showing an example of the Mg concentration distribution in the depth direction of the well region 3 according to the second embodiment of the present invention. In FIG. 13, the horizontal axis indicates the position in the depth direction of the well region 3, and the vertical axis indicates the Mg concentration. FIG. 14 is a graph showing an example of the distribution of surface Mg concentration in the well region 3 according to the second embodiment of the present invention. In FIG. 14, the horizontal axis indicates the position of the well region 3 in the surface direction, and the vertical axis indicates the surface Mg concentration.

As shown in FIG. 13, between the surface D1 and the bottom D2 of the well region 3, there are two peak positions D31 and D32 where the Mg concentration is maximum and maximum (an example of the "second peak position" of the present invention). exists. As shown in FIG. 14, between the first end P1 and the second end P2 of the well region 3, there are two peak positions P31 and P32 (in the present invention) where the surface Mg concentration is maximum and maximum. 1 peak position) exists. Even in such an embodiment, the GaN semiconductor device 100 can have both good channel characteristics and good breakdown voltage.

The peak positions D31, D32, P31, and P32 can be formed, for example, by ion-implanting Mg in two steps with different implantation energies in the process shown in FIG. For example, in the process shown in FIG. 8, the manufacturing apparatus implants Mg ions with a first implantation energy, and then implants Mg ions with a second implantation energy different from the first implantation energy. Alternatively, the peak positions D31, D32, P31, and P32 can be determined by applying Mg in two steps using two types of masks 21M with different thicknesses or angles of inclination of the inclined surfaces 21a, for example, in the process shown in FIG. It can be formed by ion implantation.

(Modification 1)
In the embodiment of the present invention, the Mg concentration at the peak position D31 and the Mg concentration at the peak position D32 may not have the same value. Similarly, the surface Mg concentration at peak position P31 and the surface Mg concentration at peak position P32 may not have the same value.

FIG. 15 is a graph showing an example (Modification 1) of the Mg concentration distribution in the depth direction of the well region 3 according to the second embodiment of the present invention. The horizontal and vertical axes in FIG. 15 are the same as in FIG. 13. FIG. 16 is a graph showing an example (modification 1) of the distribution of surface Mg concentration in the well region 3 according to the second embodiment of the present invention. The horizontal and vertical axes in FIG. 16 are the same as in FIG. 14.

As shown in FIG. 15, the Mg concentration at the peak position D31 may be the maximum value C2, and the Mg concentration at the peak position D32 may be a value C3 smaller than the maximum value C2. As shown in FIG. 16, the surface Mg concentration at the peak position P31 may be the maximum value C2, and the surface Mg concentration at the peak position D32 may be a value C3 smaller than the maximum value C2. Even in such an embodiment, the GaN semiconductor device 100 can have both good channel characteristics and good breakdown voltage.

(Modification 2)
FIG. 17 is a graph showing an example (modified example 2) of the Mg concentration distribution in the depth direction of the well region 3 according to the second embodiment of the present invention. The horizontal and vertical axes in FIG. 17 are the same as in FIG. 13. FIG. 18 is a graph showing an example (modified example 2) of the distribution of surface Mg concentration in the well region 3 according to the second embodiment of the present invention. The horizontal and vertical axes in FIG. 18 are the same as in FIG. 14.

As shown in FIG. 17, the Mg concentration at the peak position D32 is the maximum value C2, and the Mg concentration at the peak position D31 may be a value C3 smaller than the maximum value C2. As shown in FIG. 18, the surface Mg concentration at the peak position P32 may be the maximum value C2, and the surface Mg concentration at the peak position D31 may be a value C3 smaller than the maximum value C2. Even in such an embodiment, the GaN semiconductor device 100 can have both good channel characteristics and good breakdown voltage.

(Modification 3)
FIG. 19 is a graph showing an example (modified example 3) of the Mg concentration distribution in the depth direction of the well region 3 according to the second embodiment of the present invention. The horizontal and vertical axes in FIG. 19 are the same as in FIG. 13. FIG. 20 is a graph showing an example (modified example 3) of the distribution of surface Mg concentration in the well region 3 according to the second embodiment of the present invention. The horizontal and vertical axes in FIG. 20 are the same as in FIG. 14.

As shown in FIG. 19, between the surface D1 and the bottom D2 of the well region 3, there are three peak positions D31, D32, and D33 (an example of the "second peak position" of the present invention) where the Mg concentration is maximum. may exist. Among the three peak positions D31, D32, and D33, the Mg concentration at the peak position D32 may be the maximum value C2, and the Mg concentration at the peak positions D31 and D33 may be a value C3 smaller than the maximum value C2.

As shown in FIG. 20, between the first end P1 and the second end P2 of the well region 3, there are three peak positions P31, P32, and P33 (the "first" 1 peak position) may exist. Among the three peak positions P31, P32, and P33, the surface Mg concentration at the peak position P32 may be the maximum value C2, and the surface Mg concentration at the peak positions P31 and P33 may be a value C3 smaller than the maximum value C2. Even in such an embodiment, the GaN semiconductor device 100 can have both good channel characteristics and good breakdown voltage.

The peak positions D31 to D33 and P31 to P33 can be formed by ion-implanting Mg three times at different implantation energies, for example, in the process shown in FIG. Alternatively, the peak positions D31 to D33 and P31 to P33 can be determined by applying Mg in three times using three types of masks 21M with different thicknesses or inclination angles of the inclined surfaces 21a, for example, in the process shown in FIG. It can be formed by ion implantation.

(Modification 4)
In the embodiment of the present invention, among the three peak positions D31 to D33, the peak position where the Mg concentration is maximum is not limited to the peak position D32. Similarly, among the three peak positions P31 to P33, the peak position where the surface Mg concentration is maximum is not limited to peak position P32.

FIG. 21 is a graph showing an example (modified example 4) of the Mg concentration distribution in the depth direction of the well region 3 according to the second embodiment of the present invention. The horizontal and vertical axes in FIG. 21 are the same as in FIG. 13. FIG. 22 is a graph showing an example (modified example 4) of the distribution of surface Mg concentration in the well region 3 according to the second embodiment of the present invention. The horizontal and vertical axes in FIG. 22 are the same as in FIG. 24.

As shown in FIG. 21, among the three peak positions D31, D32, and D33, the Mg concentration at the peak position D31 is the maximum value C2, and the Mg concentration at the peak positions D32 and D33 is a value C3 smaller than the maximum value C2. There may be. As shown in FIG. 22, among the three peak positions P31, P32, and P33, the surface Mg concentration at the peak position P31 is the maximum value C2, and the surface Mg concentration at the peak positions P32 and P33 is a value smaller than the maximum value C2. It may be C3. Even in such an embodiment, the GaN semiconductor device 100 can have both good channel characteristics and good breakdown voltage.

(Modification 5)
FIG. 23 is a graph showing an example (modified example 5) of the Mg concentration distribution in the depth direction of the well region 3 according to the second embodiment of the present invention. The horizontal and vertical axes in FIG. 23 are the same as in FIG. 13. FIG. 24 is a graph showing an example (modification 5) of the distribution of surface Mg concentration in the well region 3 according to the second embodiment of the present invention. The horizontal and vertical axes in FIG. 24 are the same as in FIG. 14.

As shown in FIG. 23, among the three peak positions D31, D32, and D33, the Mg concentration at the peak position D33 is the maximum value C2, and the Mg concentration at the peak positions D31 and D32 is a value C3 smaller than the maximum value C2. There may be. As shown in FIG. 24, among the three peak positions P31, P32, and P33, the surface Mg concentration at the peak position P33 is the maximum value C2, and the surface Mg concentration at the peak positions P31 and P32 is a value smaller than the maximum value C2. It may be C3. Even in such an embodiment, the GaN semiconductor device 100 can have both good channel characteristics and good breakdown voltage.

<Embodiment 3>
FIG. 25 is a cross-sectional view showing a configuration example of a GaN semiconductor device 100A according to Embodiment 3 of the present invention. As shown in FIG. 25, the GaN semiconductor device 100A includes an n-type JFET region 30 (an example of the "second conductivity type impurity region" of the present invention) provided on the surface side of the GaN layer 2. The JFET region 30 is sandwiched between the p-type well regions 3 from both sides in the surface direction (for example, the X-axis direction). The JFET region 30 has a higher concentration of n-type impurities than the n ^- type GaN layer 2 (n ^- type drift layer). Even with such a configuration, the GaN semiconductor device 100A can have both good channel characteristics and good breakdown voltage.

Further, in the GaN semiconductor device 100A, the electrical resistance of the current path from the drain electrode 8 to the well region 3 is lower than that of the GaN semiconductor device 100 shown in FIG. , on-resistance can be reduced. Further, at the pn junction between the p-type well region 3 and the n-type JFET region 30, the depletion layer spreads closer to the well region 3 than the pn junction between the well region 3 and the n-type drift layer. Therefore, the GaN semiconductor device 100A can further improve the breakdown voltage compared to the GaN semiconductor device 100 shown in FIG. The GaN semiconductor device 100A can have good channel characteristics, good breakdown voltage, and good on-resistance.

<Comparative example>
Next, a comparative example of the present invention will be explained. FIG. 26 is a cross-sectional view showing a part of the manufacturing process of a GaN semiconductor device 200 according to a comparative example of the present invention. As shown in FIG. 26, the GaN semiconductor device 200 includes an n ⁺ type GaN substrate 101, an n ⁻ type GaN layer 102 provided on the GaN substrate 101, and a p type well provided on the GaN layer 102. A region 103 and an n ⁺ type source region 104 provided on the surface side of the well region 103.

In the step of forming the p-type well region 103, Mg ions are implanted using a highly vertical mask 121. The side surface of the end of the mask 121 is substantially perpendicular to the surface of the GaN layer 102. As shown in FIG. 26, in the comparative example, since a highly vertical mask 121 is used, the Mg injection peak is parallel to the surface of the GaN layer 102.

FIG. 27 is a graph showing the Mg concentration distribution in the depth direction of the well region 103 according to a comparative example of the present invention. FIG. 28 is a graph showing the distribution of surface Mg concentration in the well region 3 according to a comparative example of the present invention. In FIGS. 27 and 28, Comparative Example 1 shows a case where Mg implantation energy is low, and Comparative Example 2 shows a case where Mg implantation energy is high.

As shown in FIG. 27, the Mg concentration distribution in the comparative example has a retrograde profile in the depth direction of the well region 103. In Comparative Example 1 with low implantation energy and Comparative Example 2 with high implantation energy, the maximum value of the Mg concentration in the depth direction is C21, which is the same value. On the other hand, as shown in FIG. 28, the surface Mg concentration distribution of the comparative example is constant in the surface direction of the well region 103. In Comparative Example 1 where the implantation energy is low, the Mg implantation peak is located in a shallow region, whereas in Comparative Example 2 where the implantation energy is high, the Mg implantation peak is located in a deep region. Therefore, a difference occurs in the surface Mg concentration between Comparative Examples 1 and 2. The surface Mg concentration C12 of Comparative Example 2 has a lower value than the surface Mg concentration C11 of Comparative Example 1.

In this way, in the GaN semiconductor device 200 according to the comparative example, variations in Mg implantation energy and implantation angle are reflected in the surface Mg concentration of the well region 103. Therefore, in the GaN semiconductor device 200, the surface Mg concentration of the well region 103 tends to vary, and the channel characteristics tend to fluctuate.

<Comparison of characteristics>
Table 1 shows the results of comparing the characteristics of Embodiments 1 to 3 of the present invention and the comparative example. Table 1 shows the Mg surface concentration distribution, threshold value, and breakdown voltage as characteristics. Further, in Table 1, ◯ means good, and × means bad.

In Embodiments 1 to 3, variations in the maximum surface Mg concentration of the channel region 10 are unlikely to occur, and a stable threshold value can be obtained. On the other hand, in the comparative example, the maximum value of the surface Mg concentration in the channel region tends to vary, and the threshold value tends to fluctuate. Regarding the breakdown voltage, in both Embodiments 1 to 3 and the comparative example, the peak of the Mg concentration exists in the deep region of the well region, so that high breakdown voltage characteristics can be obtained.

<Other embodiments>
As described above, the present invention has been described by way of embodiments and modifications, but the statements and drawings that form part of this disclosure should not be understood as limiting the present invention. Various alternative embodiments and modifications will be apparent to those skilled in the art from this disclosure.

For example, a silicon oxynitride (SiON) film, a strontium oxide (SrO) film, or a silicon nitride (Si ₃ N ₄ ) film can also be used for the gate insulating film 5 . Furthermore, a composite film or the like in which several single-layer insulating films are laminated can be used as the gate insulating film 5. A vertical MOSFET using an insulating film other than the SiO ₂ film as the gate insulating film 5 may be referred to as a vertical MISFET. MISFET refers to the more general insulated gate transistor, which includes MOSFET.

Thus, it goes without saying that the present invention includes various embodiments not described here. At least one of various omissions, substitutions, and modifications of the constituent elements can be made without departing from the gist of the embodiment and each modification described above. Furthermore, the effects described in this specification are merely examples and are not limiting, and other effects may also be present. The technical scope of the present invention is determined only by the matters specifying the invention in the claims that are reasonable from the above description.

1, 101 GaN substrate 1a, 2a Front surface 1b Back surface 2, 102 GaN layer 3, 103 Well region 3' (well region will be formed) planned region 4, 104 Source region 4' (source region will be formed) planned region 5 Gate insulating film 6 Gate electrode 7 Source electrode 8 Drain electrode 10 Channel region 21 Insulating films 21a, 22a Slanted surfaces 21M, 121 Masks 22, 23 Resist mask 23 Resist mask 30 JFET region 100 GaN semiconductor device D1 Surface D2 Bottom D3, D31 , D32, D33 Peak position P1 First end P2 Second end P3, P31, P32, P33 Peak position VL Virtual line

Claims (9)

a nitride semiconductor layer;
a first conductivity type well region provided in the nitride semiconductor layer;
a second conductivity type source region provided on the surface side of the well region;
a gate insulating film provided on the well region;
a gate electrode provided on the gate insulating film,
The well region is
a first end located on the source region side;
a second end located on the opposite side of the first end in the surface direction of the well region,
The first conductivity type impurity concentration at the surface of the well region is:
changes from the first end toward the second end, a first maximum value exists between the first end and the second end, and the first maximum value and the second having a first distribution in which there is a region between the end portion and the impurity concentration of the first conductivity type lower than the first maximum value ;
The impurity concentration of the first conductivity type in the depth direction of the well region is:
A nitride semiconductor device having a second distribution that changes from the surface of the well region toward the bottom of the well region and has a second maximum value between the surface and the bottom of the well region. The second distribution includes:
2. The nitride semiconductor device according to claim 1, wherein there is a region between the second maximum value and the bottom where the impurity concentration of the first conductivity type is lower than the second maximum value. A first peak position where the impurity concentration of the first conductivity type is maximum between the first end and the second end, and a first peak position where the impurity concentration of the first conductivity type is maximum between the surface and the bottom of the well region. 3. The nitride semiconductor device according to claim 1 , wherein there are the same number of second peak positions where the impurity concentration is maximum. The first conductivity type impurity is magnesium,
4. The magnesium concentration at the surface of the well region and the magnesium concentration in the depth direction of the well region are each 1×10 ¹⁶ cm ⁻³ or more and 1×10 ²⁰ cm ⁻³ or less , respectively. The nitride semiconductor device according to item 1 . The first conductivity type impurity is magnesium,
The magnesium concentration at the surface of the well region and the magnesium concentration in the depth direction of the well region are each 1×10 ¹⁷ cm ⁻³ or more and 1×10 ¹⁸ cm ⁻³ or less , respectively. The nitride semiconductor device according to item 1 . The nitride semiconductor layer is
a first nitride semiconductor layer of a second conductivity type;
a second nitride semiconductor layer of a second conductivity type provided on the first nitride semiconductor layer,
The second nitride semiconductor layer has a lower impurity concentration of the second conductivity type than the first nitride semiconductor layer,
6. The nitride semiconductor device according to claim 1, wherein the well region and the source region are provided in the second nitride semiconductor layer. further comprising a second conductivity type impurity region provided in the second nitride semiconductor layer and adjacent to the second end,
7. The impurity concentration of the second conductivity type is lower in the impurity region than in the first nitride semiconductor layer, and is lower in the second nitride semiconductor layer than in the impurity region. Nitride semiconductor device. forming a first conductivity type well region in the nitride semiconductor layer;
forming a two-conductivity type source region on the surface side of the well region;
forming a gate insulating film on the well region;
forming a gate electrode on the gate insulating film,
The step of forming the well region includes:
forming a mask on the nitride semiconductor layer having an inclined surface inclined with respect to a surface direction of the well region;
ion-implanting impurities of a first conductivity type into the nitride semiconductor layer on which the mask is formed from the mask side;
In the step of forming the mask,
arranging the inclined surface on a region in the nitride semiconductor layer where the well region is to be formed;
An end of the well region located on the source region side is a first end, and an end located on the opposite side of the first end in the surface direction of the well region is a second end. If the section is
In the step of ion-implanting the first conductivity type impurity,
Regarding the impurity concentration of the first conductivity type at the surface of the well region,
changes from the first end toward the second end, a first maximum value exists between the first end and the second end, and the first maximum value and the second A method for manufacturing a nitride semiconductor device , comprising forming a first distribution in which a region having an impurity concentration of the first conductivity type lower than the first maximum value exists between the end portion and the end portion . In the step of ion-implanting the first conductivity type impurity,
ion-implanting the first conductivity type impurity with a first implantation energy;
9. The method of manufacturing a nitride semiconductor device according to claim 8 , comprising the step of ion-implanting the first conductivity type impurity with a second implantation energy different from the first implantation energy.

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