JP7238303B2 - Gallium nitride semiconductor device and method for manufacturing gallium nitride semiconductor device - Google Patents

Description

The present invention relates to a gallium nitride semiconductor device and a method for manufacturing a gallium nitride semiconductor device.

Conventionally, it is known to partially remove an epitaxially formed P ⁻ -type gallium nitride (hereinafter referred to as GaN) layer to provide a gate trench portion (see, for example, Non-Patent Document 1). It is also known to partially remove a P ⁻ -type GaN layer to form a mesa portion of the GaN layer, and to form field plates on the sides and bottom of the mesa portion (see, for example, Non-Patent Documents 1). Patent Documents 1 and 2 describe partially ion-implanting magnesium (hereinafter referred to as Mg) into a GaN layer and then thermally diffusing the Mg to make the diffusion region P-type. Further, Patent Document 2 describes that by not providing a gate trench portion and a mesa portion in a GaN layer, concentration of an electric field on a corner portion is avoided, and a decrease in breakdown voltage is prevented. there is

JP 2007-258578 A Japanese Patent No. 6327379

Tohru Oka et al. ，”Ｖｅｒｔｉｃａｌ ＧａＮ－ｂａｓｅｄ ｔｒｅｎｃｈ ｍｅｔａｌ ｏｘｉｄｅ ｓｅｍｉｃｏｎｄｕｃｔｏｒ ｆｉｅｌｄ－ｅｆｆｅｃｔ ｔｒａｎｓｉｓｔｏｒｓ ｏｎ ａ ｆｒｅｅ－ｓｔａｎｄｉｎｇ ＧａＮ ｓｕｂｓｔｒａｔｅ ｗｉｔｈ ｂｌｏｃｋｉｎｇ ｖｏｌｔａｇｅ ｏｆ １．６ ｋＶ”，Ａｐｐｌｉｅｄ Ｐｈｙｓｉｃｓ Ｅｘｐｒｅｓｓ，ｐｕｂｌｉｓｈｅｄ ２８ Ｊａｎｕａｒｙ ２０１４，Ｖｏｌｕｍｅ ７，Ｎｕｍｂｅｒ ２，０２１００２

A gallium nitride semiconductor device capable of improving characteristics while suppressing a decrease in breakdown voltage is desired.

SUMMARY OF THE INVENTION It is an object of the present invention to provide a gallium nitride semiconductor device and a method for manufacturing a gallium nitride semiconductor device capable of improving characteristics while suppressing a decrease in breakdown voltage. and

To solve the above problems, a gallium nitride semiconductor device according to an aspect of the present invention provides a gallium nitride layer, a first conductivity type source region provided in the gallium nitride layer, a first conductivity type source region provided in the gallium nitride layer, and a first conductivity type source region provided in the gallium nitride layer. an impurity region of a second conductivity type adjacent to the source region in the direction and the second direction. The first direction is parallel to the surface of the gallium nitride layer. The second direction is a direction intersecting the first direction and the surface of the gallium nitride layer. In the second direction, the impurity region has a peak position where the concentration of impurities of the second conductivity type is highest. The depth from the surface of the gallium nitride layer to the peak position is 200 nm or more and 1500 nm or less. The concentration of the impurity of the second conductivity type at the peak position is 1×10 ¹⁷ cm ⁻³ or more and 1×10 ¹⁹ cm ⁻³ or less. The concentration of the impurity of the second conductivity type in the surface of the impurity region is 1×10 ¹⁶ cm ⁻³ or more and 3×10 ¹⁸ cm ^{−3 or} less.

A method for manufacturing a gallium nitride semiconductor device according to an aspect of the present invention includes a gallium nitride layer, a first conductivity type source region provided in the gallium nitride layer, a first conductivity type source region provided in the gallium nitride layer, and a first direction and a second direction. and an impurity region of the second conductivity type adjacent to the source region in the method of manufacturing a gallium nitride semiconductor device. A method for manufacturing a gallium nitride semiconductor device includes a step of ion-implanting an impurity of a second conductivity type into a gallium nitride layer, and performing a heat treatment on the gallium nitride layer into which the impurity of the second conductivity type has been implanted to obtain the second conductivity type. and forming an impurity region. In the step of ion-implanting the impurity of the second conductivity type, the implantation peak position of the impurity of the second conductivity type is at a depth of 200 nm or more and 1500 nm or less from the surface of the gallium nitride layer, and the implantation concentration at the implantation peak position is 1×10. The ion implantation conditions are set so that the concentration is ¹⁷ or more and 1×10 ¹⁹ cm ⁻³ or less.

According to the present invention, it is possible to provide a gallium nitride semiconductor device and a method for manufacturing a gallium nitride semiconductor device, which are capable of improving device characteristics while suppressing a decrease in breakdown voltage.

FIG. 1 is a plan view showing a configuration example of a gallium nitride semiconductor device according to an embodiment of the present invention. FIG. 2 is a cross-sectional view showing a configuration example of a vertical MOSFET according to an embodiment of the present invention. FIG. 3 is a cross-sectional view showing a configuration example of the edge termination region of the GaN semiconductor device according to the embodiment of the invention. 4A to 4D are cross-sectional views showing the manufacturing method of the vertical MOSFET according to the embodiment of the present invention in order of steps. 5A to 5C are cross-sectional views showing the manufacturing method of the vertical MOSFET according to the embodiment of the present invention in order of steps. 6A to 6C are cross-sectional views showing the manufacturing method of the vertical MOSFET according to the embodiment of the present invention in order of steps. 7A to 7C are cross-sectional views showing the manufacturing method of the vertical MOSFET according to the embodiment of the present invention in order of steps. 8A to 8D are cross-sectional views showing the manufacturing method of the vertical MOSFET according to the embodiment of the present invention in order of steps. 9A to 9D are cross-sectional views showing the manufacturing method of the vertical MOSFET according to the embodiment of the present invention in order of steps. FIG. 10 is a graph showing the Mg concentration distribution (before heat treatment) in the depth direction of the GaN layer. FIG. 11 is a graph showing the Mg concentration distribution (after heat treatment) in the depth direction of the GaN layer. FIG. 12 is a graph showing the relationship between the surface Mg concentration of the GaN layer and the threshold. FIG. 13 is a cross-sectional view showing the configuration of a vertical MOSFET according to a modification of the embodiment of the invention. FIG. 14 is a cross-sectional view showing a method of manufacturing a vertical MOSFET according to a modification of the embodiment of the invention. FIG. 15 is a graph schematically showing the Mg concentration distribution (before heat treatment and after heat treatment) in the depth direction of a GaN layer into which Mg is implanted in multiple stages.

Embodiments of the present invention are described below. In the following description of the drawings, the same or similar parts are denoted by the same or similar reference numerals. However, it should be noted that the drawings are schematic, and the relationship between thickness and planar dimensions, the ratio of the thickness of each device and each member, etc. are different from the actual ones. Therefore, specific thicknesses and dimensions should be determined with reference to the following description. In addition, it goes without saying that there are portions with different dimensional relationships and ratios between the drawings.

Also, in the following description, the positive direction of the Z-axis may be referred to as "up" and the negative direction of the Z-axis may be referred to as "down." "Upper" and "lower" do not necessarily mean perpendicular to the ground. That is, the "up" and "down" directions are not limited to the direction of gravity. "Upper" and "lower" are merely expedient expressions specifying relative positional relationships among regions, layers, films, substrates, etc., and do not limit the technical idea of the present invention. For example, if the paper surface is rotated 180 degrees, it goes without saying that "top" becomes "bottom" and "bottom" becomes "top".

Also, in the following description, a case where the first conductivity type is the N type and the second conductivity type is the P type will be exemplified. However, the conductivity types may be selected in the opposite relationship, so that the first conductivity type is P-type and the second conductivity type is N-type. Moreover, + or - attached to P or N means that the semiconductor region has a relatively high or low impurity concentration, respectively, compared to a semiconductor region not marked with + or -. However, even if the same P is attached to the semiconductor region, it does not mean that the impurity concentration of each semiconductor region is exactly the same.

(Configuration example of GaN semiconductor device)
FIG. 1 is a plan view showing a configuration example of a gallium nitride semiconductor device (hereinafter referred to as a GaN semiconductor device) according to an embodiment of the present invention. FIG. 1 is an XY plan view. For example, the first direction (the X-axis direction and the Y-axis direction) is a direction parallel to the first main surface 10a of the GaN substrate 10, which will be described later. The second direction (Z-axis direction) is a direction perpendicular to the first main surface 10 a and is the thickness direction of the GaN semiconductor device 100 . The X-axis direction, Y-axis direction and Z-axis direction are orthogonal to each other.

As shown in FIG. 1, GaN semiconductor device 100 has an active region 110 and an edge termination region 130 . Active area 110 has a gate pad 112 and a source pad 114 . The gate pad 112 and the source pad 114 are electrode pads electrically connected to a gate electrode 44 and a source electrode 54, respectively, which will be described later.

The edge termination region 130 surrounds the active region 110 in plan view from the Z-axis direction. Edge termination region 130 may have one or more of a guard ring structure, a field plate structure, and a JTE (Junction Termination Extension) structure. The edge termination region 130 may function to prevent electric field concentration in the active region 110 by extending the depletion layer generated in the active region 110 to the edge termination region 130 .

(Configuration example of vertical MOSFET)
FIG. 2 is a cross-sectional view showing a configuration example of a vertical MOSFET according to an embodiment of the present invention. FIG. 2 shows a cross section of the active region 110 shown in FIG. The GaN semiconductor device 100 includes a plurality of vertical MOSFETs (Metal Oxide Semiconductor Field Effect Transistors) 1 shown in FIG. In the GaN semiconductor device 100, vertical MOSFETs 1 are repeatedly provided in the Y-axis direction. In addition, in FIG. 2, the virtual line CL is shown in figure for convenience which demonstrates the structure of vertical MOSFET1. A virtual line CL is a straight line parallel to the Z-axis direction. A virtual line CL passes through the center of the unit structure shown in FIG. 2 in the Y-axis direction.

As shown in FIG. 2 , the vertical MOSFET 1 has a gallium nitride substrate (hereinafter referred to as a GaN substrate) 10 , a GaN layer 16 , a gate insulating film 42 , a gate electrode 44 , a source electrode 54 and a drain electrode 56 .

The GaN substrate 10 is a GaN single crystal substrate. The GaN substrate 10 is a first conductivity type (N type) substrate, for example, an N ⁺ type substrate. GaN substrate 10 has a first main surface 10a and a second main surface 10b opposite to first main surface 10a. For example, the GaN substrate 10 is a low-dislocation freestanding substrate with a dislocation density of less than 1×10 ⁷ cm ⁻² . Since the GaN substrate 10 is a low-dislocation free-standing substrate, the dislocation density of the GaN layer 16 formed on the GaN substrate 10 is also low.

Moreover, by using a low-dislocation substrate for the GaN substrate 10, even when a large-area power device is formed on the GaN substrate 10, leakage current in the power device can be reduced. As a result, the manufacturing apparatus can manufacture power devices with a high non-defective product rate. Further, in the heat treatment, it is possible to prevent the ion-implanted impurities from diffusing deeply along the dislocations.

GaN layer 16 is provided on first main surface 10 a of GaN substrate 10 . A GaN layer 16 is epitaxially formed on the GaN substrate 10 . The GaN layer 16 is an N-type layer, such as an N ⁻ -type layer. The N-type impurities contained in the GaN layer 16 may be one or more elements of Si (silicon), Ge (germanium), and O (oxygen). In the embodiment of the present invention, Si is used as an example of N-type impurities. The second conductivity type (P-type) impurity for the GaN layer 16 may be one or more elements of Mg (magnesium), Ca (calcium), Be (beryllium) and Zn (zinc). In the embodiment of the present invention, Mg is used as an example of a P-type impurity.

In vertical MOSFET 1, the semiconductor material is GaN, but the semiconductor material may contain one or more elements of aluminum (Al) and indium (In). The semiconductor material may be a mixed crystal semiconductor containing trace amounts of Al and In, ie, AlxInyGa1-xyN (0≤x<1, 0≤y<1). Note that GaN is the case where x=y=0 in AlxInyGa1-xyN.

The GaN layer 16 is provided with a drift region 22 , a base region 23 , a contact region 25 , a source region 26 and a buried region 28 . The base region 23, the contact region 25, the source region 26, and the embedded region 28 are regions formed by ion-implanting impurities to a predetermined depth from the surface 16a of the GaN layer 16 and heat-treating them.

The base region 23, contact region 25 and buried region 28 are P-type regions. The base region 23, the contact region 25, and the embedded region 28 contain, for example, Mg as a P-type impurity. The base region 23, the contact region 25, and the buried region 28 are formed by ion-implanting Mg into the GaN layer 16 and performing heat treatment to activate the Mg. The base region 23 is P-type or P ^- type, and the contact region 25 and buried region 28 are P ⁺ -type. The contact region 25 and the embedded region 28 have a higher P-type impurity concentration than the base region 23 .

The base region 23 and the embedded region 28 constitute the P-type impurity region 2 . In the P-type impurity region 2 , the side closer to the surface 16 a of the GaN layer 16 is the base region 23 , and the side farther from the surface 16 a of the GaN layer 16 is the embedded region 28 . The P-type impurity concentration continuously changes between the base region 23 and the buried region 28 .

Drift region 22 and source region 26 are N-type regions. The drift region 22 and the source region 26 contain, for example, Si as N-type impurities. The source region 26 is formed by ion-implanting Si into the GaN layer 16 and heat-treating it. Source region 26 is of the N ⁺ type. Also, the drift region 22 is an N-type or N ⁻ -type region. The drift region 22 has a lower N-type impurity concentration than the source region 26 . For example, in the manufacturing process of the vertical MOSFET 1, the drift region 22 is not ion-implanted with N-type impurities. The N-type impurity concentration of the drift region 22 is the same as the N-type impurity concentration of the GaN layer 16 .

As shown in FIG. 2, the upper portion of the source region 26 is exposed on the surface 16a of the GaN layer 16. As shown in FIG. The source region 26 contacts the base region 23 on its bottom and inner sides, and contacts the contact region 25 on its outer sides. The inner side of the source region 26 is the side closer to the imaginary line CL. The outer side of source region 26 is the side farther from imaginary line CL. In the unit structure shown in FIG. 2, the source region 26 has a first source region 26-1 and a second source region 26-2. The first source region 26-1 and the second source region 26-2 are arranged symmetrically with respect to the virtual line CL.

The embedded region 28 is located below the bottom of the source region 26 (that is, on the GaN substrate 10 side). Base region 23 is located between the bottom of source region 26 and the top of buried region 28 . Also, the inner side portion of the embedded region 28 is in contact with the drift region 22 . The inner side portion of the embedded region 28 is the side portion closer to the imaginary line CL. In the unit structure shown in FIG. 2, the embedded region 28 has a first embedded region 28-1 and a second embedded region 28-2. The first embedded region 28-1 and the second embedded region 28-2 are arranged line-symmetrically with respect to the virtual line CL.

Base region 23 is provided on embedded region 28 . An upper portion of base region 23 is exposed at surface 16 a of GaN layer 16 . Above the base region 23 is the channel region 231 of the vertical MOSFET 1 . Channel region 231 is in contact with gate insulating film 42 at surface 16a. A lower portion of the base region 23 is in contact with the embedded region 28 . Also, the inner side portion of the base region 23 is in contact with the drift region 22 . The inner side portion of the base region 23 is the side portion closer to the imaginary line CL. In the unit structure shown in FIG. 2, the base region 23 has a first base region 23-1 and a second base region 23-2. The first base region 23-1 and the second base region 23-2 are arranged symmetrically with respect to the virtual line CL.

A contact region 25 is provided on the buried region 28 . The upper portion of contact region 25 is exposed at surface 16 a of GaN layer 16 . The contact region 25 contacts the source region 26 and the base region 23 on the inner side and the buried region 28 on the bottom. The inner side portion of the contact region 25 is the side portion closer to the imaginary line CL. In the unit structure shown in FIG. 2, the contact region 25 has a first contact region 25-1 and a second contact region 25-2. The first contact region 25-1 and the second contact region 25-2 are arranged line-symmetrically with respect to the virtual line CL.
The base region 23, contact region 25, source region 26 and buried region 28 have a stripe shape extending in the X-axis direction.

An upper portion (hereinafter referred to as an upper region) 221 of the drift region 22 is exposed on the surface 16 a of the GaN layer 16 . Upper region 221 is in contact with gate insulating film 42 at surface 16a. A lower portion (hereinafter referred to as lower region) 222 of drift region 22 is in contact with first main surface 10 a of GaN substrate 10 . The upper region 221 is positioned between the first base region 23-1 and the second base region 23-2 and between the first buried region 28-1 and the second buried region 28-2, respectively.

The lower region 222 is positioned between the upper region 221 and the GaN substrate 10, between the first buried region 28-1 and the GaN substrate 10, and between the second buried region 28-2 and the GaN substrate 10, respectively. do. The lower region 222 may be provided continuously in the Y-axis direction between multiple vertical MOSFETs 1 (that is, multiple unit structures) repeated in the Y-axis direction.

Drift region 22 functions as a current path between channel region 231 and GaN substrate 10 . Contact region 25 has a function of reducing contact resistance with source electrode 54 . The contact region 25 also functions as a hole extraction path when the gate is turned off.

The embedded region 28 functions as a breakdown voltage structure. For example, when the buried region 28 is not provided in the GaN layer 16, the depletion layer formed by the PN junction between the base region 23 and the drift region 22 reaches the upper end of the base region 23, so that the breakdown voltage when the gate is turned off. may decline. In contrast, the vertical MOSFET 1 according to the embodiment of the present invention can prevent the depletion layer from reaching the upper end of the base region 23 by having the buried region 28 with a high P-type impurity concentration. In addition, since the vertical MOSFET 1 has the buried region 28 with a high P-type impurity concentration, the depletion layer formed by the PN junction between the buried region 28 and the drift region 22 can be expanded toward the lower region 222 side. . As a result, the vertical MOSFET 1 can improve the withstand voltage when the gate is turned off, compared to the case where the buried region 28 is not provided.

The gate insulating film 42 is, for example, a silicon oxide film (SiO ₂ film). A gate insulating film 42 is provided on the flat surface 16a. In embodiments of the present invention, a flat surface means a surface that is not intentionally roughened by etching intended to provide a gate trench or mesa structure. However, the flat surface is not limited to a completely flat surface, and may be a substantially flat surface. In embodiments of the present invention, the flat surface may have irregularities of the order of 10 nm, for example. The unevenness may be evaluated, for example, by the maximum height roughness Rz. The maximum height roughness Rz is the height Rp from the average line to the highest peak and the lowest valley in a graph in which the contour curve is extracted by the reference length L in the direction of the average line of the contour curve showing unevenness. , and the depth Rv.

In active region 110 , surface 16 a of GaN layer 16 includes the surface of contact region 25 , the surface of source region 26 , the surface of channel region 231 and the surface of upper region 221 . The surface of contact region 25 , the surface of source region 26 , the surface of channel region 231 , and the surface of upper region 221 constitute one plane parallel or substantially parallel to first main surface 10 a of GaN substrate 10 . In the active region 110, the surface 16a of the GaN layer 16 does not have stepped portions such as gate trench portions and mesa portions. Therefore, in the active region 110, the electric field is not concentrated on the corners of the bottom of the stepped portion. As a result, the GaN semiconductor device 100 can reduce the possibility that the withstand voltage is lowered due to electric field concentration at the corners.

The gate electrode 44 is provided above the channel region 231 with the gate insulating film 42 interposed therebetween. For example, the gate electrode 44 is continuously provided from above the channel region 231 to above the source region 26 via the gate insulating film 42 . The gate electrode 44 is of a planar type provided on the flat gate insulating film 42 . The gate electrode 44 is also formed flat by forming the gate electrode 44 on the flat gate insulating film 42 . The gate electrode 44 is made of a material different from that of the gate pad 112 . The gate electrode 44 is made of impurity-doped polysilicon, and the gate pad 112 is made of Al or Al--Si alloy.

A source electrode 54 is provided on the surface 16 a of the GaN layer 16 . Source electrode 54 is in contact with part of source region 26 and contact region 25 . The source electrode 54 may also be provided on the gate electrode 44 via an interlayer insulating film (not shown). The interlayer insulating film may cover the top and sides of the gate electrode 44 so that the gate electrode 44 and the source electrode 54 are not electrically connected.

The source electrode 54 is made of the same material as the source pad 114 . For example, the source electrode 54 made of Al or an Al—Si alloy also serves as the source pad 114 . The source electrode 54 may have a barrier metal layer between the surface 16a of the GaN layer 16 and the Al layer (or Al--Si layer). Titanium (Ti) may be used as the material for the barrier metal layer. That is, the source electrode 54 may be a stack of Ti layers and Al layers, or a stack of Ti layers and Al—Si alloy layers. The drain electrode 56 is provided on the second main surface 10b side of the GaN substrate 10 and is in contact with the second main surface 10b. The drain electrode 56 is also made of the same material as the source electrode 54 .

In FIG. 2, the gate, source and drain terminals are denoted by G, D and S, respectively. For example, when a potential higher than the threshold voltage is applied to the gate electrode 44 via the gate terminal G, an inversion layer is formed in the channel region 231 . When a predetermined high potential is applied to the drain electrode 56 and a low potential (for example, ground potential) is applied to the source electrode 54 in a state in which an inversion layer is formed in the channel region 231, the voltage from the drain terminal D to the source is applied. A current flows to the terminal S. Further, when a potential lower than the threshold voltage is applied to the gate electrode 44, no inversion layer is formed in the channel region 231 and the current is cut off. Thereby, the vertical MOSFET 1 can switch the current between the source terminal S and the drain terminal D. FIG.

By the way, in the Z-axis direction, the impurity region 2 has an Mg peak position 28P where the concentration of P-type impurities (for example, Mg) is the highest. A Mg peak position 28P exists in the embedded region 28 of the impurity region 2 . A depth D1 from the surface 16a of the GaN layer 16 to the Mg peak position 28P (hereinafter referred to as Mg peak depth) is 200 nm or more and 1500 nm or less, more preferably 300 nm or more and 1000 nm or less, and still more preferably 400 nm or more. 800 nm or less. Further, the concentration of Mg at the Mg peak position 28P (hereinafter referred to as Mg peak concentration) is 1×10 ¹⁷ cm ⁻³ or more and 1×10 ¹⁹ cm ⁻³ or less, more preferably 1×10 ¹⁸ cm ⁻³ or more. It is 1×10 ¹⁹ cm ⁻³ or less. Thereby, the vertical MOSFET 1 can improve the breakdown voltage when the gate is turned off.

Further, the concentration of Mg on the surface of the base region 23 (hereinafter referred to as surface Mg concentration) is 1×10 ¹⁶ cm ⁻³ or more and 3×10 ¹⁸ cm ⁻³ or less, more preferably 1×10 ¹⁷ cm ⁻³ . It is more than 1×10 ¹⁸ cm ⁻³ or less. As a result, the vertical MOSFET 1 can keep the threshold value and the mobility within appropriate ranges while suppressing a decrease in breakdown voltage when the gate is turned off, and can improve its characteristics. In addition, in the embodiment of the present invention, the surface Mg concentration means, for example, the Mg concentration in the range from the outermost surface of the base region 23 to a depth of 100 nm.

(Configuration example of edge termination region)
3A and 3B are cross-sectional views showing configuration examples of the edge termination region of the GaN semiconductor device according to the embodiment of the present invention. FIGS. 3(a) and 3(b) show two examples of cross-sections taken along line III-III' in FIG. Specifically, FIG. 3( a ) shows the case where the edge termination region 130 has a guard ring structure 74 . FIG. 3(b) shows the case where the edge termination region 130 has a JTE (Junction Termination Extension) structure 78. FIG.
As shown in FIGS. 3A and 3B, the GaN substrate 10, the GaN layer 16 and the drain electrode 56 are commonly provided in the active region 110 and the edge termination region 130. FIG. However, as shown in FIGS. 3A and 3B, the structure inside the GaN layer 16 in the edge termination region 130 is different from the structure inside the GaN layer 16 in the active region 110 . The edge termination region 130 also comprises an electrode 58 provided on the GaN layer 16 and a protective film 70 provided on the GaN layer 16 .

GaN layer 16 in edge termination region 130 includes drift region 22 , base region 23 , first doped region 35 , second doped region 36 and buried region 28 . Base region 23, first doped region 35, second doped region 36 and buried region 28 are P-type regions. The base region 23, the first doped region 35, the second doped region 36 and the buried region 28 contain Mg as a P-type impurity. The base region 23, the first doped region 35, the second doped region 36, and the buried region 28 are formed by ion-implanting Mg into the GaN layer 16 and heat-treating. Buried region 28 is of P ⁺ type. Base region 23, first doped region 35 and second doped region 36 are of P-type or P ^- type.

The base region 23 is provided on the embedded region 28 . In the XY plane, first doped region 35 is located between second doped region 36 and base region 23 . Base region 23 is located closer to active region 110 and second doped region 36 is located farther from active region 110 .

As shown in FIG. 3(a), edge termination region 130, for example, includes a plurality of guard ring structures 74 spaced apart from one another. The guard ring structure 74 is a structure in which an active region is surrounded by a plurality of narrow p-type layers in a ring shape. Alternatively, the edge termination region 130 may have one guard ring structure 74 rather than multiple. The guard ring structure 74 may be composed of the base region 23 or the buried region 28, or may be of other configurations. For example, the guard ring structure 74 may be composed of an impurity region having a different concentration or implantation peak depth from the base region 23 and the buried region 28 .

Since the GaN semiconductor device 100 has the guard ring structure 74 , the depletion layer in the gate-off state tends to spread to the edge of the GaN layer 16 on the outer peripheral side. As a result, the GaN semiconductor device 100 can improve the breakdown voltage of the vertical MOSFET 1 as compared with the case without the guard ring structure 74 .

The edge termination region 130 may have a JTE structure 78, as shown in FIG. 3(b). The JTE structure 78 may be composed of one impurity region, or may be composed of two or more impurity regions having different concentrations. In either case, a suitable configuration may be chosen.
For example, JTE structure 78 is comprised of first doped region 35 and second doped region 36 . The P-type impurity concentration in the second doped region 36 is lower than the P-type impurity concentration in the first doped region 35 . By making the P-type impurity concentration of the second doped region 36 relatively lower than that of the first doped region 35 , the depletion layer in the gate-off state easily spreads to the edge of the GaN layer 16 on the outer peripheral side. As a result, the GaN semiconductor device 100 can improve the withstand voltage of the vertical MOSFET 1 compared to the case without the JTE structure 78 .
Edge termination region 130 may also have both guard ring structures 74 and JTE structures 78 . Even when both the guard ring structure 74 and the JTE structure 78 are combined, the GaN semiconductor device 100 can improve the withstand voltage of the vertical MOSFET 1 .

Also, in edge termination region 130 , surface 16 a of GaN layer 16 includes the surface of base region 23 , the surface of first doped region 35 , and the surface of second doped region 36 . In an embodiment of the present invention, the surface of the base region 23, the surface of the first doped region 35, and the surface of the second doped region 36 are one plane parallel or substantially parallel to the first main surface 10a of the GaN substrate 10. configure. The GaN layer 16 in the edge termination region 130 has no steps such as gate trenches or mesas. Also, the thickness of the GaN layer 16 is the same in the active region 110 and the edge termination region 130 . At the interface between the active region 110 and the edge termination region 130, the GaN layer 16 does not have a stepped portion such as a gate trench portion or a mesa portion. Therefore, the electric field does not concentrate on the bottom corners of the steps in the edge termination region 130 and the boundary between the active region 110 and the edge termination region 130 . The GaN semiconductor device 100 can reduce the possibility that the withstand voltage is lowered due to electric field concentration at the corners.

The protective film 70 is a passivation film, such as a SiO ₂ film. Protective film 70 covers surface 16 a of GaN layer 16 at edge termination region 130 . This can prevent impurities from entering the inside from the surface 16 a of the GaN layer 16 .

(Manufacturing method of vertical MOSFET)
Next, a method for manufacturing the vertical MOSFET 1 according to the embodiment of the present invention will be described. 4 to 9 are cross-sectional views showing the manufacturing method of the vertical MOSFET according to the embodiment of the present invention in order of steps. The vertical MOSFET 1 is manufactured by various manufacturing apparatuses such as a film forming apparatus, an exposure apparatus, and an etching apparatus.

As shown in FIG. 4 , the manufacturing equipment forms a GaN layer 16 on the GaN substrate 10 . For example, the manufacturing apparatus epitaxially forms the N-type GaN layer 16 on the N ⁺ -type GaN substrate 10 by metal-organic growth (MOCVD), halide vapor phase epitaxy (HVPE), or the like. The epitaxially formed GaN layer 16 may have Si as an N-type impurity. The concentration of Si in the GaN layer 16 is, for example, 1×10 ¹⁵ cm ⁻³ or more and 5×10 ¹⁶ cm ⁻³ or less. Also, the thickness of the GaN layer 16 (that is, the distance from the first main surface 10a of the GaN substrate 10 to the surface 16a of the GaN layer 16) may be changed according to the desired breakdown voltage, and is, for example, 1 μm or more and 50 μm or less. be.

Next, in the GaN layer 16, a region (hereinafter referred to as a base forming region) 23' in which the base region 23 (see FIG. 2) is formed and a region (see FIG. 2) in which the embedded region 28 (see FIG. 2) is formed. Mg is ion-implanted as an N-type impurity into a buried formation region 28'. For example, the manufacturing equipment forms a mask M1 on the GaN layer 16 . Mask M1 is a SiO ₂ film or photoresist that is selectively removable with respect to GaN layer 16 . In the active region 110 (see FIG. 1), the mask M1 has an opening above the base formation region 23' and the embedding formation region 28', and has a shape that covers the other regions above. The manufacturing apparatus implants Mg ions into the GaN layer 16 on which the mask M1 is formed.

In the process of ion-implanting Mg into the base formation region 23' and the embedded formation region 28' (hereinafter referred to as the Mg implantation process), the depth from the surface 16a of the GaN layer 16 to the injection peak position 28P' (hereinafter referred to as the injection peak depth c) The injection energy (acceleration voltage) is set such that D1′ is 200 nm or more and 1500 nm or less, more preferably 300 nm or more and 1000 nm or less, and still more preferably 400 nm or more and 800 nm or less.
In the Mg injection step, the concentration of Mg at the injection peak position 28P′ (hereinafter referred to as injection peak concentration) is 1×10 ¹⁷ or more and 1×10 ¹⁹ cm ⁻³ or less, more preferably 1×10 ¹⁸ cm ^{−3 .} The dose amount of Mg is set to be ³ or more and 1×10 ¹⁹ cm ⁻³ or less.

In the Mg implantation process, in order to achieve the above-described implantation peak depth D1′ and implantation peak concentration, the manufacturing apparatus performs single-step implantation of Mg at an acceleration voltage of 700 KeV and a dose of 4.2×10 ¹⁴ cm ⁻² , for example. are implanted into the GaN layer 16 . After the ion implantation, the manufacturing equipment removes the mask M1 from above the GaN layer 16 . The one-step injection means that the acceleration voltage is one condition.

Next, as shown in FIG. 5, the manufacturing apparatus forms an insulating film 31 on the GaN layer 16. Next, as shown in FIG. For example, the insulating film 31 is a _SiO2 film. The manufacturing apparatus forms the insulating film 31 by chemical vapor deposition (CVD). Next, in the GaN layer 16, the manufacturing apparatus implants Si ions as an N-type impurity into a region 26' where a source region is to be formed (hereinafter referred to as a source forming region). For example, the manufacturing apparatus forms a mask M2 on the GaN layer 16. FIG. The mask M2 is a _SiO2 film or photoresist. In the active region 110, the mask M2 has a shape that opens above the source formation region 26' and covers above other regions. The manufacturing apparatus implants Si ions into the GaN layer 16 on which the mask M2 is formed. After the ion implantation, the manufacturing equipment removes the mask M2 from above the GaN layer 16 .

Next, as shown in FIG. 6, in the GaN layer 16, the manufacturing apparatus ion-implants Mg as a P-type impurity into a region 25' where a contact region is to be formed (hereinafter referred to as a contact formation region). For example, the manufacturing equipment forms a mask M3 on the GaN layer 16 . The mask M3 is a _SiO2 film or photoresist. In the active region 110, the mask M3 has a shape that opens above the contact formation region 25' and covers above other regions. The manufacturing apparatus implants Mg ions into the GaN layer 16 on which the mask M3 is formed. After the ion implantation, the manufacturing equipment removes the mask M3 from above the GaN layer 16 .

Next, as shown in FIG. 7 , the manufacturing apparatus forms a protective film 33 on the insulating film 31 . The protective film 33 has a function of preventing nitrogen atoms from being released from the GaN layer 16 during heat treatment. Nitrogen vacancies are formed where nitrogen atoms are released from the GaN layer 16 . Nitrogen vacancies can act as donor-type defects, thus inhibiting the development of P-type properties. In order to prevent this, the manufacturing apparatus provides a protective film 33 on the GaN layer 16 with an insulating film 31 interposed therebetween.

The protective film 33 has high heat resistance, has good adhesion to the insulating film 31 , does not diffuse impurities from the protective film 33 to the GaN layer 16 side, and can be selectively removed from the GaN layer 16 . is preferably High heat resistance means that the protective film 33 does not substantially decompose to such an extent that pits (through openings) are not formed in the protective film 33 even when heat-treated at a temperature of 800° C. to 2000° C., for example. means.
The protective film 33 is an aluminum nitride (AlN) film, a _SiO2 film or a silicon nitride (SiN) film. Note that the protective film 33 may be a laminated film in which another film is laminated on the AlN film. Other films are exemplified by one or more of _SiO2 films, SiN films and GaN films.

Next, the manufacturing apparatus heat-treats the laminate including the GaN substrate 10, the GaN layer 16, the insulating film 31, and the protective film 33 at a maximum temperature of 800°C or higher and 2000°C or lower. This heat treatment is, for example, rapid heat treatment. This heat treatment activates the Mg and Si introduced into the GaN layer 16 . As a result, a P-type or P ⁻ -type base region 23, a P ⁺ -type contact region 25, an N ⁺ -type source region 26, and a P ⁺ -type buried region 28 are formed in the GaN layer 16. Along with this, a drift region 22 is defined. In addition, this heat treatment can recover defects caused by ion implantation in the GaN layer 16 to some extent. After the heat treatment, the manufacturing equipment removes the protective film 33 and the insulating film 31 from above the GaN layer 16 .

Next, as shown in FIG. 8 , the manufacturing equipment forms a gate insulating film 42 on the GaN layer 16 . For example, the manufacturing apparatus forms an insulating film by a CVD method, and then shapes the insulating film into a predetermined shape using photolithography and etching techniques. Thereby, the manufacturing apparatus forms the gate insulating film 42 . The gate insulating film 42 is a SiO ₂ film with a thickness of 100 nm.
Next, as shown in FIG. 9, the manufacturing equipment forms a gate electrode 44, a source electrode 54, and a drain electrode 56. Next, as shown in FIG. Next, the manufacturing equipment forms an interlayer insulating film (see FIG. 1) on the gate electrode 44 . The interlayer insulating film is, for example, a _SiO2 film. Next, the manufacturing equipment forms a gate pad 112 electrically connected to the gate electrode 44 and a source pad 114 electrically connected to the source electrode 54 . Thus, the vertical MOSFET 1 is completed.

(Experimental result)
Experimental results are shown for the distribution of Mg concentration in the depth direction of the GaN layer. FIG. 10 is a graph showing the Mg concentration distribution (before heat treatment) in the depth direction of the GaN layer. FIG. 11 is a graph showing the Mg concentration distribution (after heat treatment) in the depth direction of the GaN layer. The horizontal axes in FIGS. 10 and 11 indicate the depth [nm] from the surface of the GaN layer. The vertical axis in FIGS. 10 and 11 indicates the Mg concentration [cm ⁻³ ] in the GaN layer.

As shown in FIG. 10, the inventor performed the Mg implantation process under three different conditions (A), (B), and (C), respectively, and measured the Mg concentration in the depth direction of the GaN layer by SIMS (Secondary Ion Mass Spectrometry; secondary ion mass spectrometry). Condition (A) is an acceleration voltage of 700 keV (single-step implantation) and a Mg dose of 4.2×10 ¹⁴ cm ⁻² .
In the GaN layer of condition (A), the Mg injection peak depth was 650 nm and the Mg injection peak concentration was 1×10 ¹⁹ cm ⁻³ .
Condition (B) has an acceleration voltage of 700 keV (single-step implantation) and a Mg dose of 1.3×10 ¹⁴ cm ⁻² . In the GaN layer of condition (B), the Mg injection peak depth was 600 nm and the Mg injection peak concentration was 3×10 ¹⁸ cm ⁻³ .
Condition (C) is an acceleration voltage of 700 keV (single-step implantation) and a Mg dose of (4.2×10 ¹³ ) cm ⁻² . In the GaN layer of condition (C), the Mg injection peak depth was 600 nm and the Mg injection peak concentration was 1×10 ¹⁸ cm ⁻³ .

Next, the inventor performed a heat treatment for activating Mg on each GaN layer implanted with Mg under the conditions (A), (B), and (C). The heat treatment conditions are 1300° C. and 5 minutes. Then, as shown in FIG. 11, the inventor measured the Mg concentration in the depth direction of the GaN layer after the heat treatment by SIMS.
In the GaN layer of condition (A), the Mg peak depth after heat treatment was 700 nm, the Mg peak concentration was 7.5×10 ¹⁸ cm ⁻³ , and the surface Mg concentration was 3×10 ¹⁸ cm ⁻³ .
In the GaN layer of condition (B), the Mg peak depth after heat treatment was 450 nm, the Mg peak concentration was 3×10 ¹⁸ cm ⁻³ , and the surface Mg concentration was 8×10 ¹⁶ cm ⁻³ .
In the GaN layer of condition (C), the Mg peak depth after heat treatment was 600 nm, the Mg peak concentration was 1×10 ¹⁸ cm ⁻³ , and the surface Mg concentration was 3×10 ¹⁶ cm ⁻³ .

As can be seen by comparing FIG. 10 and FIG. 11, in the GaN layer of condition (A), Mg tends to diffuse to the surface side of the GaN layer due to the above heat treatment. That is, it was found that when the injection peak concentration approaches 1×10 ¹⁹ cm ⁻³ in the Mg injection step, Mg diffuses to the surface side of the GaN layer due to the above heat treatment, and the surface Mg concentration tends to increase. Further, in each of the GaN layers of the conditions (B) and (C), even if the above heat treatment is performed, almost no diffusion of Mg to the surface side of the GaN layer is observed, and the surface Mg concentration hardly changes. Do you get it. From this result, when the injection peak depth is around 500 nm in the Mg injection step, when the injection peak concentration exceeds 1×10 ¹⁹ cm ⁻³ , Mg diffuses significantly toward the surface side of the GaN layer during the above heat treatment. As a result, it is considered that the increase in the surface Mg concentration becomes remarkable.

Here, the higher the surface Mg concentration, the higher the threshold value of the vertical MOSFET. A threshold value of, for example, 3 V or higher is required to operate the vertical MOSFET normally off, but the higher the threshold value, the lower the mobility. There is a trade-off relationship between threshold and mobility. A decrease in mobility is not preferable in terms of vertical MOSFET characteristics.

FIG. 12 is a graph showing the relationship between the surface Mg concentration of the GaN layer and the threshold. FIG. 12 shows the results of an experiment conducted by the inventor. The horizontal axis of FIG. 12 indicates the surface Mg concentration [cm ⁻³ ]. The vertical axis of FIG. 12 indicates the threshold value Vth [V] of the vertical MOSFET. As shown in FIG. 12, the higher the surface Mg concentration, the higher the threshold Vth. Therefore, it is necessary to control the surface Mg concentration in order to set the threshold value Vth to a desired value. For example, it is desirable to set the Vth of the vertical MOSFET to 3 V or more and 10 V or less in relation to mobility. It has been found that the surface Mg concentration must be 1×10 ¹⁶ cm ⁻³ or more and 3×10 ¹⁸ cm ^{−3 or} less in order to achieve this. It was also found that the more preferable range P1 for the surface Mg concentration is 1×10 ¹⁷ cm ⁻³ or more and 1×10 ¹⁸ cm ^{−3 or} less.

As described above, the GaN semiconductor device 100 according to the embodiment of the present invention includes the GaN layer 16, the N-type source region 26 provided in the GaN layer 16, the surface of the GaN layer 16 provided in the GaN layer 16, and the a P-type impurity region 2 adjacent to the source region 26 in a first direction (X-axis direction and Y-axis direction) parallel to the surface 16a and a second direction (Z-axis direction) intersecting with the surface 16a. In the second direction, impurity region 2 has Mg peak position 28P where the concentration of P-type impurities (for example, Mg) is the highest.

For example, the impurity region 2 has a base region 23 adjacent to the source region 26 in the first direction and the second direction, and a buried region 28 located farther from the surface 16a of the GaN layer 16 than the base region 23. . The embedded region 28 has a higher Mg concentration than the base region 23 . Mg peak position 28P exists in embedded region 28 .

A depth (Mg peak depth) D1 from the surface 16a of the GaN layer 16 to the Mg peak position 28P is 200 nm or more and 1500 nm or less, more preferably 300 nm or more and 1000 nm or less, and still more preferably 400 nm or more and 800 nm or less. is. The Mg concentration (Mg peak concentration) at the Mg peak position 28P is 1×10 ¹⁷ cm ⁻³ or more and 1×10 ¹⁹ cm ⁻³ or less, more preferably 1×10 ¹⁸ cm ⁻³ or more and 1×10 ¹⁹ cm ⁻³ or less. The Mg concentration (surface Mg concentration) at surface 16a of impurity region 2 is 1×10 ¹⁶ cm ⁻³ or more and 3×10 ¹⁸ cm ^{−3 or} less.

With such a configuration, the GaN semiconductor device 100 can set the threshold value to a value suitable for normally-off operation without excessively reducing the mobility of the vertical MOSFET 1 . Thereby, the GaN semiconductor device 100 can improve the characteristics of the vertical MOSFET. In addition, there is a Mg peak position 28P in the embedded region 28 existing at a deep position when viewed from the surface 16a of the GaN layer 16. FIG. As a result, the depletion layer formed between the P-type buried region 28 and the N-type GaN layer 16 (for example, the drift region 22 ) spreads toward the side closer to the GaN substrate 10 . Thereby, the GaN semiconductor device 100 can improve the breakdown voltage when the vertical MOSFET 1 is gate-off.

In addition, the method of manufacturing the GaN semiconductor device 100 according to the embodiment of the present invention includes a step of ion-implanting Mg into the GaN layer 16 (Mg implantation step), and performing a heat treatment on the Mg-implanted GaN layer 16 to remove impurities. and forming region 2 . In the Mg injection step, the Mg injection peak position is 200 nm or more and 1500 nm or less, more preferably 300 nm or more and 1000 nm or less, still more preferably 400 nm or more and 800 nm or less from the surface 16a of the GaN layer 16, The concentration of Mg at the injection peak position (implantation peak concentration) is 1×10 ¹⁷ cm ⁻³ or more and 1×10 ¹⁹ cm ⁻³ or less, more preferably 1×10 ¹⁸ cm ⁻³ or more and 1×10 ¹⁹ cm −3 or more ^. The conditions for ion implantation are set so that the number is ³ or less.

According to this, in the heat treatment for activating Mg, diffusion of Mg to the surface 16a side of the GaN layer 16 is suppressed. Therefore, the Mg peak depth D1 is 200 nm or more and 1500 nm or less, more preferably 300 nm or more and 1000 nm or less, still more preferably 400 nm or more and 800 nm or less, and the Mg peak concentration is 1×10 ¹⁷ cm ⁻³ or more. ×10 ¹⁹ cm ⁻³ or less, more preferably 1×10 ¹⁸ cm ⁻³ or more and 1×10 ¹⁹ cm ⁻³ or less, and a surface Mg concentration of 1×10 ¹⁶ cm ⁻³ or more and 3×10 ¹⁸ cm A vertical MOSFET 1 can be manufactured that is ^-3 or less.

(Modification 1)
In embodiments of the present invention, drift region 22 may be doped to increase the concentration of N-type impurities.

FIG. 13 is a cross-sectional view showing the configuration of a vertical MOSFET according to a modification of the embodiment of the invention. As shown in FIG. 13, a vertical MOSFET 1A according to a modification of the embodiment includes an N ^- type doped region cd provided in an N − -type drift region 22. As shown in FIG. The doped region cd is a region doped with N-type impurities (eg, Si). In the drift region 22, regions other than the doped regions cd are undoped regions ucd. The doped region cd has a higher concentration of N-type impurities (eg, Si) than the undoped region ucd.

Also, the doped region cd is closer to the surface 16a of the GaN layer 16 than the undoped region ucd. For example, the doped region cd is provided continuously over the entire upper region 221 and the end of the lower region 222 on the side contacting the upper region 221 . According to this, in the drift region 22, the N-type impurity concentration in the region adjacent to the channel region 231 can be increased. As a result, the on-resistance of the vertical MOSFET 1 can be reduced while suppressing a decrease in breakdown voltage.

FIG. 14 is a cross-sectional view showing a method of manufacturing a vertical MOSFET according to a modification of the embodiment of the invention. FIG. 14 shows the steps for forming the doped region cd. As shown in FIG. 14, in the GaN layer 16, the manufacturing apparatus ion-implants an N-type impurity into a region cd' where the doped region cd is to be formed (hereinafter referred to as a dope forming region). For example, the manufacturing equipment forms a mask M4 on the GaN layer 16. FIG. The mask M4 is a _SiO2 film or photoresist. In the active region 110 (see FIG. 1), the mask M4 has an opening above the doping formation region cd' and a shape covering the other regions above. The manufacturing apparatus implants Si ions into the GaN layer 16 on which the mask M4 is formed. After the ion implantation, the manufacturing equipment removes the mask M4 from above the GaN layer 16 .

Next, the manufacturing equipment heat-treats the GaN layer 16 . As a result, the Si ion-implanted into the dope formation region cd' is activated, and an N-type dope region cd is formed in the GaN layer 16 . This heat treatment is performed in combination with the heat treatment for forming the base region 23, the contact region 25, the source region 26 and the buried region 28 (for activating Mg).

(Modification 2)
In the above embodiments, the Mg implantation step was described as a one-step implantation. However, embodiments of the invention are not so limited. The Mg injection step may be a multistage injection in which the acceleration voltage is switched midway. In the multistage implantation, Mg is implanted to different depths into the GaN layer by dividing the acceleration voltage into several stages. Even with such a method, the Mg peak depth D1 after heat treatment (see, for example, FIG. 2) is 200 nm or more and 1500 nm or less, more preferably 300 nm or more and 1000 nm or less, and still more preferably 400 nm or more and 800 nm. can be: Further, the Mg concentration (Mg peak concentration) at the Mg peak position 28P (see, for example, FIG. 2) after the heat treatment is set to 1×10 ¹⁷ cm ⁻³ or more and 1×10 ¹⁹ cm ⁻³ or less, more preferably 1× It can be 10 ¹⁸ cm ⁻³ or more and 1×10 ¹⁹ cm ⁻³ or less. Further, the surface Mg concentration after the heat treatment is 1×10 ¹⁶ cm ⁻³ or more and 3×10 ¹⁸ cm ⁻³ or less, more preferably 1×10 ¹⁷ cm ⁻³ or more and 1×10 ¹⁸ cm ⁻³ or less. be able to.

FIG. 15 is a graph schematically showing the Mg concentration distribution (before heat treatment and after heat treatment) in the depth direction of a GaN layer into which Mg is implanted in multiple stages. The horizontal axis of FIG. 15 indicates the depth [nm] from the surface of the GaN layer. The vertical axis in FIG. 15 indicates the Mg concentration [cm ⁻³ ] in the GaN layer. D1 in FIG. 15 indicates the Mg concentration before heat treatment. D2 in FIG. 15 indicates the Mg concentration after heat treatment.
When the Mg injection step is performed by multi-stage injection, as shown in D1 in FIG. , the acceleration voltage is preferably set in multiple stages.

According to this, as shown in D2 of FIG. 15, in the vicinity of the surface of the GaN layer, the surface Mg concentration after the heat treatment can be made high and the distribution of the Mg concentration after the heat treatment can be made flat. As a result, variations in threshold values can be reduced among a plurality of vertical MOSFETs.
Further, even when the Mg implantation process is performed by multi-stage implantation, if the injection peak depth of Mg and the injection peak concentration of Mg are set in the same manner as in the case of single-stage implantation, the diffusion of Mg to the surface side of the GaN layer can be suppressed. be able to.

(Modification 3)
In the above embodiment, epitaxial formation of the GaN layer 16 on the GaN substrate 10 has been described. Then, formation of the drift region 22, the base region 23, the contact region 25, the source region 26 and the buried region 28 in the GaN layer 16 has been described. However, the formation of GaN layer 16 is not essential in embodiments of the present invention. In embodiments of the present invention, drift region 22 , base region 23 , contact region 25 , source region 26 and buried region 28 may be formed in GaN substrate 10 instead of GaN layer 16 . In this case, the GaN substrate 10 is an example of the "gallium nitride layer" of the present invention.

(Other embodiments)
As described above, the present invention has been described through embodiments and variations, but the statements and drawings forming part of this disclosure should not be understood to limit the present invention. Various alternative embodiments and modifications will become apparent to those skilled in the art from this disclosure.
For example, the gate insulating film 42 is not limited to the _SiO2 film, and may be another insulating film. A silicon oxynitride (SiON) film, a strontium oxide (SrO) film, a silicon nitride (Si ₃ N ₄ ) film, and an aluminum oxide (Al ₂ O ₃ ) film can also be used for the gate insulating film 42 . A composite film or the like in which several single-layer insulating films are laminated can also be used for the gate insulating film 42 . A vertical MOSFET using an insulating film other than the SiO ₂ film as the gate insulating film 42 may be called a vertical MISFET. MISFET means a more generic insulated gate transistor that includes MOSFET.

Moreover, as an example of the manufacturing method, in the Mg implantation step of FIG. This insulating film may be the insulating film 31 shown in FIG. Even with such a method, the vertical MOSFET 1 can be manufactured.

1, 1A Vertical MOSFET
2 impurity region 10 GaN substrate 10a first main surface 10b second main surface 10V or more 16 GaN layer 16a surface 22 drift region 23 base region 23' base formation region 25 contact region 25' contact formation region 26 source region 26' source formation region 28 buried region 28' buried forming region 28P peak position 28P' injection peak position 31 insulating film 33 protective film 35 first doped region 36 second doped region 42 gate insulating film 44 gate electrode 54 source electrode 56 drain electrode 58 electrode 70 protective film 74 guard ring structure 78 JTE structure 100 GaN semiconductor device 110 active region 112 gate pad 114 source pad 130 edge termination region 221 upper region 222 lower region 231 channel region

Claims (9)

a gallium nitride layer;
a first conductivity type source region provided in the gallium nitride layer;
a second conductivity type impurity region provided in the gallium nitride layer and adjacent to the source region in a first direction parallel to the surface of the gallium nitride layer and in a second direction crossing the surface;
In the second direction, the impurity region has a peak position where the impurity concentration of the second conductivity type is highest,
The depth from the surface of the gallium nitride layer to the peak position is 200 nm or more and 1500 nm or less,
the concentration of the impurity of the second conductivity type at the peak position is 1×10 ¹⁷ cm ⁻³ or more and 1×10 ¹⁹ cm ^{−3 or} less;
a concentration of the impurity of the second conductivity type in the surface of the impurity region is 1×10 ¹⁶ cm ⁻³ or more and 3×10 ¹⁸ cm ^{−3 or} less ;
a first conductivity type drift region provided in the gallium nitride layer and adjacent to the impurity region;
the drift region has a lower impurity concentration of the first conductivity type than the source region;
The drift region is
a doped region;
an undoped region adjacent to the doped region;
the doped regions are closer to the surface of the gallium nitride layer than the undoped regions;
the doped region has a higher impurity concentration of the first conductivity type than the undoped region ;
The doped region is
a first region sandwiched from both sides by the impurity regions;
a second region located farther from the surface of the gallium nitride layer than the lower end of the impurity region;
The gallium nitride semiconductor device , wherein the second region is wider than the first region . 2. The gallium nitride semiconductor device according to claim 1 , wherein said doped region contains at least one of silicon, oxygen and germanium as said first conductivity type impurity. 3. The gallium nitride semiconductor device according to claim 1, wherein said impurity region contains at least one of magnesium and beryllium as said second conductivity type impurity. The impurity region is
a base region adjacent to the source region in the first direction and the second direction;
a buried region located farther from the surface of the gallium nitride layer than the base region;
the embedded region has a higher concentration of the second conductivity type impurity than the base region;
4. The gallium nitride semiconductor device according to claim 1, wherein said peak position exists in said buried region. a gate insulating film provided on the impurity region;
a gate electrode provided on the gate insulating film;
a source electrode provided on the source region;
5. The gallium nitride semiconductor device according to any one of claims 1 to 4 , further comprising a drain electrode provided on the back surface side opposite to the surface of said gallium nitride layer. 6. The gallium nitride semiconductor device according to claim 5 , wherein said gate insulating film is a silicon oxide film. 7. The gallium nitride semiconductor device according to any one of claims 1 to 6 , further comprising a gallium nitride single crystal substrate adjacent to the back surface opposite to the surface of said gallium nitride layer. a gallium nitride layer;
a first conductivity type source region provided in the gallium nitride layer;
an impurity region of a second conductivity type provided in the gallium nitride layer and adjacent to the source region in a first direction parallel to the surface of the gallium nitride layer and in a second direction crossing the surface;
a first conductivity type drift region provided in the gallium nitride layer and adjacent to the impurity region;
the drift region has a lower impurity concentration of the first conductivity type than the source region;
The drift region is
a doped region;
an undoped region adjacent to the doped region;
the doped regions are closer to the surface of the gallium nitride layer than the undoped regions;
the doped region has a higher impurity concentration of the first conductivity type than the undoped region;
The doped region is
a first region sandwiched from both sides by the impurity regions;
a second region located farther from the surface of the gallium nitride layer than the lower end of the impurity region;
The method for manufacturing a gallium nitride semiconductor device , wherein the second region is wider than the first region ,
ion-implanting impurities of a second conductivity type into the gallium nitride layer;
heat-treating the gallium nitride layer into which the impurity of the second conductivity type is implanted to form the impurity region;
In the step of implanting ions,
the injection peak position of the impurity of the second conductivity type is at a depth of 200 nm or more and 1500 nm or less from the surface of the gallium nitride layer;
so that the concentration of the impurity of the second conductivity type at the injection peak position is 1×10 ¹⁷ or more and 1×10 ¹⁹ cm ⁻³ or less,
A method of manufacturing a gallium nitride semiconductor device, wherein the ion implantation conditions are set. 9. The method of manufacturing a gallium nitride semiconductor device according to claim 8 , wherein in the step of applying said heat treatment, the maximum temperature of said heat treatment is set at 800[deg.] C. or more and 2000[deg.] C. or less.

Images