JP6072851B2 - 半導体ウェーハをプラズマ・ダイシングする方法及び装置 - Google Patents
半導体ウェーハをプラズマ・ダイシングする方法及び装置 Download PDFInfo
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- JP6072851B2 JP6072851B2 JP2015093181A JP2015093181A JP6072851B2 JP 6072851 B2 JP6072851 B2 JP 6072851B2 JP 2015093181 A JP2015093181 A JP 2015093181A JP 2015093181 A JP2015093181 A JP 2015093181A JP 6072851 B2 JP6072851 B2 JP 6072851B2
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- H01L2221/683—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping
- H01L2221/68304—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support
- H01L2221/68327—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support used during dicing or grinding
-
- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
- Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y10S414/00—Material or article handling
- Y10S414/135—Associated with semiconductor wafer handling
- Y10S414/139—Associated with semiconductor wafer handling including wafer charging or discharging means for vacuum chamber
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- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Power Engineering (AREA)
- Computer Hardware Design (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Plasma & Fusion (AREA)
- Chemical & Material Sciences (AREA)
- Analytical Chemistry (AREA)
- Drying Of Semiconductors (AREA)
- Dicing (AREA)
- Container, Conveyance, Adherence, Positioning, Of Wafer (AREA)
- Plasma Technology (AREA)
Description
1)破損及び欠けが低減される。
2)20ミクロンを十分に下回るまで、ひき目寸法を低減させることができる。
3)ダイの数が増大しても、処理時間はあまり増大しない。
4)ウェーハが薄ければ薄いほど、処理時間が低減される。
5)ダイのトポロジは直線の形式に制限されない。
Claims (5)
- 基板をプラズマ・ダイシングする方法であって、
壁を有する処理チャンバを供給するステップと、
前記処理チャンバの前記壁に隣接してプラズマ源を供給するステップと、
前記処理チャンバ内に加工物支持部を供給するステップであって、前記加工物支持部がリフト機構と静電チャックを備え、該静電チャックは外径を有しているステップと、
上面と底面を有する前記基板を供給するステップであって、前記上面は複数のデバイス構造とストリート領域を有しているステップと、
上面と下面を有するフレームを供給するステップと、
加工物を形成するために、前記基板の前記底面を、支持フィルム上に配置して前記フレームの前記上面に配置するステップと、
前記加工物を前記加工物支持部の前記リフト機構上へ配置するステップであって、前記リフト機構は前記加工物の前記フレームの前記下面に接触しているステップと、
前記プラズマ源によってプラズマを生成するステップと、
前記生成されたプラズマによって前記加工物の前記基板の前記上面の保護されていない前記ストリート領域をエッチングするステップと
を含む方法。 - 前記支持フィルムが誘電体フィルムであり、前記静電チャックは100ミクロンよりも大きい厚さを有する誘電体をさらに含む、請求項1に記載の方法。
- 基板をプラズマ・ダイシングする方法であって、
壁を有する処理チャンバを供給するステップと、
前記処理チャンバの前記壁に隣接してプラズマ源を供給するステップと、
上面と底面を有する前記基板を供給するステップであって、前記上面は複数のデバイス構造とストリート領域を有しているステップと、
外径と上面と下面を有するフレームを供給するステップと、
加工物を形成するために、前記基板の前記底面を、支持フィルム上に配置して前記フレームの前記上面に配置するステップと、
前記処理チャンバ内に加工物支持部を供給するステップであって、前記加工物支持部がリフト機構と静電チャックを備え、該静電チャックは静電チャックの外径を有し、該静電チャックの外径は前記加工物の前記フレームの前記外径まで外側に延びているステップと、
前記加工物を前記加工物支持部の前記リフト機構上へ配置するステップであって、前記リフト機構は前記加工物の前記フレームの前記下面に接触しているステップと、
前記プラズマ源によってプラズマを生成するステップと、
前記生成されたプラズマによって前記加工物の前記基板の前記上面の保護されていない前記ストリート領域をエッチングするステップと
を含む方法。 - 前記支持フィルムが誘電体フィルムであり、前記静電チャックは100ミクロンよりも大きい厚さを有する誘電体をさらに含む、請求項3に記載の方法。
- 前記静電チャックが実質上共平面の表面をさらに有する、請求項3に記載の方法。
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US13/412,119 US8802545B2 (en) | 2011-03-14 | 2012-03-05 | Method and apparatus for plasma dicing a semi-conductor wafer |
US13/412,119 | 2012-03-05 |
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