JP5467506B2 - 樹脂封止型半導体装置及びその製造方法 - Google Patents
樹脂封止型半導体装置及びその製造方法 Download PDFInfo
- Publication number
- JP5467506B2 JP5467506B2 JP2009231140A JP2009231140A JP5467506B2 JP 5467506 B2 JP5467506 B2 JP 5467506B2 JP 2009231140 A JP2009231140 A JP 2009231140A JP 2009231140 A JP2009231140 A JP 2009231140A JP 5467506 B2 JP5467506 B2 JP 5467506B2
- Authority
- JP
- Japan
- Prior art keywords
- resin
- frame
- lead
- terminal
- terminal portion
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Lifetime
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Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/93—Batch processes
- H01L24/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
- H01L24/97—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
- H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/181—Encapsulation
Landscapes
- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Lead Frames For Integrated Circuits (AREA)
Description
2 リード
3 ダイパッド
4 半導体素子
5 端子部
6 金属細線
7 封止樹脂
10 リードフレーム
11 薄肉部
C モールドキャビティ
F フレーム
L グリッドリード
S 半導体装置
α カットライン
Claims (2)
- 複数のリードフレームが端子部を突設したグリッドリードを介してマトリックス状に配列されたフレームを用い、その各リードフレームにおける吊りリードで支持されたダイパッド上にそれぞれ半導体素子を配列し、それらの半導体素子を一括してモールドした後、各リードフレームの端子部を残すようにしてグリッドリードのところをダイシングソーで切断して個片化することにより製造されるノンリードタイプの樹脂封止型半導体装置であって、用いるフレームが、各端子部の付け根付近に表面又は裏面からハーフエッチング加工を施して端子部の幅方向全体にわたる薄肉部を形成したものであり、封止樹脂のカット面及び封止樹脂下面の端部に前記端子部が複数隣接して形成され、封止樹脂のカット面に露出する端子部の面積が端子部内部の断面より小さく形成され、隣接する端子部同士の間隔が近接しない状態に保たれていることを特徴とする樹脂封止型半導体装置。
- 複数のリードフレームが端子部を突設したグリッドリードを介してマトリックス状に配列されたフレームを用い、その各リードフレームにおける吊りリードで支持されたダイパッド上にそれぞれ半導体素子を配列し、それらの半導体素子を一括してモールドした後、各リードフレームの端子部を残すようにしてグリッドリードのところをダイシングソーで切断して個片化するノンリードタイプの樹脂封止型半導体装置を製造する方法において、各端子部の付け根付近に表面又は裏面からハーフエッチング加工を施して端子部の幅方向全体にわたる薄肉部を形成したフレームを用い、封止樹脂のカット面及び封止樹脂下面の端部に前記端子部が複数隣接して形成され、封止樹脂のカット面に露出する端子部の面積が端子部内部の断面より小さく形成され、隣接する端子部同士の間隔が近接しない状態に保たれているようにすることを特徴とする樹脂封止型半導体装置の製造方法。
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2009231140A JP5467506B2 (ja) | 2009-10-05 | 2009-10-05 | 樹脂封止型半導体装置及びその製造方法 |
Applications Claiming Priority (1)
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---|---|---|---|
JP2009231140A JP5467506B2 (ja) | 2009-10-05 | 2009-10-05 | 樹脂封止型半導体装置及びその製造方法 |
Related Parent Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP2000140008A Division JP4840893B2 (ja) | 2000-05-12 | 2000-05-12 | 樹脂封止型半導体装置用フレーム |
Related Child Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP2012257018A Division JP5585637B2 (ja) | 2012-11-26 | 2012-11-26 | 樹脂封止型半導体装置用フレーム |
Publications (2)
Publication Number | Publication Date |
---|---|
JP2010004080A JP2010004080A (ja) | 2010-01-07 |
JP5467506B2 true JP5467506B2 (ja) | 2014-04-09 |
Family
ID=41585471
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP2009231140A Expired - Lifetime JP5467506B2 (ja) | 2009-10-05 | 2009-10-05 | 樹脂封止型半導体装置及びその製造方法 |
Country Status (1)
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JP (1) | JP5467506B2 (ja) |
Families Citing this family (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP6738676B2 (ja) * | 2016-07-12 | 2020-08-12 | 株式会社三井ハイテック | リードフレーム |
JP2023039266A (ja) * | 2021-09-08 | 2023-03-20 | Towa株式会社 | 半導体装置の製造方法およびリードフレーム |
Family Cites Families (5)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP3304705B2 (ja) * | 1995-09-19 | 2002-07-22 | セイコーエプソン株式会社 | チップキャリアの製造方法 |
JP3209696B2 (ja) * | 1996-03-07 | 2001-09-17 | 松下電器産業株式会社 | 電子部品の製造方法 |
JPH1154663A (ja) * | 1997-08-04 | 1999-02-26 | Dainippon Printing Co Ltd | 樹脂封止型半導体装置とそれに用いられる回路部材、および回路部材の製造方法 |
JP3877410B2 (ja) * | 1997-12-26 | 2007-02-07 | 三洋電機株式会社 | 半導体装置の製造方法 |
JP3429246B2 (ja) * | 2000-03-21 | 2003-07-22 | 株式会社三井ハイテック | リードフレームパターン及びこれを用いた半導体装置の製造方法 |
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2009
- 2009-10-05 JP JP2009231140A patent/JP5467506B2/ja not_active Expired - Lifetime
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JP2010004080A (ja) | 2010-01-07 |
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