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ES8104879A1 - Dispositivo de particion temporal del acceso a una memoria principal - Google Patents

Dispositivo de particion temporal del acceso a una memoria principal

Info

Publication number
ES8104879A1
ES8104879A1 ES493412A ES493412A ES8104879A1 ES 8104879 A1 ES8104879 A1 ES 8104879A1 ES 493412 A ES493412 A ES 493412A ES 493412 A ES493412 A ES 493412A ES 8104879 A1 ES8104879 A1 ES 8104879A1
Authority
ES
Spain
Prior art keywords
access
main memory
bus
central computer
time sharing
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired
Application number
ES493412A
Other languages
English (en)
Other versions
ES493412A0 (es
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Jeumont Schneider SA
Original Assignee
Jeumont Schneider SA
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Jeumont Schneider SA filed Critical Jeumont Schneider SA
Publication of ES8104879A1 publication Critical patent/ES8104879A1/es
Publication of ES493412A0 publication Critical patent/ES493412A0/es
Granted legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/14—Handling requests for interconnection or transfer
    • G06F13/36—Handling requests for interconnection or transfer for access to common bus or bus system
    • G06F13/362—Handling requests for interconnection or transfer for access to common bus or bus system with centralised access control
    • G06F13/366—Handling requests for interconnection or transfer for access to common bus or bus system with centralised access control using a centralised polling arbiter

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Bus Control (AREA)
  • Multi Processors (AREA)
  • Small-Scale Networks (AREA)
  • Computer And Data Communications (AREA)

Abstract

DISPOSITIVO DE REPARTICION TEMPORAL DEL ACCESO A UNA MEMORIA PRINCIPAL ENTRE UN CONJUNTO DE CALCULADORES PERIFERICOS. A UNA BARRA (3) ESTAN CONECTADOS UN CALCULADOR CENTRAL (1) Y VARIOS PERIFERICOS (41, 42, 43), POR MEDIO DE ELLA TIENEN ACCESO A UNA MEMORIA (2), A LA QUE SOLO ESTA CONECTADO PERMANENTEMENTE EL CALCULADOR CENTRAL. UN DISPOSITIVO (5) DE ASIGNACION TEMPORAL DE CONEXION A LA MEMORIA (2), SE COMPONE DE UN CIRCUITO DE ESCRUTINIO (6), PARA VER QUE PERIFERICO QUIERE CONECTAR A LA MEMORIA (2), SE COMPONE DE UN CIRCUITO DE ESCRUTINIO (6), PARA VER QUE PERIFERICO QUIERE CONECTAR A LA MEMORIA (2), Y UN CIRCUITO DE ASIGNACION (7), CONECTADO AL CALCULADOR CENTRAL (1), ESTANDO ESTOS ELEMENTOS CONECTADOS ENTRE SI Y CON LOS PERIFERICOS (41, 42, 43) BIDIRECCIONALMENTE. I
ES493412A 1979-07-30 1980-07-16 Dispositivo de particion temporal del acceso a una memoria principal Granted ES493412A0 (es)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
FR7919505A FR2462745B1 (fr) 1979-07-30 1979-07-30 Dispositif de partage temporel de l'acces a une memoire connectee a un bus unique entre un calculateur central et une pluralite de calculateurs peripheriques

Publications (2)

Publication Number Publication Date
ES8104879A1 true ES8104879A1 (es) 1981-05-16
ES493412A0 ES493412A0 (es) 1981-05-16

Family

ID=9228411

Family Applications (1)

Application Number Title Priority Date Filing Date
ES493412A Granted ES493412A0 (es) 1979-07-30 1980-07-16 Dispositivo de particion temporal del acceso a una memoria principal

Country Status (25)

Country Link
US (1) US4611275A (es)
JP (1) JPS56500946A (es)
AR (1) AR228432A1 (es)
AT (1) AT385605B (es)
AU (1) AU544135B2 (es)
BE (1) BE884502A (es)
BR (1) BR8008770A (es)
CA (1) CA1172769A (es)
CH (1) CH640646A5 (es)
DD (1) DD152436A5 (es)
DE (1) DE3049774T1 (es)
ES (1) ES493412A0 (es)
FR (1) FR2462745B1 (es)
GB (1) GB2070826B (es)
HK (1) HK2685A (es)
IT (1) IT1129026B (es)
LU (1) LU82660A1 (es)
MA (1) MA18914A1 (es)
MX (1) MX147199A (es)
NL (1) NL8020243A (es)
OA (1) OA06591A (es)
SE (1) SE442352B (es)
SG (1) SG55084G (es)
WO (1) WO1981000468A1 (es)
ZA (1) ZA804217B (es)

Families Citing this family (20)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4574350A (en) * 1982-05-19 1986-03-04 At&T Bell Laboratories Shared resource locking apparatus
GB2170624B (en) * 1982-06-05 1987-06-10 British Aerospace Communication between computers
GB2123189B (en) * 1982-06-05 1987-06-10 British Aerospace Communication between computers
US4484273A (en) * 1982-09-03 1984-11-20 Sequoia Systems, Inc. Modular computer system
US4831358A (en) * 1982-12-21 1989-05-16 Texas Instruments Incorporated Communications system employing control line minimization
US4868742A (en) * 1984-06-20 1989-09-19 Convex Computer Corporation Input/output bus for system which generates a new header parcel when an interrupted data block transfer between a computer and peripherals is resumed
JPS61166668A (ja) * 1985-01-19 1986-07-28 Panafacom Ltd 多重プロセツサ制御方式
US4912627A (en) * 1985-08-14 1990-03-27 Apple Computer, Inc. Method for storing a second number as a command address of a first peripheral device and a third number as a command address of a second peripheral device
US4875158A (en) * 1985-08-14 1989-10-17 Apple Computer, Inc. Method for requesting service by a device which generates a service request signal successively until it is serviced
US4918598A (en) * 1985-08-14 1990-04-17 Apple Computer, Inc. Method for selectively activating and deactivating devices having same first address and different extended addresses
US4910655A (en) * 1985-08-14 1990-03-20 Apple Computer, Inc. Apparatus for transferring signals and data under the control of a host computer
JP2749819B2 (ja) * 1987-10-26 1998-05-13 松下電工株式会社 共有メモリ制御方式
US5293493A (en) * 1989-10-27 1994-03-08 International Business Machines Corporation Preemption control for central processor with cache
FR2654531A1 (fr) * 1989-11-13 1991-05-17 Diatech France Sarl Dispositif d'interconnection sur le meme bus de plusieurs microprocesseurs 16 bits.
FR2664772A1 (fr) * 1990-07-13 1992-01-17 Thomson Csf Reseau local d'intercommunication de modules de traitement de donnees.
SE9203016L (sv) * 1992-10-14 1994-04-15 Ericsson Telefon Ab L M Signalbehandlingssystem med delat dataminne
JP3615409B2 (ja) * 1999-01-29 2005-02-02 沖電気工業株式会社 パケット通信装置
US6374319B1 (en) 1999-06-22 2002-04-16 Philips Electronics North America Corporation Flag-controlled arbitration of requesting agents
US6675268B1 (en) * 2000-12-11 2004-01-06 Lsi Logic Corporation Method and apparatus for handling transfers of data volumes between controllers in a storage environment having multiple paths to the data volumes
CN100354849C (zh) * 2004-05-14 2007-12-12 凌阳科技股份有限公司 加强型可扩充分时总线架构

Family Cites Families (13)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
GB904334A (en) * 1959-02-04 1962-08-29 Int Computers & Tabulators Ltd Improvements in or relating to data handling equipment
US3289168A (en) * 1962-07-31 1966-11-29 Ibm Interrupt control system
US3629854A (en) * 1969-07-22 1971-12-21 Burroughs Corp Modular multiprocessor system with recirculating priority
FR2273317B1 (es) * 1974-05-28 1976-10-15 Philips Electrologica
US3959775A (en) * 1974-08-05 1976-05-25 Gte Automatic Electric Laboratories Incorporated Multiprocessing system implemented with microprocessors
NL7411989A (nl) * 1974-09-10 1976-03-12 Philips Nv Computersysteem met busstruktuur.
US4034347A (en) * 1975-08-08 1977-07-05 Bell Telephone Laboratories, Incorporated Method and apparatus for controlling a multiprocessor system
JPS5837585B2 (ja) * 1975-09-30 1983-08-17 株式会社東芝 ケイサンキソウチ
JPS5812611B2 (ja) * 1975-10-15 1983-03-09 株式会社東芝 デ−タテンソウセイギヨホウシキ
DE2546202A1 (de) * 1975-10-15 1977-04-28 Siemens Ag Rechnersystem aus mehreren miteinander verbundenen und zusammenwirkenden einzelrechnern und verfahren zum betrieb des rechnersystems
JPS5296836A (en) * 1976-02-10 1977-08-15 Toshiba Corp Multiplex data processing system
US4104720A (en) * 1976-11-29 1978-08-01 Data General Corporation CPU/Parallel processor interface with microcode extension
US4128876A (en) * 1977-04-28 1978-12-05 International Business Machines Corporation Synchronous microcode generated interface for system of microcoded data processors

Also Published As

Publication number Publication date
GB2070826B (en) 1984-05-16
ES493412A0 (es) 1981-05-16
JPS56500946A (es) 1981-07-09
AU6057580A (en) 1981-03-03
SG55084G (en) 1985-03-08
ZA804217B (en) 1981-07-29
BR8008770A (pt) 1981-05-26
FR2462745A1 (fr) 1981-02-13
HK2685A (en) 1985-01-18
GB2070826A (en) 1981-09-09
DD152436A5 (de) 1981-11-25
DE3049774C2 (es) 1988-09-01
DE3049774T1 (de) 1982-02-25
CA1172769A (fr) 1984-08-14
ATA907980A (de) 1987-09-15
SE442352B (sv) 1985-12-16
CH640646A5 (fr) 1984-01-13
MA18914A1 (fr) 1981-04-01
AU544135B2 (en) 1985-05-16
FR2462745B1 (fr) 1986-01-03
LU82660A1 (fr) 1980-10-24
IT8049247A0 (it) 1980-07-15
MX147199A (es) 1982-10-20
BE884502A (fr) 1980-11-17
NL8020243A (nl) 1981-06-16
AT385605B (de) 1988-04-25
OA06591A (fr) 1981-08-31
US4611275A (en) 1986-09-09
IT1129026B (it) 1986-06-04
AR228432A1 (es) 1983-03-15
SE8101979L (sv) 1981-03-27
WO1981000468A1 (fr) 1981-02-19

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