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JPS5672754A - Electronic computer system equipped with memory protecting device - Google Patents

Electronic computer system equipped with memory protecting device

Info

Publication number
JPS5672754A
JPS5672754A JP15044779A JP15044779A JPS5672754A JP S5672754 A JPS5672754 A JP S5672754A JP 15044779 A JP15044779 A JP 15044779A JP 15044779 A JP15044779 A JP 15044779A JP S5672754 A JPS5672754 A JP S5672754A
Authority
JP
Japan
Prior art keywords
memory
access
processors
data
computer system
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP15044779A
Other languages
Japanese (ja)
Inventor
Toshihiko Ohori
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Casio Computer Co Ltd
Original Assignee
Casio Computer Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Casio Computer Co Ltd filed Critical Casio Computer Co Ltd
Priority to JP15044779A priority Critical patent/JPS5672754A/en
Publication of JPS5672754A publication Critical patent/JPS5672754A/en
Pending legal-status Critical Current

Links

Landscapes

  • Storage Device Security (AREA)
  • Multi Processors (AREA)

Abstract

PURPOSE:To protect securely data in the submemory of the multiprocessor of an electronic computer by permitting the shared memory access operation of a control processor only when the access assignment range is within its access permissible range. CONSTITUTION:To control processors 1-3 differing in function, common memory 4 is connected via bus channel selector 5 and through memory 4, data processing is performed. To address bus line A4 and data bus line D4 of this computer system, memory protecting circuit 10 is connected and this circuit 10 is provided with upper limit latch circuits 111-113, lower limit latch circuits 121-123, upper limit address comparator 16, low limit address comparator 17, etc. Then, the address assignment range accessed by processors 1-3 is compared with that presets for the processors and only when the assignment range is within the permissible range, access to memory 4 is permitted, thereby preventing data in memory 4 from being destroyed.
JP15044779A 1979-11-20 1979-11-20 Electronic computer system equipped with memory protecting device Pending JPS5672754A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP15044779A JPS5672754A (en) 1979-11-20 1979-11-20 Electronic computer system equipped with memory protecting device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP15044779A JPS5672754A (en) 1979-11-20 1979-11-20 Electronic computer system equipped with memory protecting device

Publications (1)

Publication Number Publication Date
JPS5672754A true JPS5672754A (en) 1981-06-17

Family

ID=15497127

Family Applications (1)

Application Number Title Priority Date Filing Date
JP15044779A Pending JPS5672754A (en) 1979-11-20 1979-11-20 Electronic computer system equipped with memory protecting device

Country Status (1)

Country Link
JP (1) JPS5672754A (en)

Cited By (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4757441A (en) * 1985-02-28 1988-07-12 International Business Machines Corporation Logical arrangement for controlling use of different system displays by main proessor and coprocessor
JPS6488602A (en) * 1987-09-29 1989-04-03 Matsushita Electric Ind Co Ltd Method for originating data
US4833596A (en) * 1985-02-28 1989-05-23 International Business Machines Corporation Logical arrangement for controlling use of different system displays by main processor and co-processor
WO2006022161A1 (en) * 2004-08-25 2006-03-02 Nec Corporation Information communication device, and program execution environment control method
US20160004647A1 (en) * 2013-02-28 2016-01-07 Siemens Aktiengesellschaft Method and circuit arrangement for accessing slave units in a system on chip in a controlled manner

Cited By (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4757441A (en) * 1985-02-28 1988-07-12 International Business Machines Corporation Logical arrangement for controlling use of different system displays by main proessor and coprocessor
US4833596A (en) * 1985-02-28 1989-05-23 International Business Machines Corporation Logical arrangement for controlling use of different system displays by main processor and co-processor
JPS6488602A (en) * 1987-09-29 1989-04-03 Matsushita Electric Ind Co Ltd Method for originating data
WO2006022161A1 (en) * 2004-08-25 2006-03-02 Nec Corporation Information communication device, and program execution environment control method
US8640194B2 (en) 2004-08-25 2014-01-28 Nec Corporation Information communication device and program execution environment control method
US20160004647A1 (en) * 2013-02-28 2016-01-07 Siemens Aktiengesellschaft Method and circuit arrangement for accessing slave units in a system on chip in a controlled manner

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